KR900000607B1 - Circuit for dividing dmac channel request - Google Patents

Circuit for dividing dmac channel request Download PDF

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Publication number
KR900000607B1
KR900000607B1 KR1019860011210A KR860011210A KR900000607B1 KR 900000607 B1 KR900000607 B1 KR 900000607B1 KR 1019860011210 A KR1019860011210 A KR 1019860011210A KR 860011210 A KR860011210 A KR 860011210A KR 900000607 B1 KR900000607 B1 KR 900000607B1
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South Korea
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signal
dmac
dma
circuit
channel request
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KR1019860011210A
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Korean (ko)
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KR880008165A (en
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유관섭
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주식회사 금성사
구자학
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

The circuit includes; a DMAC channel request Daisy Chain Circuit (40) for generating and supplying DMAC request signal to a DMAC (10) when one or more DMAC request signal is generated in devices (4-1,-,4-4), for classifying acknowledgement signal(ACK4) according to the classes of the acknowledgement signals, (DACK1DACK4), and for supplying the classified signal to the devices (4-1,-,4-4); a device address decoder (50) for generating and supplying chip enable signals (DCE1- DCE4) to the device utilizing the acknowledgement signals and the address signals (A1-A23); and a memory access address modifier (60) for generating memory address signals (MA1-MA23) utilizing the acknowlidgement signal and the address signal.

Description

DMAC 채널요구 분할회로DMAC channel request split circuit

제1도는 본 발명의 동작설명을 위한 전체블록구성도.1 is a block diagram illustrating the operation of the present invention.

제2도는 본 발명의 블록구성도.2 is a block diagram of the present invention.

제3도는 본 발명에서의 DMAC채널요구 데이지체인회로도.3 is a DMAC channel request daisy chain circuit diagram of the present invention.

제4도는 디바이스의 DMAC채널요구 회로도.4 is a DMAC channel request circuit diagram of a device.

* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings

1, 2, 3, 4-1, 4-2, 4-3, 4-4 : 디바이스1, 2, 3, 4-1, 4-2, 4-3, 4-4: device

10 : DMAC 20 : 데이터 및 어드레스버스멀티플렉서10: DMAC 20: Data and Address Bus Multiplexer

30 : DMAC 채널요구분할회로 40 : DMAC 채널요구 데이지 체인회로30: DMAC channel request splitting circuit 40: DMAC channel request daisy chain circuit

60 : 메모리액세스어드레스모디파이어60: memory access address modifier

71-74 : DMA채널요구회로 U1, U2 : DMA채널요구집적회로71-74: DMA channel request circuit U1, U2: DMA channel request integrated circuit

A1-A4 :앤드게이트 I1 : 인버터A1-A4: Andgate I1: Inverter

N1 : 낸드게이트N1: NAND Gate

본 발명은 DMAC(직접 메모리 액세스 채널)의 채널요구 분할회로에 관한 것으로서, 특히 컴퓨터장치에 적용할 수 있게한 채널요구 분할회로에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to channel request splitting circuits for DMAC (Direct Memory Access Channels), and more particularly to channel request splitting circuits that can be applied to computer devices.

종래의 DMAC는 DMA(직접 메모리 액세스)동작을 요구하는디바이스를 4개까지 밖에는 부착할 수가 없고, 또한 어느한 순간의 DMA동작은 단지 1채널에 대하여서만 DMA동작을 하게된다.The conventional DMAC can only attach up to four devices that require DMA (direct memory access) operation, and at any one time, the DMA operation is performed only for one channel.

따라서, 4개 이상의 DMA동작을 요구하는 디바이스가 있으면, DMAC를 2개 사용해야만 하므로 이에따라 제품코스트가 상승되는 문제점이 있었다.Therefore, if there is a device requiring four or more DMA operations, two DMACs must be used, resulting in a rise in product cost.

본 발명은 이와 같은 종래의 문제점을 감안하여 4채널 밖에 존재하지 아니하는 DMAC에 7채널까지의 DMA요구를 할 수 있도록 하여 DMAC의 칩을 단일로 축소하고, 또한 DMA동작를 빠른 동작으로 처리할 수 있도록 함을 목적으로 한다.In view of the above-mentioned problems, the present invention enables the DMAC which has only four channels to make DMA requests up to seven channels, thereby reducing the chip of the DMAC to a single size and processing the DMA operation in a fast operation. For the purpose of

본 발명을 첨부한 도면에 따라서 상세히 설명하면 다음과 같다.The present invention will be described in detail with reference to the accompanying drawings as follows.

제1도는 본 발명의 동작설명을 위한 전체블록구성도로서, DMAC(10)와, 데이터 및 어드레스버스밀티플렉서(20)와, DMAC채널요구분할회로(30)와, 디바이스(1, 2, 3, 4-1, 4-2, 4-3, 4-4)로 구성된다.1 is an overall block diagram for explaining the operation of the present invention. The DMAC 10, the data and address bus tight multiplexer 20, the DMAC channel request splitting circuit 30, the devices 1, 2, 3, 4-1, 4-2, 4-3, 4-4).

제2도는 상기 제1도의 DMAC채널요구분할회로(30)의 상세블록도로서 이에 도시한 바와 같이, DMAC채널요구데이지체인(Daisy Chain)회로(40)와, 디바이스어드레스디코오더(50)와, 메모리액세스어드레스모디파이어(Memory Access Address Modifier)(60)로서 구성된다.2 is a detailed block diagram of the DMAC channel request splitting circuit 30 of FIG. 1, as shown therein, a DMAC channel request chain chain 40, a device address decoder 50, It is configured as a memory access address modifier 60.

제3도는 제2도의 DMAC채널요구데이지체인회로(40)의 상세회로도로서 이에 도시한 바와 같이 DMAC의 1채널에 4개의 DMA동작을 요구하는 DMA채널요구회로(71-74) 및 앤드게이트(A1-A3)로 구성되어져 있다.FIG. 3 is a detailed circuit diagram of the DMAC channel request chain circuit 40 of FIG. 2. As shown therein, the DMA channel request circuits 71-74 and the AND gate (A1) requesting four DMA operations on one channel of the DMAC. -A3).

또한, 데이지체인을 보다 빠르게 작동시키기 위하여 앤드게이트(1)를 사용하여 록어헤드데이지체인(Look Ahead Daisy-Chain)회로를 구성하였다.In addition, in order to operate the daisy chain faster, a lock ahead daisy-chain circuit was constructed using the end gate 1.

디바이스어드레스디코오더(50)는 DMAC가 할당된 채널에 대한 디바이스 어드레스를 출력하면, 이것을 각 디바이스(4-1)(4-2)(4-3)(4-4)에 대한 DMA요구의 인식신호를 참고하여 4개의 디바이스를 선택할 수 있도록 하는 칩인에이블신호(Chip Enable signal)(

Figure kpo00001
)를 발생시키는 회로이다.When the device address decoder 50 outputs the device address for the channel to which the DMAC is assigned, the device address decoder 50 recognizes the DMA request for each of the devices 4-1, 4-2, 4-3, and 4-4. Chip Enable signal that allows you to select four devices by referring to the signal (
Figure kpo00001
) Is a circuit that generates.

메모리액세스어드레스모디파이어(60)는 각 디바이스(4-1)(4-2)(4-3)(4-4)가 각각 다른 메모리영역으로 데이터를 전송한 경우에 DMAC 에서 출력되는 메모리 액세스 어드레스를 수정하여 어드레스를 밸생시키는 회로이다.The memory access address modifier 60 stores the memory access addresses output from the DMAC when the devices 4-1, 4-2, 4-3, and 4-4 each transmit data to different memory areas. It is a circuit that corrects an address to correct it.

이와 같이 구성된 본 발명의 작용효과를 상세히 설명하면 다음과 같다.Referring to the effects of the present invention configured as described above in detail.

DMAC(10)의 1채널에 4개의 디바이스(4-1, 4-2, 4-3, 4-4)가 DMA동작을 요구할 경우에, 우선 각 디바이스(4-1, 4-2, 4-3, 4-4)가 DMAC 동작을 요구할 경우에, 우선 각 디바이스(4-1, 4-2, 4-3, 4-4)에서는 DMA요구신호(

Figure kpo00002
)를 로우상태로 되게한다. 그러면, 제3도에 도시된 4입력앤드게이트(A1)를 통하여 DMAC(10)에 DMA요구신호(
Figure kpo00003
)가 인가된다. 그 다음에 DMAC(10)에는 DMA요구신호(
Figure kpo00004
)에 대한 인식신호(
Figure kpo00005
)를 발생시킨다. 이때에 DMAC채널요구데이지체인회로(40)에서 순위를 결정하여 높은순위[디바이스(4-1)가 가장 높고, 디바이스(4-4)가 가장 낮음]에 해당하는 디바이스에 인식신호(
Figure kpo00006
)를 발생시키게 된다.When four devices 4-1, 4-2, 4-3, and 4-4 request DMA operation on one channel of the DMAC 10, each device 4-1, 4-2, 4- is first. When 3, 4-4 requests DMAC operation, first, each device 4-1, 4-2, 4-3, 4-4 has a DMA request signal (
Figure kpo00002
To low). Then, the DMA request signal to the DMAC 10 through the four input and gate A1 shown in FIG.
Figure kpo00003
) Is applied. DMAC 10 then transmits a DMA request signal (
Figure kpo00004
Recognition signal for
Figure kpo00005
). At this time, the DMAC channel request daisy-chain circuit 40 determines the rank and recognizes the recognition signal (
Figure kpo00006
) Will be generated.

제4도에서 인식신호(

Figure kpo00007
)가 저전위 상태로 인가되면, 인버터(I1)를 통하여 고전위 신호로 반전되어 DMA채널요구 집적회로(U1)의 클럭단자(CLK)에 인가되므로 그 DMA채널요구 집적회로(U1)의 출력단자(
Figure kpo00008
)신호는 DMA요구신호(
Figure kpo00009
)의 상태에 따라 결정된다.In Figure 4 the recognition signal (
Figure kpo00007
Is applied to the clock terminal CLK of the DMA channel request integrated circuit U1 through the inverter I1, and is output to the clock terminal CLK of the DMA channel request integrated circuit U1. (
Figure kpo00008
) Signal is the DMA request signal (
Figure kpo00009
) Is determined by the state.

한편, 상기 인식신호(

Figure kpo00010
)에 의하여 DMA채널요구집적회로(U1)가 클럭킹된후에 지연회로(80)에 의해 30ns경과할때 다시 DMA채널요구집적회로(U2)가 클럭킹되며, 이 DMA채널요구집적회로(U2)의 출력단자(Q), (
Figure kpo00011
)신호는 상기 DMA채널요구집적회로(U1)의 출력단자(
Figure kpo00012
)신호에 의해 결정된다.On the other hand, the recognition signal (
Figure kpo00010
After the DMA channel request integrated circuit U1 is clocked by the delay circuit 80, the DMA channel request integrated circuit U2 is clocked again, and the output of the DMA channel request integrated circuit U2 is Terminal (Q), (
Figure kpo00011
Signal is output terminal of the DMA channel request integrated circuit U1.
Figure kpo00012
Is determined by the signal.

즉, DMA요구신호(

Figure kpo00013
)가 로우상태일때 인식신호(
Figure kpo00014
)가 저전위 액티브가 되면, DMA채널요구집적회로(U1)의 출력단자(
Figure kpo00015
)신호가 하이상태가 되며, 지연회로(80)를 통하여 30ns지연후에 다시 DMA채널요구집적회로(U2)가 클럭킹되어 그 DMA채널요구집적회로(U2)의 출력단자(Q)신호는 고전위 상태로 되고, 출력단자(
Figure kpo00016
)신호는 저전위 상태로 된다.That is, the DMA request signal (
Figure kpo00013
Signal is low when
Figure kpo00014
When the low potential becomes active, the output terminal of the DMA channel request integrated circuit U1 (
Figure kpo00015
Signal goes high, and after a delay of 30 ns through the delay circuit 80, the DMA channel request integrated circuit U2 is clocked again so that the output terminal Q signal of the DMA channel request integrated circuit U2 is in a high potential state. Output terminal (
Figure kpo00016
Signal becomes a low potential state.

데이지체인회로(40)의 입력신호(

Figure kpo00017
) 와 출력신호(
Figure kpo00018
)가 적어도 30ns후에는 하이 또는 로우상태로 결정되어 있으므로 DMA채널요구집적회로(U2)의 출력단자(Q)신호와 입력신호(
Figure kpo00019
)에 의해 인식신호
Figure kpo00020
를 결정하게 된다. 또한 입력신호(
Figure kpo00021
)는 앞단의 입력신호(
Figure kpo00022
)의 결과에 따라 변환된다. 만일, 디바이스에서DMA의 요구가 있고, 입력신호(
Figure kpo00023
)가 하이상태이고 인식신호(
Figure kpo00024
)가 입력되었으면, 그때 해당되는 디바이스에 인식신호(
Figure kpo00025
)를 저전위 액티브로 하여 주며, 출력신호(
Figure kpo00026
)는 로우액티브로 만들어 준다.Input signal of the daisy chain circuit 40
Figure kpo00017
) And output signal (
Figure kpo00018
) Is determined to be high or low after at least 30 ns, so that the output terminal Q and the input signal of the DMA channel request integrated circuit U2 are
Figure kpo00019
Recognition signal by
Figure kpo00020
Will be determined. In addition, the input signal (
Figure kpo00021
) Is the front input signal (
Figure kpo00022
Is converted according to the result of If there is a demand for DMA in the device,
Figure kpo00023
) Is high and the recognition signal (
Figure kpo00024
) Is input, then the recognition signal (
Figure kpo00025
) To low potential active and output signal (
Figure kpo00026
) Makes it low active.

또한, DMAC(10)가 데이터 전송을 완료시에 출력되는 신호(

Figure kpo00027
)가 저전위 액티브이면, 데이터 전송의 완료를 나타내는 신호이므로 그 신호(
Figure kpo00028
)가 저전위 상태일때 DMA채널요구집적회로(U2)가 클리어되어 인식신호(
Figure kpo00029
)를 고전위상태로 만들어주게 되고, 또한 출력신호(
Figure kpo00030
)도 고전위 상태로 된다.In addition, the signal output when the DMAC 10 completes data transmission (
Figure kpo00027
) Is a low-potential active signal, indicating that the data transfer is complete.
Figure kpo00028
DMA channel request integrated circuit U2 is cleared when the
Figure kpo00029
) To the high potential state and the output signal (
Figure kpo00030
) Is also in a high potential state.

한편, 디바이스(1, 2, 3)에서 요구신호(

Figure kpo00031
)가 발생된 경우에는 DMAC(10)에서 그를 인식하여 그에 대응하는 인식신호(
Figure kpo00032
)를 디바이스(1, 2, 3)에 직접 인가하여 제어하게 된다.On the other hand, the request signal from the devices 1, 2, 3 (
Figure kpo00031
) Is generated, the DMAC 10 recognizes it and the corresponding recognition signal (
Figure kpo00032
) Is directly applied to the devices 1, 2, 3 to control.

한편, 상기에서와 같이 DMAC채널요구분할회로(3)의 DMA요구신호(

Figure kpo00033
)에 의해 DMAC(10)에서 로칼버스를 제어하게 되는 상태에서는 그 자신의 제어상태를 나타내는 신호(
Figure kpo00034
)를 DMAC 채널요구분할회로(30)의 디바이스어드레스디코오더(50) 및 메모리액세스어드레스모디파이어(60)에 인가하게 된다.On the other hand, as described above, the DMA request signal of the DMAC channel request splitting circuit 3 (
Figure kpo00033
In the state where the local bus is controlled by the DMAC 10 by
Figure kpo00034
) Is applied to the device address decoder 50 and the memory access address modifier 60 of the DMAC channel request splitting circuit 30.

한편, 상기에서와 같이 디바이스(4-1, 4-2, 4-3, 4-4)의 DMA요구신호(

Figure kpo00035
)에 의해 DMAC(10)의 채널을 요구할 경우에는 DMAC채널요구데이지체인회로(40)의 데이지체인에 의해 DMA요구신호(
Figure kpo00036
)를 발생하여 DMAC(10)에 인가하게 되고, 이때 DMAC(10)는 그 DMA요구신호(
Figure kpo00037
)에 대한 인식신호(
Figure kpo00038
)를 발생하여 DMAC채널요구데이지체인회로(40)에 인가하게 되므로 그 DMAC채널요구데이지체인회로(40)에서는 원래의 인식신호(
Figure kpo00039
)를 발생하여 된다. 즉, DMAC(10)입장에서는 하나의 DMA요구신호(
Figure kpo00040
)에 대한 인식신호(
Figure kpo00041
)를 발생하므로, DMAC채널요구데이지체인회로(40)에는 그 DMA요구신호(
Figure kpo00042
)를 발생할때의 원래의 DMA요구신호(
Figure kpo00043
)에 따라 분류하여 인식신호(
Figure kpo00044
)에 따라 분류하여 인식신호(
Figure kpo00045
)를 디바이스(4-1, 4-2, 4-3, 4-4)에 인가하여야 된다. 또한, 이때 디바이스어드레스디코더(50)에 의해 디바이스(4-1, 4-2, 4-3, 4-4)를 선택하기 위한 칩인에이블신호(
Figure kpo00046
)를 분류하게 되고, 메모리액세스 어드레스모디파이어(60)에 의해 메모리어드레스(MA01-MA23)를 분류하게 된다.On the other hand, as described above, the DMA request signal of the devices 4-1, 4-2, 4-3, 4-4 (
Figure kpo00035
In the case of requesting the channel of the DMAC 10 by means of the DMA request signal by the daisy chain of the DMAC channel request daisy chain circuit 40,
Figure kpo00036
) Is applied to the DMAC (10), where the DMAC (10) is the DMA request signal (
Figure kpo00037
Recognition signal for
Figure kpo00038
) Is applied to the DMAC channel request daisy chain circuit 40, the DMAC channel request daisy chain circuit 40 generates the original recognition signal (
Figure kpo00039
Is generated. That is, in the DMAC 10, one DMA request signal (
Figure kpo00040
Recognition signal for
Figure kpo00041
), The DMAC channel request daisy chain circuit 40 has its DMA request signal (
Figure kpo00042
Original DMA request signal when
Figure kpo00043
) According to the recognition signal (
Figure kpo00044
) According to the recognition signal (
Figure kpo00045
) Shall be applied to the devices 4-1, 4-2, 4-3, 4-4. In this case, the chip enable signal for selecting the devices 4-1, 4-2, 4-3, and 4-4 by the device address decoder 50 (
Figure kpo00046
) Are classified, and the memory addresses MA01 to MA23 are classified by the memory access address modifier 60.

이상에서 상세히 설명한 바와 같이 4채널 밖에 존재하지 아니하는 DMAC에 7개의 디바이스에서 DMA요구를 할 수 있게되므로 DMAC칩을 2개 사용할 경우를 1개로 감소시킬 수 있게되고, 또한 DMA동작이 빠른속도로 이루어질때는 더욱 효과적인 이점이 있게 된다.As described in detail above, DMA requests can be made from seven devices to a DMAC having only four channels, thereby reducing the use of two DMAC chips to one, and the DMA operation can be performed at a high speed. There is a more effective advantage.

Claims (1)

디바이스(1,2,3)의 DMA요구신호(
Figure kpo00047
)에 따라 DMAC(10)에서 인식신호(
Figure kpo00048
)를 그 디바이스(1,2,3)에 인가하고 한 DMAC채널요구회로에 있어서, 디바이스(4-1, 4-2, 4-3, 4-4)에서 DMA요구신호(
Figure kpo00049
)가 하나라도 발생될 경우에 DMA요구신호(
Figure kpo00050
)를 발생하여 상기 DMAC(10)에 인가하고, 그 DMAC(10)에서 그 DMA요구신호(
Figure kpo00051
)에 따른 인식신호(
Figure kpo00052
)가 출력될때에 상기 원래의 DMA요구신호(
Figure kpo00053
)에 따른 인식신호(
Figure kpo00054
)로 분류하여 상기 디바이스(4-1, 4-2, 4-3, 4-4)에 인가하는 DMAC채널요구데이지체인회로(40)와, 상기 인식신호(
Figure kpo00055
) 및 어드레스신호(A01-A23)에 의해 칩인에이블신호(
Figure kpo00056
)를 발생하여 상기 디바이스(4-1, 4-2, 4-3, 4-4)에 인가하는 디바이스어드레스디코오더(50)와, 상기 인식신호(
Figure kpo00057
) 및 어드레스신호(A01-A23)에 의해 메모리어드레스신호(MA01-MA23)를 발생하여 출력하는 메모리액세스어드레스모디파이어(60)로 구성하여 된 것을 특징으로 하는 DMAC채널요구분할회로.DMA request signal of the devices 1, 2, 3
Figure kpo00047
) By the DMAC 10
Figure kpo00048
) Is applied to the devices 1, 2, and 3, and in one DMAC channel request circuit, the DMA request signal (
Figure kpo00049
DMA request signal (if any)
Figure kpo00050
) Is applied to the DMAC 10, and the DMA request signal (
Figure kpo00051
Recognition signal according to
Figure kpo00052
Is outputted, the original DMA request signal (
Figure kpo00053
Recognition signal according to
Figure kpo00054
And the DMAC channel request daisy chain circuit 40 to be applied to the devices 4-1, 4-2, 4-3, 4-4, and the recognition signal
Figure kpo00055
) And the chip enable signal (A01-A23)
Figure kpo00056
) And a device address decoder 50 for applying to the devices 4-1, 4-2, 4-3, 4-4, and the recognition signal (
Figure kpo00057
And a memory access address modulator (60) which generates and outputs a memory address signal (MA01-MA23) by means of an address signal (A01-A23).
KR1019860011210A 1986-12-24 1986-12-24 Circuit for dividing dmac channel request KR900000607B1 (en)

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Application Number Priority Date Filing Date Title
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Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1019860011210A KR900000607B1 (en) 1986-12-24 1986-12-24 Circuit for dividing dmac channel request

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KR880008165A KR880008165A (en) 1988-08-30
KR900000607B1 true KR900000607B1 (en) 1990-02-01

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