RU93052382A - SYSTEM OF ORDERING OF THE ELEMENTS FOR THE PERFORCEABLE PART OF THE TELECOMMUNICATION NETWORK AND METHOD OF PHASE CORRELATION OF THE FIRST TIMER FACILITIES - Google Patents

SYSTEM OF ORDERING OF THE ELEMENTS FOR THE PERFORCEABLE PART OF THE TELECOMMUNICATION NETWORK AND METHOD OF PHASE CORRELATION OF THE FIRST TIMER FACILITIES

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Publication number
RU93052382A
RU93052382A RU93052382/09A RU93052382A RU93052382A RU 93052382 A RU93052382 A RU 93052382A RU 93052382/09 A RU93052382/09 A RU 93052382/09A RU 93052382 A RU93052382 A RU 93052382A RU 93052382 A RU93052382 A RU 93052382A
Authority
RU
Russia
Prior art keywords
value
time
delay
timer
inputs
Prior art date
Application number
RU93052382/09A
Other languages
Russian (ru)
Other versions
RU2142204C1 (en
Inventor
Альбер Жулиа Верий Анри
Андре Робер Анрион Мишель
Филемон Мадлен Де Соме Мишель
Жозеф Жерар Паувелс Барт
Original Assignee
Белл Телефон Мануфакчуринг Кампани Н.В.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from EP92202866A external-priority patent/EP0587944B1/en
Application filed by Белл Телефон Мануфакчуринг Кампани Н.В. filed Critical Белл Телефон Мануфакчуринг Кампани Н.В.
Publication of RU93052382A publication Critical patent/RU93052382A/en
Application granted granted Critical
Publication of RU2142204C1 publication Critical patent/RU2142204C1/en

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Claims (1)

Система переупорядочения элементов для переупорядочивающей части (RS), имеющей два входа (SIn), связанных с вводами (12n) схемы переключений (SN2) через линии передач (TLn), организованных в группу линий (LG). Элементы, передающиеся от входов к выводам (N2m) схемы переключений, подвергаются первой переменной временной задержке и затем сохраняются в средствах фиксации состояний (R2m) для второй переменной временной задержки до выпуска к выходу части. Вторая задержка выбирается таким образом, что для каждого элемента сумма первой и второй задержек по существу равна предварительно определенному постоянному временному значению. Размер средств фиксации состояний определяется разностью между предварительно определенным постоянным временным значением и фиксированной задержкой передачи (TD), ниже которой никакой элемент передаваться от входа к выводу не может. Также предлагается метод фазовой корреляции двух таймерных средств (СК1/2), выдающих значения отметок времени (tA1, tA2/tB). Первые таймерные средства посылают первое значение отметки времени (tA1) вторым таймерным средствам (СК2), которые выдают второе значение отметки времени (tB). Затем в месте (А/В) либо первых, либо вторых таймерных средств определяется значение коррекции отметок времени (ТТС), равное разности между вторым и первым значениями отметок времени. Это значение коррекции отметок времени является функцией разности фаз между двумя тактовыми средствами и фиксированной задержки передачи (TD).An element reordering system for a reordering part (RS) having two inputs (SIn) connected to inputs (12n) of a switching circuit (SN2) via transmission lines (TLn) organized into a group of lines (LG). Elements transmitted from the inputs to the outputs (N2m) of the switching circuit are subjected to the first variable time delay and then stored in the state latching means (R2m) for the second variable time delay before being released to the output part. The second delay is selected in such a way that for each element the sum of the first and second delays is essentially equal to a predefined constant time value. The size of the state-fixation means is determined by the difference between a predefined constant time value and a fixed transfer delay (TD), below which no element can be passed from input to output. It also proposes a method of phase correlation of two timer means (CK1 / 2), issuing the values of time stamps (tA1, tA2 / tB). The first timer means send the first value of the time stamp (tA1) to the second timer tools (CK2), which give the second value of the time stamp (tB). Then, in the place (A / B) of either the first or second timer means, the correction value of the time stamps (TTC) is determined, which is equal to the difference between the second and the first values of the time stamps. This timestamp correction value is a function of the phase difference between the two clock means and the fixed transmission delay (TD).
RU93052382A 1992-09-18 1993-09-17 System for reordering elements for reordering part of telecommunication network RU2142204C1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP92202866.7 1992-09-18
EP92202866A EP0587944B1 (en) 1992-09-18 1992-09-18 Cell resequencing system for a telecommunication network

Publications (2)

Publication Number Publication Date
RU93052382A true RU93052382A (en) 1996-04-10
RU2142204C1 RU2142204C1 (en) 1999-11-27

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Family Applications (1)

Application Number Title Priority Date Filing Date
RU93052382A RU2142204C1 (en) 1992-09-18 1993-09-17 System for reordering elements for reordering part of telecommunication network

Country Status (9)

Country Link
US (1) US5491728A (en)
EP (1) EP0587944B1 (en)
JP (1) JPH06205476A (en)
CN (1) CN1046071C (en)
AU (2) AU671472B2 (en)
CA (1) CA2106418A1 (en)
DE (1) DE69225592T2 (en)
ES (1) ES2115636T3 (en)
RU (1) RU2142204C1 (en)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI104672B (en) * 1997-07-14 2000-04-14 Nokia Networks Oy A clutch assembly
US6246684B1 (en) * 1997-12-24 2001-06-12 Nortel Networks Limited Method and apparatus for re-ordering data packets in a network environment
JP3616247B2 (en) * 1998-04-03 2005-02-02 株式会社アドバンテスト Skew adjustment method in IC test apparatus and pseudo device used therefor
KR100279949B1 (en) * 1998-12-28 2001-02-01 윤종용 Cell rearrangement buffer
US6728211B1 (en) * 2000-03-07 2004-04-27 Cisco Technology, Inc. Method and apparatus for delaying packets being sent from a component of a packet switching system
US6907041B1 (en) * 2000-03-07 2005-06-14 Cisco Technology, Inc. Communications interconnection network with distributed resequencing
US6757284B1 (en) * 2000-03-07 2004-06-29 Cisco Technology, Inc. Method and apparatus for pipeline sorting of ordered streams of data items
US6359888B1 (en) * 2000-07-05 2002-03-19 Coactive Networks, Inc. Method for detecting invalid packets by rewriting transaction identifers
US6832261B1 (en) 2001-02-04 2004-12-14 Cisco Technology, Inc. Method and apparatus for distributed resequencing and reassembly of subdivided packets
US6934760B1 (en) * 2001-02-04 2005-08-23 Cisco Technology, Inc. Method and apparatus for resequencing of packets into an original ordering using multiple resequencing components
US7092393B1 (en) 2001-02-04 2006-08-15 Cisco Technology, Inc. Method and apparatus for distributed reassembly of subdivided packets using multiple reassembly components
GB0118196D0 (en) 2001-07-26 2001-09-19 Zarlink Semiconductor Ltd Apparatus for switching time division multiplex channels
KR100747464B1 (en) 2002-01-05 2007-08-09 엘지전자 주식회사 Timer based Stall Avoidance method in HSDPA system
US6717927B2 (en) 2002-04-05 2004-04-06 Interdigital Technology Corporation System for efficient recovery of node B buffered data following serving high speed downlink shared channel cell change
US7706405B2 (en) * 2002-09-12 2010-04-27 Interdigital Technology Corporation System for efficient recovery of Node-B buffered data following MAC layer reset
US7289508B1 (en) * 2003-03-12 2007-10-30 Juniper Networks, Inc. Systems and methods for processing any-to-any transmissions
US7586917B1 (en) 2003-09-30 2009-09-08 Juniper Networks, Inc. Systems and methods for re-ordering data in distributed data forwarding
DE102004018200A1 (en) * 2004-04-15 2005-11-10 Deutsche Thomson-Brandt Gmbh A method for processing a sequence of data packets in a receiver device and receiver device
WO2009035091A1 (en) * 2007-09-14 2009-03-19 Nec Corporation Clock synchronization system, its method and program
US8423468B2 (en) * 2008-07-07 2013-04-16 Telefonaktiebolaget L M Ericsson (Publ) Real time correlation of parallel charging events
CN105230089B (en) 2013-01-31 2019-05-03 马维尔国际贸易有限公司 Method and communication equipment for clock compensation
CN103973592B (en) * 2014-05-16 2017-12-05 华为技术有限公司 Cell processing method and processing device

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE68920748T2 (en) * 1989-08-09 1995-06-29 Alcatel Nv SEQUENTIAL RETURN FOR A INTERMITTENT NODE.
EP0519954B1 (en) * 1990-03-16 1995-09-27 Newbridge Networks Corporation Digital data transmission system
FR2661297B1 (en) * 1990-04-18 1993-02-12 Alcatel Radiotelephone CLOCK SIGNAL MULTIPLEXING CIRCUIT.
US5177739A (en) * 1990-04-20 1993-01-05 Racal Data Communications, Inc. Multiport - multipoint digital data service
US5347512A (en) * 1993-09-17 1994-09-13 Rockwell International Corporation Telecommunication system with delay data buffer and method

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