RU92586U1 - MULTI-CHANNEL ANALOG-DIGITAL SIGNAL CONVERTER - Google Patents

Abstract

Multichannel analog-to-digital converter (ADC) of signals, consisting of sequentially connected multichannel key time sampler of speech signals, performing amplitude-pulse modulation of AIM-1, a compressor of the reading level, converter AIM-1 to AIM-2, signal encoder, shift register with a clock pulse generator connected to its second input, as well as a distribution line, which includes a pulse generator, first connected to the control inputs of the sampler keys a pulse counter, a decoder, and the output of the pulse generator is also connected directly to the second input of the encoder and to the second input of the AIM-1 to AIM-2 converter through the first time delay unit, characterized in that a half-wave rectifier of speech samples, RS -trigger, two time delay blocks, two coincidence circuits AND, a second pulse counter, a 2I-NOT circuit, a differentiating circuit, with a compressor and converter A connected to each other through a half-wave rectifier M-1 to PAM-2; The RS-trigger is connected with its S-input to the output of the first time delay unit through the second delay unit, and the inverse output of this trigger is connected to the CE enable input for reading from the shift register; the direct output of the RS-trigger is connected to its R-input through the first matching circuit, the second pulse counter, the second matching circuit, connected in series; the second input of the first matching circuit is connected to the output of the clock; a 5 V power supply is connected to the input of the differentiating RC circuit and to the input of permission n

Description

The utility model (PM) relates to the field of digital signal transmission (DS).

Known analog-to-digital converters (ADCs), described in sources, for example, in:

1. Shmytinsky V.V., Kotov V.K., Zdorovtsev I.A. Digital information transmission systems in railway transport. - M .: Transport, 1995

2. Edited by S. Yakubovsky. Digital and analog integrated circuits. Directory. - M .: Radio and communications, 1990

3. Gorelov G.V., Fomin A.F., Volkov A.A., Kotov V.K. The theory of signal transmission in railway transport. M .: - Transport, 2003

By its technical nature, the PCM - 30 ADC of the PCM - 30 system, which is described in the first source, which is for this reason taken as its prototype, is closest to PM. Other sources describe PM analogues.

The prototype consists of a multi-channel speech signal sampler (PC) in time, a distribution line, and an encoder that works by the weighting method. The encoder includes a sample level comparator, two eleven reference signal shapers (FES), an eight-input shift register with parallel loading, a pulse generator, a FES switching device (UKF), and a control signal conversion device (UPSU). AIM-2 samples of speech signals are received at one input of the comparator, and reference signals are received at its other input. The output of the comparator is connected to the inputs of the shift register, the outputs of which are connected to the UKF through UPSU. The pulse generator is connected to the enable input of the comparator.

The encoder also compresses the samples, moreover, only discretely, at eight points of a continuous logarithmic curve in the positive and negative regions of variation of the samples. These points are interconnected by straight lines (segments)

The duration of each segment is doubled compared to the previous one, starting from the third. There is no compression within the segment. Therefore, at high signal levels, speech is conducted against the background of a large level of quantization noise, which reduces the quality of speech.

The main disadvantage of the prototype is the relatively low quality of speech at high signal levels.

The technical result of PM is to improve the quality of speech due to the continuous compression of the samples, instead of discrete, which is carried out using the introduced elements.

The essence of PM consists in the fact that in a multi-channel ADC, consisting of successively connected multi-channel key time-based samplers of speech signals, performing amplitude-pulse modulation of AIM-1, a compressor of the level of readings, a converter of AIM-1 to AIM-2, a signal encoder, shift register with a clock generator connected to its second input, as well as a distribution line that includes a pulse generator in series with the control inputs of the sampler keys, the first counter pulses, a decoder, and the output of the pulse generator is also connected directly to the second input of the encoder and to the second input of the AIM-1 to AIM-2 converter through the first time delay unit, a two-half-wave rectifier of speech samples, an RS-trigger, two delay units, time, two coincidence circuits AND, a second pulse counter, a 2I-NOT circuit, a differentiating circuit, and, through a half-wave rectifier, the compressor and the AIM-1 to AIM-2 converter are connected; The RS-trigger is connected by its S-input to the output of the first time delay unit through the second delay unit, and the inverse output of this trigger is connected to the CE enable input for reading the shift register; the direct output of the RS-trigger is connected to its R-input through the first matching circuit, the second pulse counter, the second matching circuit, connected in series; the second input of the first matching circuit is connected to the output of the clock; a 5 V power supply is connected to the input of the differentiating RC circuit and to the input of the permission to write the shift register through the 2I-NOT circuit, the second input of which is connected to the output of the first time delay unit; the compressor input is connected to the first trigger of the shift register through the third time delay block.

A significant difference between PM is the introduced elements and their relationships, since only they can improve the quality of speech.

PM is illustrated in the drawing.

Figure 1 presents the structural diagram of the proposed multi-channel ADC, where it is indicated:

1 - multi-channel sampler of speech signals;

2 - sampling pulse generator;

3 - compressor level readings;

4 - decoder;

5, 17 - pulse counters;

6 - half-wave rectifier samples;

7, 9, 11 - time delay blocks;

8 - converter AIM-1 to AIM-2;

10 - RS trigger;

12 - encoder;

13 - scheme 2I-NOT;

14 - shift register;

15 - clock generator;

16, 18 - matching patterns;

RC is a differentiating circuit.

The VD diode is used for decoupling cascades.

Entered elements are surrounded by dashed lines.

The operation of this ADC (figure 1) is as follows.

At the information input of the first key of the multichannel sampler 1, a constant voltage E is supplied, through which a clock signal is further generated, and analog speech signals are fed to the information inputs of its remaining keys A _{1 ...} A _n . The control inputs of these keys alternately receive short pulses from the output of the decoder 4. The pulse repetition rate f = 8 kHz, where k is the number of keys is set by the oscillator 2, connected to the address inputs of the decoder 4 through the pulse counter 5, which converts the pulse number from the decimal system calculus in binary. In this case, the sampling frequency of the signal time with each key is F ₀ = 8 kHz, which corresponds to the Kotelnikov theorem. At the output of each key, pulse-amplitude modulation AIM-1 takes place; the outputs of all the keys are connected together and connected to the input of the compressor 3 and in parallel to the first trigger of the shift register 14 through the third time delay unit 11; blocks 2, 4 and 5 form a distribution line, which with the help of keys provides temporary sealing of the channels.

The total signal from block 1 is compressed (compressed) by the level in block 3, after which it is biannually rectified in block 6, being converted from bipolar to unipolar pulses arriving at one input of block 8, to the second input of which pulses are sent from generator 2 through the first block of time delays 7. In block 8, short AIM-1 pulses having different amplitudes are converted into rectangular pulses of the required duration τ with a horizontal top, still having different amplitudes. These AIM-2 pulses arrive at encoder 12, where their level is converted from a decimal system to a binary, that is, to a digital signal (DS). From the output of block 10, the CA receives a parallel code for all data inputs, starting from the second shift register 14, where the sign of samples from the input of compressor 3 through the time delay unit 11 arrives at the first input at this time; the inverse output of the 2I-NOT 13 microcircuit is connected to the PE permission entry to write data to the shift register 14, the one supply of which is supplied with constant power 5 V, and the other with pulses from the generator 2 through the first block of time delay 7. By this time, the central block 12 is formed and the pulse from block 7 provides zero at the input of PE, which is a write permission, and it is carried out. The operating modes of the shift register K555IR9 with parallel eight-input data loading are presented in Table 1, borrowed from the book by Shilo V.L. Popular digital circuits. - M.: Radio and Communications, 1987.

Table 1 Status of the register K555IR9 N p / p Mode FROM one. Parallel Download (Recording) N x x 2. Sequential shift (read) AT N x 3. Storage AT AT x

In the table:

H - low voltage;

In - high voltage;

x is any voltage.

Clock input from shift register 14 receives clock pulses from generator 15. While there is a high voltage at the CE enable input (see Table 1), information is not read from block 14. This voltage is set by the inverse output of the RS-flip-flop 10. The pulses from the generator 2 pass through the first 7 and second 9 time delay blocks to the S-input of this flip-flop, which transfer this trigger from the zero state to the unit state, and zero appears on its inverse output , which is the permission to read information from the shift register 14 using clock pulses. Clock pulses from the generator 15 are also supplied to the input of the second counter 17 through the first matching circuit 16, the second input of which is connected to the direct output of the RS-trigger 10. After the counter 17 counts 8 pulses, the three-input matching circuit 18 connected to the output will work counter 17, and will issue a unit to the R-input of the RS-trigger. From this, the trigger is reset to zero, and a unit appears on its inverse output, stopping the process of reading information from shift register 14 until the next pulse arrives from block 7 on the RS-trigger 10. The 5 V power supply voltage is also supplied to the R-input of this trigger differentiating RC circuit, which puts this trigger to zero when the power is turned on.

It can be seen that the work of this ADC is significantly different from the work of the ADC of the prototype, which works by the weighing method. Their different structural structure and the structure of digital signals.

The technical and economic effect of PM is to improve the quality of speech due to continuous compression of the speech signal instead of a discrete one.

Claims (1)

Multichannel analog-to-digital converter (ADC) of signals, consisting of sequentially connected multichannel key time sampler of speech signals, performing amplitude-pulse modulation of AIM-1, a compressor of the reading level, converter AIM-1 to AIM-2, signal encoder, shift register with a clock pulse generator connected to its second input, as well as a distribution line, which includes a pulse generator, first connected to the control inputs of the sampler keys a pulse counter, a decoder, and the output of the pulse generator is also connected directly to the second input of the encoder and to the second input of the AIM-1 to AIM-2 converter through the first time delay unit, characterized in that a half-wave rectifier of speech samples, RS -trigger, two time delay blocks, two coincidence circuits AND, a second pulse counter, a 2I-NOT circuit, a differentiating circuit, and a compressor and converter A are connected through a half-wave rectifier M-1 to PAM-2; The RS-trigger is connected with its S-input to the output of the first time delay unit through the second delay unit, and the inverse output of this trigger is connected to the CE enable input for reading from the shift register; the direct output of the RS flip-flop is connected to its R-input through the first matching circuit, the second pulse counter, and the second matching circuit; the second input of the first matching circuit is connected to the output of the clock; a 5 V power supply is connected to the input of the differentiating RC circuit and to the input of the write permission to the shift register through the 2I-NOT circuit, the second input of which is connected to the output of the first time delay unit; the compressor input is connected to the input of the first trigger of the shift register through the third time delay unit.