RU91489U1 - ANALOG-DIGITAL CONVERTER - Google Patents

Abstract

An analog-to-digital converter, consisting of a series-connected source of an analog signal, a pulse-width modulator (PWM), a first coincidence circuit, a first digital pulse counter, a first shift register, and also a pulse generator connected to the second input of a PWM modulator, a multivibrator connected to the second input of the first coincidence circuit, and a clock generator connected to the second input of the first shift register, the first differentiator connected to the output of the modulator and PWM, and the output - to the enable input of reading the shift register, and the delay unit connected between the output of the differentiator and the counter reset input to zero, characterized in that an additional second and third coincidence circuit, two digital inverters, a frequency divider of 2 are introduced into it times, three differentiators, two 2I-NOT circuits, a digital serial adder, the pulse generator being connected to the second input of the PWM modulator through the first time delay unit connected in series, the frequency divider 2 times, the second circuit matches is connected between the first match circuit and the first digital counter, and the output of the first shift register is connected directly to one input of the digital adder, the second input of which is connected to the output of the first match circuit through the third match circuit connected in series, the second digital counter, the second shift register, to the clock the input of which the output of the clock generator is connected, the input of the frequency divider is 2 times connected directly to the second input of the second coincidence circuit and through the first

Description

A utility model (PM) relates to the field of digital signal (CS) generation.

Known analog-to-digital converters (ADC) of signals based on pulse-width modulation (PWM), described in the literature, for example in:

1. Yu.P. Borisov, P.I. Pennin. Basics of multichannel information transfer. - M .: Communication, 1967. - 298-299;

2. G.V., Gorelov, A.A. Volkov, V.I. Shelukhin. Channel-forming devices of railway telemechanics and communications. - M .: GOI, 2007 .-- p.266-268.

In terms of technical nature, the closest to PM is the ADC described in the first source, which for this reason is taken as its prototype. The second source describes an analogue of PM.

The prototype consists of a series-connected source of an analog signal, a PWM modulator, a coincidence circuit, a digital pulse counter, a shift register, and also a pulse generator connected to the second input of the PWM modulator, a multivibrator connected to the second input of the coincidence circuit, a clock pulse generator connected to the second input shift register, a differentiator, which is connected through the output to the PWM modulator entry permission to start the shift register, the time delay at time T _pr pre block rofessional parallel to serial, through which the differentiator output is connected to the R - entry counter reset to zero. The error of the ADC is proportional to the time T _ol , which is significant, since the number of bits in the codeword is significant, equal to 8.

The main disadvantage of the prototype is the relatively large error of the ADC, since a significant period of the PWM pulse is often allocated to the conversion of the parallel counter code to serial, which reduces the deviation of the pulse duration.

The technical result of PM is to reduce the error of the ADC by increasing the deviation of the pulse duration during PWM, which provides the introduced elements and their connections, eliminating the loss of time when converting a parallel code to a serial one.

The essence of the PM is that the ADC contains a series-connected source of an analog signal, a PWM modulator, a coincidence circuit, a digital pulse counter, a shift register, as well as a pulse generator connected to the second input of the PWM modulator, a multivibrator connected to the second input of the coincidence circuit , a clock generator connected to the second input of the shift register, a differentiator through which the output of the PWM modulator is connected to the input of the permission to start the shift register, time delay unit _direct conversion of parallel to serial, through which the differentiator output is connected to the R - entry counter reset to zero; additionally introduced the second and third coincidence circuits, two digital inverters, a 2-fold frequency divider, three differentiators, two 2I-NOT circuits, a digital serial adder, and the pulse generator is connected to the second input of the PWM modulator through the first time delay block connected in series, the frequency divider is 2 times, the second coincidence circuit is connected between the first coincidence circuit and the first digital counter, and the output of the first shift register is connected directly to one input of the digital adder, to the second at the input of which the output of the first coincidence circuit is connected through the third coincidence circuit, the second digital counter, and the second shift register, the output of the clock generator is connected to the clock input, the input of the frequency divider is 2 times connected directly to the second input of the second coincidence circuit and through the first digital inverter - to the second input of the third coincidence circuit; the output of the PWM pulse generator is connected to the zero input of the first counter through the first differentiator and the second counter through the second digital inverter and second differentiator; the first 2I-NOT circuit is connected with its output to the recording permission input of the first shift register, one input of which receives 5 V supply voltage, and its other input is connected to the output of the first digital inverter through the third differentiator; the second 2I-NOT circuit is connected with its output to the recording permission input of the second shift register, to one input of which 5 V supply voltage is supplied, and its other input is connected to the input of the frequency divider 2 times through the fourth differentiator; the permissions for converting the parallel code into serial of both shift registers are connected to the output of the first digital inverter.

A significant difference between the PM is the introduced elements and their relationships, since only they provide the possibility of maximum deviation of the pulse duration during PWM and thereby minimize the error of the ADC.

PM is illustrated by drawings.

The figure 1 presents the structural diagram of the ADC, the figure 2 is a timing diagram explaining its operation.

In figure 1 is indicated:

1 - source of an analog signal;

2 - pulse-width modulator (PWM);

3 - frequency divider 2 times;

4 - block time delay;

5 - pulse generator;

6, 13 - digital inverters;

7 - multivibrator;

8, 12, 14 — matching patterns (AND patterns);

9, 10, 11, 15 - differentiators;

16, 17 - digital counters;

18, 22 - schemes 2I-NOT;

19, 21 - shift registers;

20 - clock generator;

23 is a digital serial adder.

Entered elements are outside the dashed line.

The operation of the circuit is as follows.

The analog signal u ₁ (t) is supplied from source 1 to the low-frequency (LF) input of modulator 2, to the high-frequency (HF) input of which a periodic pulse sequence u ₅ (t) of the subcarrier frequency is supplied from the generator 5 through the time delay unit 4 and the divider 3 frequencies 2 times. The pulse sequence u ₃ (t), like u ₅ (t), has the shape of a meander when, on a period T, the pulse duration τ is equal to the pause duration Δτ = T-τ, as shown in Fig. 2.

In block 2, pulse-width modulation (PWM) takes place, in which the pulse width at its output changes in proportion to the amplitude of the analog signal u ₁ (t), and the period T remains constant.

From the output of block 2, the oscillation u ₂ (t) goes to one input of the first coincidence circuit 8 (circuit I), to the other input of which the oscillation u ₇ (t) of the multivibrator 7 is also in the form of a meander, but its pulse duration δ is many times less the duration of the shortest PWM pulse u ₂ (t). The pulses u ₇ (t) sample in time the PWM pulses in block 8, as shown in FIG. 2. The number of pulses of duration δ at the output of the coincidence circuit 8 is proportional to the pulse width of the PWM. These pulses u ₈ (t) are supplied in parallel to one of the inputs of the second 12 and third 14 coincidence circuits, the other inputs of which are supplied with the oscillation u ₄ (t) from the output of the delay unit 4: directly to circuit 12 and through the digital inverter 13 to circuit 14. Since the pulse period u ₄ (t) is 2 times less than the oscillation period u ₃ (t), then circuits 12 and 14 work alternately: in the first half of period T, circuit 12 works, passing part of the pulses of duration δ of circuit 8 to its output, and the second part of the period running circuit 14, passing at its output the remainder of the ₈ pulses u (t) by n IRS TS output circuit 12 pulses ₁₂ u (t) input to the binary counter 16, and pulses output from the circuit 14 are input to the binary counter 17.

Before these pulses arrive, the counters 16 and 17 are reset to zero by the edges of the pulses from the generator 5, which are ahead of the pulses from the output of the delay unit 4. For this, the pulses from the output of the block 5 are fed to the R - input of the counter 16 through the first differentiator 10, and to R - the input the counter 17 through a second digital inverter 6 and a second differentiator 11 connected in series. From the output of the counter 16, the digital signal (DS) u ₁₆ (t) of the parallel code is fed to the D - inputs of register 19 with parallel loading, and from the output of the counter 17 the DS goes to D - inputs of the second ID secondary shift register 21. These shift registers 19 and 21 of type K555IR9 have a write enable input PE, a read enable input CE and a clock input C. The states of these inputs for each mode are presented in Table 1, borrowed from the book by V.L.Shilo Popular digital microcircuits. - M .: Radio, 1987 p.122.

To the input of both registers is connected the output of a generator of 20 clock pulses. At the input of the PE register 19, a constant voltage of 5 V is supplied through the 2I-NOT 18 chip, the second input of which is connected to the output of the delay unit 4 through the digital inverter 13 and the third differentiator 15 connected in series. As soon as the counter 16 finishes counting the pulses at the half-cycle at the PE input a zero voltage (H) appears, and at this moment, the readings of the counter 16 are recorded in the shift register 19 (table 1). The rest of the time, the output of the PE register 19 will be high (B) voltage, which excludes recording and the register is in storage mode, which is indicated by the arrows in figure 2. A 5 V supply voltage is also supplied to the PE input of the counter 21 through a 2I-NOT 22 chip, the second input of which is connected to the output of the delay unit through the fourth differentiator 9. As soon as the first half of the pulse period starts at the output of unit 4, or, what is the same, the work ends counter 17, zero voltage (H) will appear at the input of counter PE 21, and at this moment the readings of the counter 17 will be recorded in register 21. The rest of the time, there will be a high (V) voltage at the input of register PE 21, which prevents recording.

The input CE of both registers is connected to the output of the digital inverter 13. This means that the reading of information from both registers, that is, the conversion of the recorded parallel code to serial will occur in pauses of the counter 17. The output of register 19 is connected to one input of the serial binary adder 23, and the output of register 21 is to its second input. At the output of the adder 23, the exact number of pulses of duration δ is obtained, corresponding to the pulse of the PWM of unit 2 for a given period T.

The technical and economic effect of PM is to reduce the error of the ADC by increasing the deviation of the pulse width of the PWM from 0.8 to 0.96, that is, by 16%. This is achieved by eliminating the loss of time converting parallel code to serial by reading information in the pauses of one of the counters. This ADC does not have quantization noise, since there is no operation to quantize samples by level.

Table 1
Status of the register K555IR9 N p / p Mode FROM one. Parallel loading N x x 2. Sequential shift AT N ↑ 3. Storage AT AT x H - low voltage; B - high voltage; x is any voltage.

Claims (1)

An analog-to-digital converter, consisting of a series-connected source of an analog signal, a pulse-width modulator (PWM), a first coincidence circuit, a first digital pulse counter, a first shift register, and also a pulse generator connected to the second input of a PWM modulator, a multivibrator connected to the second input of the first coincidence circuit, and a clock generator connected to the second input of the first shift register, the first differentiator connected to the output of the modulator and PWM, and the output - to the enable input of reading the shift register, and the delay unit connected between the output of the differentiator and the counter reset input to zero, characterized in that an additional second and third coincidence circuit, two digital inverters, a frequency divider of 2 are introduced into it times, three differentiators, two 2I-NOT circuits, a digital serial adder, the pulse generator being connected to the second input of the PWM modulator through the first time delay unit connected in series, the frequency divider 2 times, the second circuit matches is connected between the first match circuit and the first digital counter, and the output of the first shift register is connected directly to one input of the digital adder, the second input of which is connected to the output of the first match circuit through the third match circuit connected in series, the second digital counter, the second shift register, to the clock the input of which the output of the clock generator is connected, the input of the frequency divider is 2 times connected directly to the second input of the second coincidence circuit and through the first rovoy inverter to the second input of the third coincidence circuit; the output of the PWM pulse generator is connected to the zero input of the first counter through the first differentiator and the second counter through the second digital inverter and second differentiator; the first 2I-NOT circuit is connected with its output to the recording permission input of the first shift register, one input of which receives 5 V supply voltage, and its other input is connected to the output of the first digital inverter through the third differentiator; the second 2I-NOT circuit is connected with its output to the recording permission input of the second shift register, to one input of which 5 V supply voltage is supplied, and its other input is connected to the input of the frequency divider 2 times through the fourth differentiator; the permissions for converting the parallel code into serial of both shift registers are connected to the output of the first digital inverter.