SU1390772A1 - Sinusoidal oscillator - Google Patents

Abstract

The invention relates to radio engineering. The purpose of the invention is to reduce the frequency discreteness. The generator of sinusoidal oscillations contains the master oscillator 1, dividers (d) 2 and 4 frequencies with variable coefficients. dividing, pulse train 3 to sin. A memory register (RP) 5 has been entered. Generator 1 generates a sequence of square pulses with a repetition rate f arriving at the clock input D2. Coefficient the division of D2 is equal to the integer part of the quotient, where g ,,, is the coefficient. divisions D4, m are the number of sampling intervals of the period of the output voltage (the resolution of the D / A converter contained in the converter C). Moreover, for D4, the inequality should be satisfied, where p is the width of the input, the control coefficient. division of D4, and the size of the DF. 5. Part of the higher bits of the output of the Dt. 5 i, where 1 is the size of the D2, and is connected to the control input of the coefficient. division D2. Coefficient The divisions of D4 can be represented as Nn-m + k, where k can vary from 0 to (t-1) in increments of one. 2 Il. with (L with oo; with about Is3

Description

I-k1bretenka refers to radotechnology 1.:ike and can be used in measuring equipment and as a measuring generator tuned by frequency.

The purpose of the invention is to reduce the discreteness of frequency spawning.

FIG. 1 shows a structural electrical circuit of a generator of sinusoidal oscillations; in fig. 2 - timing diagrams for the generator operation.

The generator of sinusoidal oscillations contains the master oscillator I, the first, the divider 2 hours of the cell with a variable division factor (WPC D). a pulse width converter in sinusoid voltage; a second divider 4 xjacTOTbi with a variable division factor (D11 CD and memory register 5).

The generator works as follows.

The master oscillator 1 generates a sequence of rectangular pulses with a repetition frequency f arriving at the clock input LT1KD. 2, the division ratio of the PDKD 2 is equal to the fraction of the private p

f.

and

Where

m ° - is the division ratio of DPCD 4;

6b (Y

0

p.puchae even in the absence of PDKD 4 on H1,1x od (; converters 3, the voltage is generated with a voltage of the first harmonic equal to fo / n-m (Fig. 2c).

When N is not divided by m without remainder, i.e. k O, the frequency of the signal at the output of DKD 4 is equal to f,) / (n-ra + k), and at the output of DCDD 2 is equal to fo / n. The zero signal of the PDKD 2 and the converter 3, coming from the output of the PDKD 4 (Fig. 2d), appears with a delay of k / L,. , relative to the end of the last sampling time interval, equal to. After installation; SC1CD 2 and converter 3 into the zero state (Fig. 2e), the period of the generated voltage increases with discreteness, therefore, it becomes possible to obtain additional (ml) frequencies at the output of converter 3 and thereby decrease the frequency tuning discreteness at constant division ratio of DDKD 2. In the case when k705 increases the nonlinear distortion of the output voltage. However, with an increase in the period, it is obtained for a time not exceeding the duration of one sampling interval and by time, and the nonlinear distortion increases slightly.

m is the number of sampling intervals for the period of the output n; apr (the digitizer’s converter size (not shown; contained in the converter 3). And for dakd 4, the inequality must be fulfilled, where p is the width of the input that controls the coefficient divisions of D11KD 4, and the memory register 5 has a fraction. Some of the most significant bits of the output of register 5 of memory are G-, i is the bit size. PDKD 2 ,, cce (2m, connected to the input of control of the division ratio of PDKD 2. Coefficient divisions of D11KD 4 can be represented as m + k, where k can vary CiT to (m-l) with uiaroM, equal to unity.

When W is divided by m without remainder,; , e. , p1; tota of following impulses at the output of DPDD 2, / n 1FIG. 2a), - and at the exit. DPKD 4 G / P ha 1, fig. 2b). consequently, the moment of zeroing of converter 3 and DCDD 2 coincides with the appearance of the next pulse at the output of DCD 2, B

35

pm lla

and 3 o b

the shadows

0

five

0

five

A generator of sinusoidal oscillations, containing a series-connected master oscillator and a first frequency divider with a variable division factor, as well as a second frequency divider with a variable division factor and a converter of a sequence of pulses into a sinusoidal voltage, distinguished. and in order to reduce the frequency tuning discreteness, a memory register is entered into it, the bit outputs of which are connected to the corresponding division control inputs of the second frequency divider with a variable division factor, and the outputs of the higher bits of the memory register are also connected to the respective inputs of the control of the division factor of the first frequency divider with a variable factor divided and, the clock input of the second ijoro frequency divider with variable

the division factor is connected to the output of the master oscillator, the output of the first frequency divider with a variable division factor is connected to the clock input of the converter of the sequence of pulses into sinusoidal voltage, the inputs about, 111Л1111111111 1Ц11Ш1111111111.

y d

 t

I I I I M I I I I I I I I I I I I I I t I I M and I I, t

Zeroes of the first frequency divider with a variable division factor and a pulse train into a sinusoidal voltage are combined and connected to the output of the second frequency divider with a variable division factor.

 t

2

Claims (1)

Claim A sinusoidal oscillation generator comprising a serially connected master oscillator and a first frequency divider with a variable division ratio, as well as a second frequency divider with a variable division coefficient and a pulse sequence converter into a sinusoidal voltage, characterized in that, in order to reduce the frequency resolution discreteness, it is introduced memory register, the bit outputs of which are connected to the corresponding inputs of the control of the division ratio of the second frequency divider with a variable nym dividing ratio and outputs MSBs memory registers are also connected to respective inputs of the control of the first frequency divider dividing ratio of the variable dividing ratio, a clock input of the second frequency divider with a variable 1390-72 a division factor is connected to the output of the master oscillator, the output of the first frequency divider with a variable division ratio is connected to the clock input of the pulse sequence converter to a sinusoidal voltage, the zero inputs of the first frequency divider with a variable division coefficient and the pulse sequence converter ^ pulses to a sinusoidal voltage are combined and connected to the output of the second frequency divider with a variable division ratio. Fi g. 2