RU2814896C1 - Cmos exclusive-or logic gate - Google Patents

Abstract

FIELD: digital computing.

SUBSTANCE: used in the construction of circuits using the EXCLUSIVE-OR function - multi-bit adders, even/odd circuits, counting registers and many other high-speed multi-bit electronic devices. For this purpose, a CMOS EXCLUSIVE-OR gate is proposed, which contains a high-voltage power supply line VDD, a low-voltage power supply line GND, four P-type MOS transistors and four N-type MOS transistors, inputs A and B, and an output OUT.

EFFECT: increased speed of the EXCLUSIVE-OR circuit and its reliability by reducing the dynamic current consumption.

1 cl, 1 dwg, 1 tbl

Description

The present invention relates to digital computing technology and can be used in the construction of circuits using the EXCLUSIVE-OR function - multi-bit adders, even/odd circuits, counting registers and many other high-speed multi-bit electronic devices.

The XOR gate circuit using TG is known [1] (p. 652, Fig. 7.5), built on 8 MOS transistors, forming two CMOS inverters and two full-level CMOS transfer gates ( Transmission Gates, TGs).

This XOR gate circuit [1] contains inputs a and b and output out, high and low voltage power supply rails, P-type MOS transistors from the first to the fourth and N-type transistors from the fifth to the eighth.

A disadvantage of the known EXCLUSIVE-OR gate circuit [1] is the low performance caused by the presence of large values of built-in parasitic node capacitances at the inverter output in the signal circuit from input b to output out through a transfer gate connected to the output of the CMOS inverter generating the inverse signal .

In addition, the dynamic current consumption of the known EXCLUSIVE-OR gate circuit [1] increases due to the increased time of the transient recharging process of this node, which leads to additional overheating of the circuit elements and reduces the overall reliability of the circuit.

The objective of the present invention is to increase the performance of the known EXCLUSIVE-OR gate circuit [1] and its reliability by reducing the dynamic current consumption.

The task is achieved by the fact that, in the EXCLUSIVE-OR gate circuit [1], containing MOS transistors of the P-type from the first to the fourth and N-type from the fifth to the eighth, the signal input A is connected to the gates of the transistors of the first, second, fifth and eighth, and the drains of the first and fifth transistors are interconnected and connected to the gates of the fourth and sixth transistors, signal input B, connected by the gates of the third and seventh transistors and with the sources of the second and sixth transistors, and the drains of the third and seventh transistors are connected to each other, the source bus high-voltage power supply VDD connected to the source of the first transistor, low-voltage power supply bus GND connected to the source of the fifth transistor, OUT output connected to the drains of the second and sixth transistors, in contrast to the well-known EXCLUSIVE-OR gate circuit [1], The source of the fourth transistor is connected to the high voltage power supply bus VDD, and the drain is connected to the source of the third, the source of the eighth transistor is connected to the low voltage power supply bus GND, and the drain is connected to the source of the seventh, and the drains of the third and seventh transistors are connected to the OUT output .

Thus, in the proposed technical solution of the CMOS logical gate EXCLUSIVE-OR, in contrast to the well-known EXCLUSIVE-OR gate circuit [1], there is no physical connection between the sources of the MOS transistors of the third and seventh and the drains of the MOS transistors of the fourth and eighth among themselves, which increases the capacity of this node and thereby reduces the performance of the EXCLUSIVE-OR gate circuit [1] due to an increase in the duration of the transient switching process of this node. Therefore, the performance of the proposed CMOS EXCLUSIVE-OR logic gate is higher than the performance of the well-known EXCLUSIVE-OR gate circuit [1].

In addition, increasing the speed of the circuit by reducing the duration of the transient process leads to a decrease in the time of flow of through current between the power supply buses of high VDD and low GND levels, a decrease in the dynamic current consumption of the circuit and a decrease in additional overheating of circuit elements, which increases the overall reliability of the proposed CMOS logic EXCLUSIVE-OR gate.

Figure shows the schematic diagram of the proposed CMOS XOR logic gate.

The proposed CMOS XOR logic gate contains P-type MOS transistors from the first to the fourth 1-4 and N-type from the fifth to the eighth 5-8, signal input A connected to the gates of the first 1, second 2, fifth 5 and eighth transistors 8, and the drains of the first 1 and fifth 5 transistors are interconnected and connected to the gates of the fourth 4 and sixth 6 transistors, the signal input B is connected to the gates of the third 3 and seventh 7 transistors and the sources of the second 2 and sixth 6 transistors, and the drains of the third 3 transistors and the seventh 7 are connected to each other, the OUT output connected to the drains of the second 2 third 3, the sixth 6 and the seventh 7 transistors, the high voltage power supply bus VDD connected to the sources of the first 1 and fourth 4 transistors, the low voltage power supply bus GND , connected to the sources of the fifth transistors 5 and the eighth 8, with the drain of the fourth transistor 4 connected to the source of the third 3, and the drain of the eighth 8 to the source of the seventh.

The proposed CMOS XOR gate is a combinational type logic circuit designed to form an XOR logic function and operates according to the truth table below. Truth Table of CMOS Exclusive-Or Logic Gate

In the initial state (Combination No. 1), a low level voltage GND is supplied to inputs A and B, which corresponds to the voltage of the low logical level “0” of the truth table. In this case, P-type transistors 1, 2 and 3 open, and N-type 5, 7 and 8 close. Through the open transistor 1, the gates of the P-type 4 and N-type 6 transistors receive a high-level voltage VDD, which corresponds to the voltage of the high logical level “1” of the truth table, as a result of which transistor 6 opens and transistor 4 closes. Therefore, the low logical level voltage “0” is supplied to the OUT output through open transistors 2 and 6 from input B, which corresponds to the value of the truth table of combination No. 1.

If a voltage of a high logical level “1” is supplied to input A, and a voltage of a low logical level “0” is supplied to input B (Combination No. 2), then P-type transistors 1 and 2 and N-type transistor 7 are closed, and transistor P- type 3 and N-type transistors 5 and 8 - open. Through the open transistor 5, a low logic level voltage “0” is supplied to the gates of the P-type 4 and N-type transistors 6, as a result of which transistor 4 opens and transistor 6 closes. Therefore, the voltage of the high logical level “1” is supplied to the OUT output through open transistors 3 and 4, which corresponds to the value of the truth table of combination No. 2.

If a voltage of a low logical level “0” is supplied to input A, and a voltage of a high logical level “1” is supplied to input B (Combination No. 3), then P-type transistors 1 and 2 and N-type transistor 7 open, and transistor P- type 3 and N-type transistors 5 and 8 are turned off. Through the open transistor 1, a voltage of the high logical level “1” is supplied to the gates of the P-type 4 and N-type transistors, as a result of which transistor 4 closes and transistor 6 opens. Therefore, from input B to output OUT through open transistors 2 and 6, a voltage of the high logical level “1” is supplied, which corresponds to the value of the truth table of combination No. 3.

If inputs A and B receive a high logic level voltage “1” (Combination No. 4), then P-type transistors 1, 2 and 3 close, and N-type transistors 5, 7 and 8 open. Through the open transistor 5, a low logic level voltage “0” is supplied to the gates of the P-type 4 and N-type transistors 6, as a result of which transistor 6 closes and transistor 4 opens. Therefore, the voltage of the low-level power supply bus GND, the corresponding voltage of the low logical level “0”, is supplied to the OUT output through open transistors 7 and 8. Thus, this state corresponds to the values of the truth table of combination No. 4.

When the circuit returns to its original state (Combination No. 1 of the truth table), a low logic level voltage “0” is supplied to inputs A and B. In this case, P-type transistors 1, 2 and 3 open, and N-type 5, 7 and 8 close. Through the open transistor 1, a voltage of the high logical level “1” is supplied to the gates of the P-type 4 and N-type transistors, causing transistor 6 to open and transistor 4 to close. Therefore, from input B to output OUT through open transistors 2 and 6, a voltage of a low logical level “0” is supplied, which corresponds to the value of the truth table of combination No. 1 and the CMOS logical gate EXCLUSIVE-OR goes to its original state.

Since in the proposed CMOS EXCLUSIVE-OR logic gate, there is no physical connection between the sources of the MOS transistors third and seventh and the drains of the MOS transistors fourth and eighth, which increases the capacitance of this node and thereby reduces the performance of the EXCLUSIVE-OR gate circuit [1] is absent, then The capacity of this node is significantly reduced. Therefore, the duration of the transient process associated with the recharging of parasitic capacitances is reduced and the performance of the proposed CMOS XOR logic gate is higher than the well-known XOR gate circuit [1].

In addition, increasing the speed of the circuit by reducing the duration of the transient process leads to a decrease in the flow time of the through current between the power supply buses of high VDD and low GND levels, a decrease in dynamic current consumption, a reduction in additional overheating of circuit elements and thereby increases the overall reliability of the proposed CMOS logic gate EXCLUSIVE-OR.

Thus, the proposed CMOS exclusive-or logic gate, compared to the well-known exclusive-or gate circuit [1], has higher performance and reliability.

Literature

1. Balaji, G. N. Combinational Circuits Using Transmission gate Logic for Power Optimization / G. Naveen Balaji, V. Aathira, K. Ambhikavathi, S. Geethiga, R. Havin // International Research J. of Eng. and Tech. - May 2016. - Vol. 03, Issue 05. - ISO 9001: 2008 Certified Journal. - P. 649-654. - e-ISSN: 2395-0056, p-ISSN: 2395-0072 (Fig. 7.5, p. 652).

Claims (1)

A CMOS XOR logic gate containing P-type MOS transistors from the first to the fourth and N-type from the fifth to the eighth, a signal input A connected to the gates of the first, second, fifth and eighth transistors, and the drains of the first and fifth transistors are connected between themselves and connected to the gates of the fourth and sixth transistors, the signal input B, connected by the gates of the third and seventh transistors and to the sources of the second and sixth transistors, and the drains of the third and seventh transistors are interconnected, the high-voltage power supply bus VDD connected to the source of the first transistor, a low-voltage power supply bus GND connected to the source of the fifth transistor, an OUT output connected to the drains of the second and sixth transistors, characterized in that the source of the fourth transistor is connected to the high-voltage power supply bus VDD, and the drain to the source of the third , the source of the eighth transistor is connected to the low voltage power supply bus GND, and the drain is connected to the source of the seventh, and the drains of the third and seventh transistors are connected to the OUT output.

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