RU2632567C1 - Voltage level converter - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: voltage level converter circuit comprises: seven P-Type field transistors (1-7) and five N-type field transistors (8-12), the inputs of direct IN and inverse

input signals, a power supply terminal of high-voltage level VDD, a high-voltage level supply terminal (GND) and an OUT output.

EFFECT: high performance of high-voltage conversion and return to high-voltage level.

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Description

The present invention relates to digital computing and can be used to coordinate circuits having different voltage levels of power supplies and internal signals.

Known converter of signal levels on MIS transistors [1]. This device is designed to convert the signal voltage level (for example, when pairing TTL- and KMDP logic elements).

The disadvantage of the above scheme is the low speed. The low speed of the circuit is caused by the limitation of the appearance of a high level voltage at the output of the circuit along the low conductivity circuit, up to the connection of a high conductivity transistor that shunts the low conductive circuit, which is delayed by the signal propagation time required for the sequential switching of two gates.

In addition, each of the output nodes of the trigger, in addition to the gates of the transistors of the output transistors, is connected to the gates of two P-type transistors, which additionally increases the stray capacitance of the output nodes of the trigger and delays the switching process.

The task of the invention is to increase the speed of the voltage level Converter.

входных сигналов, подсоединенные к затворам транзисторов, соответственно, восьмого и девятого, вывод питания высокого уровня напряжения VDD, соединенный с истоком первого транзистора, вывод питания низкого уровня напряжения GND, соединенный с истоками восьмого, десятого и одиннадцатого транзисторов, причем сток первого транзистора соединен с истоками второго и третьего, сток третьего - со стоком девятого и затвором четвертого транзисторов, а затвор - со стоками четвертого и восьмого и затворами пятого и десятого транзисторов, стоки которых соединены между собой и являются выходом OUT преобразователя уровня напряжения, затвор шестого транзистора соединен со стоками транзисторов седьмого и одиннадцатого, затворы которых соединены между собой, введен двенадцатый полевой транзистор N-типа, сток которого соединен с истоком девятого транзистора, исток - с затвором первого транзистора и выводом питания низкого уровня напряжения GND, а затвор - со стоком седьмого транзистора и затвором второго, сток которого соединен со стоком третьего, и исток шестого транзистора соединен - со стоком первого, а сток - с затворами третьего и седьмого, и истоки четвертого, пятого и седьмого транзисторов соединены с выводом питания высокого уровня напряжения VDD.The problem is achieved in that in the voltage level Converter containing P-type field-effect transistors from the first to the seventh and N-type from the eighth to the eleventh, direct IN and inverse inputs

input signals connected to the gates of the transistors of the eighth and ninth, respectively, a high voltage level power supply terminal VDD connected to the source of the first transistor, a low voltage level power supply terminal GND connected to the sources of the eighth, tenth and eleventh transistors, the drain of the first transistor being connected to the sources of the second and third, the drain of the third with the drain of the ninth and the gate of the fourth transistors, and the gate with the drains of the fourth and eighth and the gates of the fifth and tenth transistors, the drains of which interconnected and are the output OUT of the voltage level converter, the gate of the sixth transistor is connected to the drains of the seventh and eleventh transistors, the gates of which are interconnected, a twelfth N-type field effect transistor is introduced, the drain of which is connected to the source of the ninth transistor, the source is connected to the gate of the first transistor and low-voltage power output GND, and the gate with the drain of the seventh transistor and the gate of the second, the drain of which is connected to the drain of the third, and the source of the sixth transistor is connected with the drain m first and runoff - the gate electrodes of the third and seventh, and the sources of the fourth, fifth and seventh transistors are connected to the high-level output power supply voltage VDD.

Thus, in the proposed circuit of the voltage level converter, due to differences from the known device described above, the appearance of a high level voltage at the output of the OUT circuit along the low conductivity circuit is excluded before connecting a transistor with high conductivity, because The formation of the output signal at the OUT output always occurs immediately and along only high conductivity circuits.

Also, unlike the known signal level converter on MIS transistors [1], in addition to the gates of the transistors of the output inverter, the gate of only one P-type transistor is connected to one output node of the trigger in the proposed circuit of the voltage level converter, and the gate of only one transistor is connected to the other, without gates of the transistors of the output inverter, which reduces the stray capacitance of the output nodes of the trigger and further accelerates the transition process of switching the voltage level converter.

The drawing shows a diagram of the proposed voltage level Converter.

входных сигналов, подсоединенные к затворам транзисторов, соответственно, восьмого (8) и девятого (9), вывод питания высокого уровня напряжения VDD, соединенный с истоками транзисторов первого (1), четвертого (4), пятого (5) и седьмого (7), вывод питания низкого уровня напряжения (GND), соединенный с истоками транзисторов восьмого (8), десятого (10), одиннадцатого (11) и двенадцатого (12) и затвором первого транзистора (1), сток которого соединен с истоками второго (2), третьего (3) и шестого (6) транзисторов, причем сток второго транзистора (2) соединен с затвором четвертого (4) и истоками третьего (3) и девятого (9) транзисторов, а сток шестого (6) - с затворами третьего (3), пятого (5), седьмого (7), десятого (10) и одиннадцатого (11) транзисторов и стоками четвертого (4) и восьмого (8), стоки которых соединены между собой и являются выходом OUT преобразователя уровня напряжения, и затвор второго транзистора (2) соединен с затворами транзисторов шестого (6) и двенадцатого (12) и стоками седьмого (7) и одиннадцатого (11).The proposed voltage level converter contains P-type field-effect transistors from the first to the seventh (1-7) and N-type from the eighth to the twelfth (8-12), inputs of direct IN and inverse

input signals connected to the gates of the transistors, respectively, of the eighth (8) and ninth (9), a high voltage level VDD power output connected to the sources of the transistors of the first (1), fourth (4), fifth (5) and seventh (7) , a low voltage level (GND) power output connected to the sources of the eighth (8), tenth (10), eleventh (11) and twelfth (12) transistors and the gate of the first transistor (1), the drain of which is connected to the sources of the second (2) , the third (3) and sixth (6) transistors, and the drain of the second transistor (2) is connected to the gate h fourth (4) and the sources of the third (3) and ninth (9) transistors, and the drain of the sixth (6) - with the gates of the third (3), fifth (5), seventh (7), tenth (10) and eleventh (11) transistors and drains of the fourth (4) and eighth (8), the drains of which are interconnected and are the output OUT of the voltage level converter, and the gate of the second transistor (2) is connected to the gates of the transistors of the sixth (6) and twelfth (12) and the drains of the seventh ( 7) and eleventh (11).

The proposed voltage level converter is a digital logic device designed to convert the input voltage of the logical unit "1 *" (VCC) to the voltage of the logical "1" corresponding to the supply voltage of the high voltage level VDD, and works as follows.

- напряжение логической единицы «1*» (VCC). Минимальное значение напряжения логической единицы «1*» должно быть больше либо равно значению порогового напряжения транзистора N-типа. Кроме того, напряжение источника питания высокого уровня VDD («1») и напряжение логической единицы VCC («1*») должны быть больше или равны сумме пороговых напряжений транзисторов P- и N-типа. Транзистор P-типа 1 низкой проводимости открыт всегда, т.к. его затвор подключен к источнику питания низкого уровня напряжения «0». На затворы транзисторов N-типа 8 и 9 с входов IN и

поступают напряжения соответственно низкого уровня GND («0») и напряжение логической единицы «1*» (VCC). Поэтому транзистор 8 закрыт, а транзистор 9 открыт. Также в результате действия предыдущего регенеративного цикла транзисторы 2, 6, 10 и 11 открыты, а транзисторы 3, 4, 5, 7 и 12 закрыты. Поэтому на выходе OUT преобразователя уровня напряжения через открытый транзистор 10 установлено напряжение низкого уровня «0» (GND).The initial state. A low level voltage corresponding to a logic voltage of “0” is applied to the GND power supply terminal and to the IN input;

- voltage of the logical unit "1 *" (VCC). The minimum voltage value of the logical unit "1 *" must be greater than or equal to the threshold voltage value of the N-type transistor. In addition, the voltage of the high-level power supply VDD (“1”) and the voltage of the logical unit VCC (“1 *”) must be greater than or equal to the sum of the threshold voltages of the P- and N-type transistors. The low conductivity P-type 1 transistor is always open because its shutter is connected to a low voltage power source “0”. To the gates of N-type transistors 8 and 9 from the inputs IN and

the voltages of the correspondingly low GND level (“0”) and the voltage of the logical unit “1 *” (VCC) are supplied. Therefore, the transistor 8 is closed, and the transistor 9 is open. Also, as a result of the previous regenerative cycle, transistors 2, 6, 10, and 11 are open, and transistors 3, 4, 5, 7, and 12 are closed. Therefore, the low voltage “0” (GND) is set at the OUT output of the voltage level converter through an open transistor 10.

и, следовательно, на затворы транзисторов 8 и 9 поступают напряжения соответственно логической единицы «1*» (VCC) и логического «0» (GND), в результате чего транзистор N-типа 8 открывается, а транзистор N-типа 9 - закрывается. Через открытый транзистор 8 на затворы транзисторов 3, 5, 7, 10 и 11 поступает напряжение низкого уровня «0» (GND). Поэтому транзисторы P-типа 3, 5 и 7 открываются, а транзисторы N-типа 10 и 11 - закрываются, и через открытые транзисторы 3, 5 и 7 напряжение высокого уровня VDD поступает на затворы транзисторов 2, 4, 6, 12 и на выход OUT преобразователя уровня напряжения. При этом транзисторы P-типа 2 и 6 закрываются, транзистор P-типа 4 удерживается в закрытом состоянии напряжением высокого уровня VDD, поступающим через открытые транзисторы P-типа 1 и 3, а транзистор N-типа 12 - открывается. Таким образом, на выходе OUT преобразователя уровня напряжения установлено напряжение высокого уровня VDD, полученное преобразованием входного высокого напряжения логической единицы «1*» (VCC).In the mode of converting a high voltage of a logical unit VCC to a high level voltage VDD at input IN and input

and, therefore, the gates of 1 * (VCC) and logical 0 (GND), respectively, are supplied to the gates of transistors 8 and 9, as a result of which the N-type transistor 8 opens, and the N-type transistor 9 closes. Through the open transistor 8, the gates of the transistors 3, 5, 7, 10, and 11 receive a low level voltage "0" (GND). Therefore, the P-type transistors 3, 5 and 7 open, and the N-type transistors 10 and 11 are closed, and through the open transistors 3, 5 and 7, the high level VDD voltage is supplied to the gates of the transistors 2, 4, 6, 12 and to the output OUT voltage level converter. In this case, the P-type transistors 2 and 6 are closed, the P-type 4 transistor is kept closed by the high-level voltage VDD supplied through the open P-type transistors 1 and 3, and the N-type transistor 12 opens. Thus, at the output OUT of the voltage level converter, a high level voltage VDD is obtained obtained by converting the input high voltage of the logical unit “1 *” (VCC).

- инверсного входного сигнала, и, следовательно, на затворы транзисторов 8 и 9, поступают соответственно напряжения логического «0» (GND) и логической единицы «1*» (VCC). Поэтому транзистор N-типа 8 закрывается, а транзистор N-типа 9 - открывается. Через открытые транзисторы N-типа 9 и 12 на затвор транзистора высокой проводимости P-типа 4 поступает напряжение низкого уровня GND («0»). Поэтому транзистор 4 открывается и через него на затворы транзисторов 3, 5, 7, 10 и 11 поступает напряжение высокого уровня VDD («1»), которое закрывает транзисторы P-типа 3, 5 и 7 и открывает транзисторы N-типа 10 и 11. Через открытый транзистор 10 на выход OUT преобразователя уровня напряжения поступает напряжение низкого уровня GND («0»). Одновременно через открытый транзистор 11 напряжение низкого уровня GND («0») поступает на затворы транзисторов 2, 6, 12. При этом транзисторы P-типа 2 и 6 открываются, а транзистор N-типа 12 закрывается. Поэтому через открытые транзисторы 1 и 2 на затвор транзистора 4 поступает напряжение высокого уровня VDD («1»), в результате чего транзистор P-типа 4 закрывается. Однако через открытый транзистор P-типа 6 на затворах транзисторов 3, 5, 7, 10 и 11 удерживается напряжение высокого уровня. Поэтому на выходе OUT преобразователя уровня напряжения сохраняется напряжение низкого уровня GND («0»), и схема переходит в исходное состояние.Upon transition of the voltage level converter to the initial state and the mode of formation at the output OUT of a low level voltage GND ("0") at the inputs IN - a direct input signal and

- inverse input signal, and, therefore, the gates of the transistors 8 and 9, respectively, are the logical voltage “0” (GND) and the logical unit “1 *” (VCC). Therefore, the N-type transistor 8 closes, and the N-type transistor 9 opens. Through the open N-type transistors 9 and 12, the low-level voltage GND (“0”) is supplied to the gate of the P-type 4 high conductivity transistor. Therefore, the transistor 4 opens and through it to the gates of the transistors 3, 5, 7, 10 and 11 receives a high level voltage VDD ("1"), which closes the P-type transistors 3, 5 and 7 and opens the N-type transistors 10 and 11 Through an open transistor 10, the low level voltage GND ("0") is supplied to the output OUT of the voltage level converter. At the same time, through the open transistor 11, the low-level voltage GND (“0”) is supplied to the gates of the transistors 2, 6, 12. In this case, the P-type transistors 2 and 6 open, and the N-type transistor 12 closes. Therefore, through the open transistors 1 and 2, a high level voltage VDD (“1”) is supplied to the gate of the transistor 4, as a result of which the P-type 4 transistor closes. However, through an open P-type transistor 6 at the gates of the transistors 3, 5, 7, 10 and 11, a high level voltage is held. Therefore, the low level voltage GND (“0”) is stored at the OUT output of the voltage level converter, and the circuit returns to its initial state.

Thus, in the proposed circuit of the voltage level converter, the formation of a high level output signal VDD (“1”) at the OUT output occurs immediately and only through high conductivity circuits, which significantly accelerates the transition process of overcharging the output capacitance and thereby increases the speed of the circuit.

In addition, in the proposed voltage level converter, in contrast to the known signal level converter for MOS transistors [1], in addition to the gates of the transistors of the output inverter, the gate of only one P-type transistor is connected to one gate of the trigger transistor, and the gate of only one transistor is connected to the other , generally without gates of the transistors of the output inverter, which significantly reduces the stray capacitance of the output nodes of the trigger and further accelerates the transition process of switching the voltage level converter.

Literature

1. USSR Author's Certificate (SU) No. 1538246, “Converter of signal levels on MIS transistors”, / V.A. Maximov, A.E. Zabolotny and Ya.Ya. Petrichkovich // Bulletin No. 3 of 01/23/90.

Claims (1)

A voltage level converter containing P-type field-effect transistors from first to seventh and N-type from eighth to eleventh, direct IN and inverse inputs

input signals connected to the gates of the transistors of the eighth and ninth, respectively, a high voltage level power supply terminal VDD connected to the source of the first transistor, a low voltage level power supply terminal GND connected to the sources of the eighth, tenth and eleventh transistors, the drain of the first transistor being connected to the sources of the second and third, the drain of the third with the drain of the ninth and the gate of the fourth transistors, and the gate with the drains of the fourth and eighth and the gates of the fifth and tenth transistors, the drains of which are interconnected and are the OUT output, the gate of the sixth transistor is connected to the drains of the seventh and eleventh transistors, the gates of which are interconnected, characterized in that a twelfth field-effect transistor of N-type is introduced into it, the drain of which is connected to the source of the ninth transistor, the source - the gate of the first transistor and the low voltage output GND, and the gate with the drain of the seventh transistor and the gate of the second, the drain of which is connected to the drain of the third, and the source of the sixth transistor is connected with the drain of the first th, and the flow - to the gate electrodes of the third and seventh, and the sources of the fourth, fifth and seventh transistors are connected to the high-level output power supply voltage VDD.

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