RU2615836C1 - Device for operators' training - Google Patents

Abstract

FIELD: information technology.

SUBSTANCE: device for operators' training comprises the assignment unit of the learning program, the operator response actions unit, three OR elements, the delay element, two comparator units, two AND elements units, the numbers register, two counters, the decoder, the trigger, the AND unit, the requirements correction unit, the command correction unit, the board, the analysis unit, the control unit, connected in a certain way. The analysis unit comprises the random access memory (RAM), and the permanent memory (ROM) devices, M of executive RAMs, the iterative comparison element, the comparison element, the intermediate RAM, the intermediate AND element and the AND element, connected in a certain way. The control unit contains a checking RAM and a counter.

EFFECT: operators training with the possibility of their warning about a possible emergency state of the system, based of the identification and verification data obtained.

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Description

The invention relates to technical means for training operators of control systems and can be used for practical training of operators on simulators.

A device for training operators, containing an address register (microcommands), a memory unit, a microcommand register, a panel of display elements made in the form of an information board, a control panel made in the form of an input unit for response of an operator, two comparison units, three OR elements, generator, delay elements, counter, trigger and sound alarm unit (see av. St. USSR No. 1437897, G09B 9/00, 1988).

However, this device has a narrow scope, because at the stage of developing skills of timely timely operation, the frequent inclusion of an audible alarm does not allow to consolidate skills when the operator develops complex control algorithms that occur in modern automated control systems (ACS).

A device for training operators is known (see RF patent No. 20111229, 5 G09B 9/00, 1994, bull. 7), containing a block for setting a training program, a block for operator response, start, main and installation elements OR, delay element, main and reciprocal comparison blocks, blocks of starting and interrogating elements AND, number register, start and main counters, decoder, trigger, element I and scoreboard.

The disadvantage of this device is the relatively low validity of assessing the correctness (error-freeness) of the actions of the operator (trainee) when practicing complex control algorithms in the conditions of continuous dynamics of the change of state of the control object and taking into account influencing factors.

The closest in technical essence to the claimed device (prototype) is a device for training operators (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22), containing a block for setting a training program, a block for operator response, starting, main and OR setting elements, delay element, main and response comparison blocks, blocks of starting and interrogating elements AND, number register, starting and main counters, decoder, trigger, element I, scoreboard, requirements correction block and command correction block, M≥2 information inputs The board odes are connected to the corresponding M outputs of the decoder, the M inputs of which are connected to the corresponding M outputs of the block of interrogating elements I, M of the counting inputs of which are connected to the corresponding M outputs of the main counter, the installation input “Set. "0" of which is connected to the first input of the OR start element, the second input of the OR installation element, the first input of the OR main element and is the "Start" input of the device, the output of the main OR element is connected to the counting input "Set. “1” of the main counter and the first control input of the training program task unit, the M indicator outputs of which are connected to the corresponding M indicator inputs of the board, the first control input of which is connected to the direct output of the trigger, the inverse output of which is connected to the first input of the And element and the second control input of the board , the first output of the main comparison unit is connected to the second input of the OR start element and the second control input of the training program task unit, the second output of the main comparison unit is connected n to the second input of the main OR element, the input of the delay element and the second input of the AND element, the output of which is connected to the counting input “Set. "1" start counter, installation input "Set. “0” of which is connected to the output of the start element OR, the output of the delay element is connected to the control input of the number register and to M information inputs of the block of start elements AND, M counting inputs of which are connected to the corresponding M outputs of the start counter, M outputs of the block of start elements AND are connected to the corresponding M information inputs of the response comparison block, the M response inputs of which are connected to the corresponding M outputs of the number register, the output of the response comparison block is connected to the first input of the OR element, the output of which is connected to the trigger input of the trigger, the resetting input of which is connected to the control output of the instruction block of the training program and to the M information inputs of the block of interrogating elements I, M outputs of the response block of the operator are connected to the corresponding M response inputs of the main comparison block, M indicator outputs of the command correction block are connected to the corresponding M indicator inputs of the scoreboard, M information outputs of the command correction block are connected to the corresponding M information the input inputs of the main comparison block, M information inputs of the command correction block are connected to the corresponding M information outputs of the training program task block, M control inputs of the command correction block are connected to the corresponding M control outputs of the requirements correction block, and M correction inputs of the number register are connected to the corresponding M correcting the outputs of the requirements correction block, the M inputs of which are the corresponding M inputs of the “Correction” device.

The prototype implements the possibility of a more informed analysis of the operator’s actions based on the dynamically adjusted number of resolved errors allowed by the student in a row when developing complex control algorithms.

However, the prototype has a drawback - the impossibility of identifying and verifying when training the operators of the boundary and emergency (catastrophic) states of the control object, the conditions characteristic of the emergency, critical position of the reliability and stability parameters of the object in a situation that can manifest itself with smooth changes in the parameters of the controlled object, due to (not explicitly) erroneous, but capable of generating and smoothly accumulating potential errors (threats) by control actions (microcommands of control) undertaken by the operator during training.

This situation may not immediately manifest itself during the next stage of the student’s control algorithm execution, the contents of one microoperation of the control algorithm, even in the case of an obvious error, does not always lead to a boundary and emergency (catastrophic) state of the system, however, the accumulation of potential control errors (threats) in the issue of saving reliability and stability with smooth and slight variations in the parameters of the managed object is very dangerous. The issues of identification and verification of possible catastrophic states of a controlled object are dealt with by a section of mathematical theory called catastrophe theory [1-3]. This theory is devoted to abrupt changes in the state of a controlled object, arising in the form of a sudden response of the system (object) to a smooth change of parameters caused by the control actions taken by the operator. Disasters at an ACS type control object can occur in the form of unexpected overloads of switching devices, sudden changes in the bandwidth of ACS control channels, abrupt changes in the parameters of the control signal propagation medium, etc. For example, in the course of teaching algorithms for dynamic multi-criteria control of the functioning of an object such as a multi-channel radio communication network, the operator (user) must generate control actions designed for a certain network bandwidth. However, during the operation of the multichannel radio communication network, along with a smooth drift of the parameters of the signal propagation medium (for example, changing the configuration of the reflecting tropospheric layer for tropospheric communication), a smooth increase in the intensity of subscriber conversations occurs, since the operator, not taking into account external conditions, allows (initiates) the connection subscribers. This is not a clear control error, but at an unforeseen moment of time it can lead to an abrupt change in the state of network throughput indicators, and as a result to a loss of reliability and stability of the functioning of the multichannel radio communication network as a whole, it can cause an avalanche-like change in throughput - collapse and network blocking .

An adequate device for training operators should be able to identify and verify the boundary and emergency (catastrophic) states of the control object, should be able to predict the possible catastrophic state of this object, thereby giving the user (operator) a hint, giving the opportunity to avoid states characteristic of emergency, critical position of the reliability and stability parameters of the control object. Failure to take into account the smooth possible change in the parameters of the control object, due to the smooth increase in the number of learner attempts that are not (not explicitly) erroneous, but capable of generating and accumulating potential errors (threats) of control actions (control micro-commands), simplifies the task of constructing an operator training device, but sharply reduces the degree of adequacy of the situations studied, the level of reliability of the environment and learning conditions.

The aim of the invention is the creation of a controlled device capable of training operators and identifying and verifying the boundary and emergency (catastrophic) states of the control object with smooth changes in the parameters of the object caused by the learner's control actions. With this in mind, it is necessary to create a device capable of timely notifying (warning) the trained system operator of its possible emergency state, based on the identification and verification data.

This goal is achieved by the fact that in a known device for training operators, containing a block for setting a training program, a block for operator response, start, main and installation elements OR, a delay element, main and response blocks for comparison, blocks of start and interrogating elements AND, number register , start and main counters, decoder, trigger, AND element, requirements correction unit, command and display correction unit, M≥2 information inputs of which are connected to the corresponding M outputs of the decoder, M inputs of which о connected to the corresponding M outputs of the block of interrogating elements AND, the M counting inputs of which are connected to the corresponding M outputs of the main counter, the installation input “Set. "0" of which is connected to the first input of the OR start element, the second input of the OR installation element, the first input of the OR main element and is the "Start" input of the device, the output of the main OR element is connected to the counting input "Set. “1” of the main counter and the first control input of the training program task unit, the first control input of the board is connected to the direct output of the trigger, the inverse output of which is connected to the first input of the AND element and the second control input of the board, the first output of the main comparison unit is connected to the second input of the start element OR and the second control input of the instruction block of the training program, the second output of the main comparison unit is connected to the second input of the main OR element, the input of the delay element and the second input of the AND element, output It is connected to the counting input "Const. "1" start counter, installation input "Set. “0” of which is connected to the output of the start element OR, M counting inputs of the block of start elements AND are connected to the corresponding M outputs of the start counter, M outputs of the block of start elements AND are connected to the corresponding M information inputs of the response block of comparison, M response inputs of which are connected to the corresponding M the outputs of the number register, the output of the response block comparison is connected to the first input of the installation element OR, the output of which is connected to the installation input of the trigger, resetting the input of which is connected It is suitable for the control output of the training program task unit and the M information inputs of the block of interrogating elements I, M outputs of the operator response block are connected to the corresponding M response inputs of the main comparison block, M information outputs of the command correction block are connected to the corresponding M information inputs of the main comparison block, M information inputs of the command correction block are connected to the corresponding M information outputs of the training program job block, M control inputs of the correction block mandates are connected to the corresponding M control outputs of the requirements correction unit, M correcting inputs of the number register are connected to the corresponding M correcting outputs of the requirements correction unit, M inputs of which are the corresponding M inputs of the Correction device, the first control input of the board connected to the input of the Exercise banner , the second control input of the scoreboard is connected to the input of the “Training” banner, and the M information inputs of the scoreboard are connected to the corresponding M inputs of the indicator of the track number irovki additionally introduced analysis unit and control unit. The output of the delay element is connected to the control input of the number register, with M information inputs of the block of start elements AND, with the clock input of the control unit and the clock input of the analysis unit, the test input of which is connected to the output of the control unit, the control input of which is the input “Control input” devices, M indicator outputs of the training program task unit are connected to the corresponding M indicator outputs of the command correction unit and connected to the corresponding M control inputs of the analysis unit, M y ravlyaetsya whose outputs are connected to respective M inputs of an indicator board, which are connected to respective M inputs of the display panel, and a warning output is the output of the analysis block "threat" device.

The analysis unit consists of a central random access memory (RAM), M executive RAM, read-only memory (ROM), an iterative comparison element, a comparison element, intermediate RAM, an intermediate element I, and an element I. Moreover, the M control inputs of the central RAM are corresponding to M the control inputs of the analysis unit, the M control outputs of the central RAM are the corresponding M control outputs of the analysis unit, the clock input of the central RAM is connected to the clock input of the PZ U and is the clock input of the analysis unit, M executive outputs of the central RAM are connected to the inputs M of the corresponding executive RAM, the inputs of the M executive RAM are combined and connected to the first input of the iterative comparison element and the second input of the comparison element, the outputs of the M executive RAM are combined and connected to the second input element of iterative comparison. The output of the ROM is connected to the first input of the comparison element, the output of the iterative comparison element is connected to the input of the intermediate RAM and the second input of the intermediate element And, the first input of which is connected to the output of the intermediate RAM. The output of the intermediate element And is connected to the output of the comparison element and the first input of the element And, the second input of which is connected to the test input of the ROM and is the test input of the analysis unit. The output of the AND element is connected to the read input of the central RAM and is a warning output of the analysis unit and the output “Threat” of the device.

The control unit consists of a test RAM and a counter. In this case, the clock output of the counter is connected to the clock input of the test RAM, the resetting output of which is connected to the resetting input of the counter, the clock input of which is the clock input of the control unit. The test output of the test RAM is the output of the control unit, the control input of the test RAM is the control input of the control unit and the input "Control input" of the device.

The principle of creating the proposed controlled device for training operators is based on the known results of research in the field of catastrophe theory, described in [1-5]. Analysis of these works allows us to generate a mathematically correct algorithm for identifying and verifying boundary and emergency (catastrophic) states that are characteristic of emergency, critical position of the reliability and stability parameters of the control object, for a situation that can manifest itself with smooth changes in the parameters of the control object due to not clearly erroneous, but capable of generating and smoothly accumulating potential errors control actions (control micro-commands) undertaken by the opera torus during training. Indeed, there are objective control micro-commands that, by their nature, are not obvious errors made by the trainee during the development of complex control algorithms, but predetermine the smooth drift of the parameters of the control object to a boundary and emergency (catastrophic) state, cause smooth movement (“rolling”) object to failure (collapse).

Thus, in the framework of controlled training of operators, the problem of a priori estimation and comparison of the values of the limit number of control microcommands is solved, which, while not being obvious errors (erroneous microcommands), determine the smooth drift of the parameters of the control object to a boundary and emergency (catastrophic) state. From the point of view of physical interpretation, this is a process of a priori statistical analysis of smooth and minor changes in control actions on the system with the possibility of notifying (warning) the operator (trainee) of potential catastrophic consequences in the behavior of the object, consequences that at first glance are not visible and almost never taken into account in the implementation of facility management algorithms and in the training of control system operators.

With this approach to operator training, it is possible to present the dynamics of changes in the state of the control object with smooth and insignificant variations of control actions, in the form of dynamics of changes at the indicator outputs of the training program task unit and the command correction block of a certain limit of the number of micro-commands (micro-operations) of control, which nature, are not obvious errors, but predetermine a smooth drift of the parameters of the control object to the boundary and emergency (catastrophic) state, cause smooth "rolling" of the object to failure (collapse). Analysis of the results of works [1-5] allows us to provide the device with the possibility of identifying and verifying the boundary and emergency (catastrophic) states of the controlled system with smooth changes in the parameters of control actions undertaken by the student.

The mathematical formalization of the parameters of the control actions taken by the student and affecting the behavior of the system can be represented by statistical determination on the indicator outputs of the training program task unit and the command correction block, corresponding values of the number of control micro commands (micro operations) entered by the student, which, by their nature, are not are obvious errors, but predetermine a smooth drift of the parameters of the control object to the boundary and emergency (catastrophic) with the state for each mth level of identification of its states, where the degree of detail (completeness) of the identification of the states of the control system is M≥2; m = 2, ..., M; M = 20.

The number N, where n = 1, 2, ... N, of the control micro-commands (micro-operations) introduced by the learner, which, by their nature, are not obvious errors, but predetermine the smooth drift of the parameters of the control object to the boundary and emergency (catastrophic) state for each m level of identification of its states (each n _m ), is determined by the capabilities of the control system, its reliability, stability, boundary values of the performance of the control object, and can be, for example, from 1 (one) to 50 (fifty).

The total number of such values is N _M and these values are many:

where each mth element of the set, except for N _M (k + 1), is a subset of N _m and has the physical meaning of exceeding the threshold of the system’s capabilities for reliability and stability and, as a consequence, the high probability of the control object going into emergency (catastrophic) state by the next step is (k + 1) learning.

Obviously, to solve the problem of a priori estimation and comparison of the number of control micro-commands (micro-operations) entered by the learner, which, by their nature, are not obvious errors, but predetermine smooth drift of parameters with smooth changes in control actions, it is necessary to carry out current step-by-step monitoring, to identify and verification of boundary and emergency (catastrophic) states of the system (control object).

The identification of the boundary and emergency (catastrophic) states of the control object is carried out by stepwise (step-by-step, where k is the training step (step)) a priori estimation and comparison of the values of each m-th of n _m elements of the set N _m in order to determine the presence or absence of possible excess of these values of the acceptable threshold defined by the expression:

where N _m is the value of the number of control micro-commands (microoperations) entered by the learner, which, by their nature, are not erroneous, but, when exceeded, the control object is likely to become emergency (catastrophic) for each m-th level of identification of the state of the object a state from any other state. Exceeding, at one of the following (k + 1) training steps, by any n _m- th of N elements of the set N _{m of a} given threshold, characterizes the beginning of a smooth change in the parameters of control actions.

Verification of the boundary and emergency (catastrophic) states of a controlled object is a process independent of identification, which characterizes the excess of the value of any n _mth of N elements of the set N _m at this kth step (step) of the learning process over the value of the same element at the next ( k + 1) -th step (measure) and is performed by a priori estimation of the values of each n _m of the N elements of the set N _m at the k-th step (measure) and comparing the obtained value with the estimated value of the same element at the next (k + 1) th step (measure) in accordance obstacle to the expression:

The physical meaning of the verification process is to identify the trend of changes in the control actions introduced by the learner (the volume of the flow of microcommands (microoperations) of control, which, by their nature, are not obvious errors, but predetermine the smooth drift of the object's parameters) towards the boundary and emergency (catastrophic) state of the object management.

In both cases of a priori estimation and comparison of the values of the number of microcommands (microoperations) of control, which, while not erroneous, nevertheless predetermine a smooth drift of the object's parameters towards the accident - as in the process of identifying the boundary and emergency (catastrophic) states of the system, when it is identified event

and during the verification process, when the trend of changing the parameters of the control actions entered by the operator towards the boundary and emergency (catastrophic) state of the system is confirmed

the trainee (user, operator) performing the control of the object must be notified (warned) of a possible emergency state of the control object.

If the trainee (user, operator) is not able to affect the undesirable change in the parameters of the introduced control actions (the number of microcommands (microoperations) of control that predetermine the smooth drift of the object's parameters towards a boundary and emergency (catastrophic) state) or needs, for example, for the learner to gain control skills in critical conditions, in obtaining precisely the boundary and emergency (catastrophic) states of the system, the learning process will be carried out without correcting the number of such micro team (microoperations) or threshold values of this quantity.

If the trainee (user, operator), in accordance with the introduced learning algorithm, can and is capable of influencing an undesirable change in the parameters of the introduced control actions (the number of microcommands (microoperations) of control that predetermine the smooth drift of the object's parameters towards the boundary and emergency (catastrophic) state) and the process of operator training is carried out in the framework of dynamic optimal control of the system, when emergency conditions of this system are unacceptable, based on the received data ide During verification and verification, an external correction of the number of such microcommands (microoperations) or their threshold values takes place in order to prevent an emergency (catastrophic) abrupt change in the state of the system with small managerial disturbances [2].

Examples illustrating similar operations, from the point of view of catastrophe theory, of preventing the loss of stability and reliability of complex controlled systems under smooth changes in both external conditions and control actions, are given in [1] and [2]; here, algorithms for analyzing the structural stability of objects and assessment of critical points (Morse points) during the functioning of the system, characterizing local maxima and minima of the stable (not catastrophic) behavior of the object under smooth changes in external conditions and led administrations.

An analysis of expressions (1) - (5) allows us to conclude that it is technically feasible to implement the training process for operators and the processes of identification and verification of boundary and emergency (catastrophic) states of a control object with smooth changes in the parameters of this object due to the control actions being taken by the student.

Thanks to the new set of essential features, through the introduction of an analysis unit designed to carry out identification and verification procedures for the boundary and emergency (catastrophic) states of the control object with smooth changes in the parameters of this object due to the control actions being taken by the learner, as well as to generate logical zero or logical signals units (prediction and warning signals), characterizing respectively the absence or presence of a possible catastrophic the state of the control object, and the control unit, designed to generate a control code sequence, a sequence of threshold values of the number of microcommands (microoperations) of control, which predetermine a smooth drift of the object parameters towards a boundary and emergency (catastrophic) state, as well as to generate a logical zero or logical signal units characterizing respectively the prohibition or permission of the trainee (user, operator) to issue a cash alert signal and the possible catastrophic state of the control object, the claimed device achieves the ability to provide an increase in the degree of adequacy of the studied situations, increase the level of reliability of the environment and learning conditions. In the claimed device, it is possible to provide training for operators and to identify and verify the boundary and emergency (catastrophic) states of the control object with smooth changes in the parameters of the object due to the control actions undertaken by the learner (the number of micro-commands (microoperations) of control that determine the smooth drift of the parameters of the object towards the boundary and catastrophic state), as well as the ability to promptly alert (warn) the operator (train oh, the user) about the possible emergency state of the control object, based on the identification and verification data.

The claimed device is illustrated by drawings, on which are presented:

in FIG. 1 is a block diagram of a device for training operators;

in FIG. 2 is a block diagram of an analysis unit;

in FIG. 3 is a structural diagram of a control unit;

in FIG. 4 is a block diagram of a task unit of a training program;

in FIG. 5 is a block diagram of a block of starting elements And;

in FIG. 6 is a block diagram of a block of polling elements AND;

in FIG. 7 is a block diagram of a number register;

in FIG. 8 is a block diagram of a requirements correction unit;

in FIG. 9 is a block diagram of a command correction block;

The operator training apparatus illustrated in FIG. 1, consists of a unit for setting a training program 1, a response unit for operator 2, start 7, main 13 and installation 18 OR elements, a delay element 21, main 3 and response 19 comparison blocks, start 8 blocks and interrogation 10 AND elements, a number register 20, start 6 and main 11 counters, decoder 12, trigger 9, element 5, requirements correction unit 22, commands correction unit 23, analysis unit 24, control unit 25 and scoreboard 4, M≥2 information inputs 44 ₁ -44 _M which are connected to respective M outputs 121 ₁ -121 _M decoder 12. M passages 122 ₁ -122 _M are connected to respective M outputs 103 ₁ -103 _M block polling of the AND 10, M counter inputs 101 ₁ -101 _M are connected to the respective M outputs 111 ₁ -111 _M main counter 11, adjusting the input "Set . "0" which is connected to the first input 71 of the starting element OR 7, the second input 182 of the installation element OR 18, the first input 131 of the main element OR 13 and is the input "Start" of the device. The output 133 of the main element OR 13 is connected to the counting input "Set. "1" of the main counter 11 and the first control input 013 of the task block for the training program 1. The first control input 41 of the board 4 is connected to the direct output 91 of the trigger 9, the inverse output 92 of which is connected to the first input 51 of the element And 5 and the second control input 42 of the board 4 , the first output 33 of the main comparison unit 3 is connected to the second input 72 of the starting element OR 7 and the second control input 014 of the unit for setting the training program 1, the second output 34 of the main unit of comparison 3 is connected to the second input 132 of the main element OR 13, input 211 of the delay element ki 21 and the second input 52 of the element And 5, the output 53 of which is connected to the counting input "Set. "1" start counter 6, installation input "Set. "0" which is connected to the output 73 of the start element OR 7. At the same time, M counting inputs 81 ₁ -81 _{M of the} block of starting elements And 8 are connected to the corresponding M outputs 61 ₁ -61 _{M of the} starting counter 6, M outputs 83 ₁ -83 _{M of the} block starting elements And 8 are connected to the corresponding M information inputs 191 ₁ -191 _{M of the} response block 19, M response inputs 192 ₁ -192 _{M of} which are connected to the corresponding M outputs 2021 -202 _M register number 20. Output 193 of the response block 19 is connected to the first input 181 of the installation element OR 18, the output 183 of which is connected nen a mounting trigger input 93 9 resetting input 94 of which is connected to the control unit output 015 courses task 1 and M data inputs 102 ₁ -102 _M block polling of the AND 10, M outputs 021 ₁ -021 _M unit operator response 2 connected to the corresponding M response inputs 31 ₁ -31 _{M of the} main comparison block 3, M information outputs 233 ₁ -233 _M of the command correction block 23 are connected to the corresponding M information inputs 32 ₁ -32 _{M of the} main comparison block 3, M information inputs 231 ₁ - 231 _M command correction unit 23 By connecting the respective output information M 012 ₁ -012 _M courses setting unit 1, M control inputs 234 ₁ -234 _M command correction unit 23 connected to the respective M outputs control 222 ₁ -222 _M requirement correction unit 22, M corrective inputs 203 ₁ The -203 _M register of number 20 is connected to the corresponding M correcting outputs 223 ₁ -223 _M of the requirements correction block 22, whose M inputs 221 ₁ -221 _M are the corresponding M (K ₁ -K _M ) inputs of the “Correction” device. Moreover, the first control input 41 of the board 4 is connected to the input 151 of the banner “Exercise” 15, the second control input 42 of the board 4 is connected to the input of the banner “Training” 16, and the M information inputs 44 ₁ -44 _{M of the} board 4 are connected to the corresponding M inputs 171 ₁ -171 _{M of} the training number indicator 17. At the same time, the output 212 of the delay element 21 is connected to the control input 201 of the register of the number 20, with M information inputs 82 ₁ -82 _{M of the} block of starting elements And 8, with a clock input 253 of the control unit 25 and with a clock input 243 analysis units 24, test input 244 connected to the output 252 of control unit 25, a control input 251 which is the input "input control" device M of indicator outputs 011 ₁ -011 _M training program setting unit 1 are connected to respective indicator M outputs 232 ₁ -232 _M command correction unit 23 and connected to the corresponding M control inputs 241 ₁ -241 _M of the analysis unit 24, M control outputs 242 ₁ -242 _{M of} which are connected to the corresponding M indicator inputs 43 ₁ -43 _{M of the} display 4, which are connected to the corresponding M inputs of 141 ₁ -141 _{M of} the display panel 14, and warning output 245 of the analysis block 24 is the output of "threat" device.

The number "M, (M≥2; m = 2, ..., M)" (inputs, outputs, AND elements, counters, etc.) is determined in accordance with the necessary and sufficient for the training of operators degree of detail (completeness) of state identification management system and, as a rule, ranges from 2 (two) to 20 (twenty).

The number “N, (n = 1, 2, ..., N)” (micro-commands (micro-operations), inputs, outputs, etc.) is determined in accordance with the capabilities of the control system, its reliability, stability, and boundary values of the performance of the control object, and may be, for example, from 1 (one) to 50 (fifty).

Analysis block 24 is designed to carry out identification and verification procedures for the boundary and emergency (catastrophic) states of the control object during smooth changes in the parameters of this object due to the control actions taken by the learner, as well as to generate logical zero or logical unit signals (prediction and warning signals) characterizing accordingly, the absence or presence of a possible catastrophic state of the control object.

Analysis block 24 (Fig. 2) consists of a central RAM 24.0, M executive RAM 24.1 ₁ -24.1 m, ROM 24.2, an iterative comparison element 24.3, a comparison element 24.4, an intermediate RAM 24.5, an intermediate element I 24.6 and an element I 24.7, and M the control inputs 24.0-1 ₁ -24.0-1 _{M of the} central RAM 24.0 are the corresponding M control inputs 241 ₁ -241 _M of the analysis unit 24, the M control outputs 24.0-2 ₁ -24.0-2 _{M of the} central RAM 24.0 are the corresponding M control outputs 242 ₁ -242 _M analysis unit 24. Clock input 24.0-3 of the central RAM 24.0 is connected to the clock input ode 24.2-1 ROM 24.2 and is a clock input 243 analysis unit 24, M Executive outputs 24.0-4 ₁ -24.0-4 _M Central RAM 24.0 connected to the inputs M of the corresponding Executive RAM 24.1 ₁ -24.1 m - Inputs M Executive RAM 24.1 ₁ - 24.1 _{M are} combined and connected to the first input 24.3-1 of the iterative comparison element 24.3 and the second input 24.4-2 of the comparison element 24.4, the outputs M of the executive RAM 24.1 ₁ -24.1 _{M are} combined and connected to the second input 24.3-2 of the iterative comparison element 24.3. The output of the ROM 24.2 is connected to the first input 24.4-1 of the comparison element 24.4, the output of the iterative comparison element 24.3 is connected to the input of the intermediate RAM 24.5 and the second input 24.6-2 of the intermediate element And 24.6, the first input 24.6-1 of which is connected to the output of the intermediate RAM 24.5. The output of the intermediate element And 24.6 is connected to the output of the comparison element 24.4 and the first input 24.7-1 of the And 24.7 element, the second input 24.7-2 of which is connected to the test input 24.2-2 of the ROM 24.2 and is the test input 244 of the analysis unit 24. The output of the And 24.7 element is connected with a read input 24.0-5 of the central RAM 24.0 and is a warning output 245 of the analysis unit 24 and the output “Threat” of the device.

Central RAM 24.0 of analysis block 24 is intended for writing, storage, reading in the interests of checking (identification and verification) from M executive outputs 24.0-4 ₁ -24.0-4 _M in binary code of the values of the number of micro-commands (microoperations) of control, which, while not erroneous nevertheless, a smooth drift parameters predetermine object toward an emergency condition, and for reading from M control outputs ₁ 24.0-2 -24.0-2 _M binary signals describing the contents of microinstructions (uops) control corresponding TEKU his step, the control algorithm trained. Central RAM 24.0 can be technically implemented based on the high-speed RAM of the 155 series (for example, K155RU2), as shown in [Shilo V.L. Popular Digital Chips: A Guide. - M .: Radio and communications, 1987 .-- 352 s, S. 164-166, fig. 1.121].

Executive RAM 24.1 ₁ -24.1 _M analysis unit 24 are identical and are designed to write, store and read in binary code from memory cells the values of n (input by the trained micro-commands (micro-operations) of control, which, by their nature, are not obvious errors, but predetermine smooth drift of the parameters of the control object to the boundary and emergency (catastrophic) state from the set N (the admissible value of the number of control micro commands (micro operations) entered by the student) at the Atom (previous) step (step) of training. Executive RAM 24.1 ₁ -24.1 _M can be technically implemented on the basis of a typical dynamic RAM described in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulse and digital technology. - SPb .: SPVVIUS, 1995, - 248 s, S. 194-196, fig. 6.9 (a)].

The read-only memory device 24.2 of the analysis unit 24 is intended for pre-recording, storing and reading in binary code from the memory cells to the first input of the comparison element 24.4 of the pre-recorded each valid value (threshold) -number n _m for each m-th element from the set Nm, allowing determine the presence or absence of a possible excess of this allowable threshold in accordance with expression (2). Technical implementation of ROM 24.2 is possible by analogy with the two-input re-programmable ROM described in [Gusev VV, Lebedev O. .. Sidorov AM Fundamentals of pulse and digital technology. - SPb .: SPVVIUS, 1995, - 248 s, S. 199-205, fig. 6.12].

The iterative comparison element 24.3 of analysis block 24 is intended for sequential (step-by-step, step-by-step) a priori estimation and comparison of the values of each n _m -th of N elements of the set N _M at this k-th step (step) of the learning and operation of the device with the value of the same element at the next (k + 1) -th step (measure) in accordance with expression (3). The iterative comparison element 24.3 can be technically implemented on the basis of a commercially available digital comparison unit (digital comparator), as shown in [Gusev VV, ON Lebedev, Sidorov AM Fundamentals of pulse and digital technology. - SPb .: SPVVIUS, 1995 .-- 248 p., S. 149-152, fig. 5.19].

Comparison element 24.4 of analysis block 24 is intended for sequential (step-by-step, cycle-wise) a priori estimation and comparison of a pre-recorded allowable value (threshold) of the number of control micro-commands (micro-operations) entered by the student N _m for each m-th level of identification of object states with real values of the number of micro-commands ( microoperations) control, in order to determine the presence or absence of the possible excess of these values of the allowable threshold in accordance with expression (2). Comparison element 24.4 is a digital comparison node (digital comparator) described in [Gusev VV, Lebedev OP, Sidorov AM Fundamentals of pulse and digital technology. - SPb .: SPVVIUS, 1995 .-- 248 s, S. 149-152, fig. 5.19].

The intermediate RAM 24.5 of the analysis unit 24 is intended for recording, intermediate storage and reading in binary code of a logical zero or logical unit characterizing the result of identification and verification obtained at the kth step (clock) of training. Intermediate RAM 24.5 can be implemented on the basis of dynamic RAM described in the literature [Gusev VV, Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995 .-- 248 s, S. 194-196, fig. 6.9 (a)].

Intermediate element I 24.6 of analysis block 24 is intended to compare the obtained identification and verification result (logical zero or logical unit) at the k-th step (cycle) of the learning cycle with the identification and verification result (logical zero or logical unit) obtained on (k + 1) -th step (step) of the learning cycle. A special case of the technical implementation of the intermediate element And 12.6 is described in [Gusev VV, Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995.-248 s, S. 13-14, Fig. 1.2].

Element I 24.7 of analysis block 24 is intended to confirm (in fact, verification) the identified trend of changes in the control actions introduced by the learner (the volume of the flow of microcommands (microoperations) of control, which, by their nature, are not obvious errors, but predetermine a smooth drift of object parameters) towards the boundary and emergency (catastrophic) state of the control object, as well as for the implementation of the procedure for notifying the operator (trainee, user) about a possible catastrophic state. Element I 24.7 can be technically implemented on the basis of a typical logical element And described in [Gusev V.V., Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995 .-- 248 s, S. 13-14, Fig. 1.2].

The control unit 25 is designed to generate a control code sequence (consisting of elements of the set N _M (see expression (1), where N _m is the value of the number of control micro-commands (microoperations) valid for each m-th state that predetermines smooth drift of the object parameters to the side catastrophe), when the values of which are exceeded, the object is likely to go into an emergency (catastrophic) state from any other state, as well as to generate a signal of a logical zero or logical unit, The prohibition or permission of the trainee (user, operator) to issue a warning signal about the presence of a possible catastrophic state of the control object, respectively.

The control unit 25 (Fig. 3) consists of a test RAM 25.0 and a counter 25.1. Clock output 25.1-3 of counter 25.1 is connected to clock input 25.0-3 of test RAM 25.0, reset output 25.0-2 of which is connected to reset input 25.1-2 of counter 25.1, clock input 25.1-1 of which is clock input 253 of control unit 25. Test output 25.0-4 of the test RAM 25.0 is the output 252 of the control unit 25. The control input 25.0-1 of the test RAM 25.0 is the control input 251 of the control unit 25 and the input “Control input” of the device.

The test RAM 25.0 of the control unit 25 is intended for recording, storing and reading in binary code a sequence of permissible (threshold) values of the number of micro-commands (micro-operations) of control, which, while not erroneous, nevertheless predetermine a smooth drift of the object parameters towards the emergency state, and also recording logical zero or logical units, characterizing respectively the prohibition or permission of the trainee (user, operator) to issue a warning signal about the presence of a possible disaster the physical state of the control object. Technical implementation of test RAM 25.0 is possible on the basis of a typical dynamic RAM described in [Gusev VV, Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.248 s, S. 194-196, fig. 6.9 (a)].

The counter 25.1 of the control unit 25 is designed to determine the start time of reading the newly entered control actions in binary code - new admissible (threshold) values of the number of microcommands (microoperations) of control, which, while not erroneous, nevertheless predetermine a smooth drift of the object parameters in the direction of emergency the state, as well as the moments of the beginning of reading a logical zero or logical unit, characterizing, respectively, the prohibition or permission of the student (user, operator) to issue with drove publicize the existence of possible catastrophic state of the control object. The description of the operation and the circuit of such a counter are known and are given, for example, in [Maltsev P.P., Dolidze N.S. et al. Digital Integrated Circuits: A Guide. - M .: Radio and communications, 1994, S. 64-65].

The task block of the training program 1, which is part of the general block diagram, is designed to record and store unchanged parameters of the control algorithm worked out by the human operator. The composition of the task block of the training program 1 and the principle of its action are known, the circuit is described in detail in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22, Fig. 5) and is shown in FIG. 4 of this description.

The response unit of operator 2, which is part of the general block diagram, is intended for the operator to type (generate) a control action code and transmit the generated signal for verification in accordance with the training algorithm. The response block of the operator 2 is a typical keyboard, which in the traditional combination with the display panel 14 of the board 4 (screen, monitor) is a physical model of the operator’s console of a real ACS. The block diagram and principle of operation of the response block of the operator 2 are known and described, for example, in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22).

The main comparison unit 3, which is part of the general block diagram, is designed to assess the accuracy of the control action generated by the operator. The main comparison unit 3 is a digital comparison unit, described in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22) and can be technically implemented as a commercially available comparison unit (digital comparator), as shown in work [Gusev VV, Lebedev O.N., Sidorov AM Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 149-152, Fig. 5.19].

Table 4, which is part of the general structural scheme, is intended to indicate (visualize in the interests of the learner) the state of the control algorithm, the training mode (exercise or training) and the training number at which the learner manages to complete the control algorithm without errors. Scoreboard 4 consists of a combined display panel 14, a banner “Exercise” 15, a banner “Training” 16 and an indicator of the training number 17. The composition of the elements of the scoreboard 4, their relationship and the principle of their action are known and described in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22).

Element And 5, which is part of the general block diagram, is designed to record operator errors and switch the counting input “Set. "1" start counter 6 in the interests of counting operator errors. Element And 5 can be technically implemented on the basis of a commercially available element And described in [Gusev VV, Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 13-14, Fig. 1.2].

The start counter 6, which is part of the general block diagram, is designed to count the number of errors made in a row at the operator training stage. A special case of the technical implementation of the start counter 6 is described in [Sobotka 3., Stary Ya. Microprocessor systems. - M .: Energoizdat, 1981. S. 96-100].

The starting element OR 7, which is part of the general block diagram, is designed to combine signals to the installation input "Set. “0” of the start counter 6 for resetting it with the start of training - from the external input “Start” of the device and in the case of error-free execution of the current operation - from the first output 33 of the main comparison unit 3. The start element OR 7 can be technically implemented on the basis of a commercially available element OR, described in detail in [Gusev VV, Lebedev ON, Sidorov AM Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.S. 24-26, Fig. 1.7].

Blocks of starting 8 and polling 10 elements of And, included in the general structural diagram, are identical, and M of the same type of elements of And (8.1 ₁ -8.1 _M and 10.1 ₁ - 10.1 _M, respectively), which are part of the blocks of starting 8 and polling 10 of And elements, perform the functions of the switching elements during the interrogation of the contents of the start 6 and main 11 counters, respectively. The structure of the starting blocks 8 and the questionnaire 10 elements And is known, described in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22, Fig. 6 and 7, respectively) and is illustrated in FIG. 5 and 6, and the elements I (8.1 ₁ -8.1 _M and 10.1 ₁ -10.1 _M ) that are part of these blocks are implemented as known and described in [Gusev VV, Lebedev OP, Sidorov AM Fundamentals pulse and digital technology. - St. Petersburg: SPVVIUS, 1995.S. 13-14, Fig. 1.2].

The trigger 9, which is part of the general block diagram, is designed to control the illumination of the banner “Exercise” 15 or the banner “Training” 16 of scoreboard 4 in the corresponding training mode. Trigger 9 can be technically implemented as a commercially available single-stage trigger with collector-base connections, as shown in [Gusev VV, Lebedev ON, Sidorov A.M. Fundamentals of pulsed and digital technology. - SPb .: SPVVIUS, 1995.S. 72-73, Fig. 3.2 (b)].

The main counter 11, which is part of the general structural diagram, is designed to count the number of attempts spent by the student before the first error-free execution of the control algorithm. The main counter 11 can be technically implemented as a binary counter with sequential transfer on T-flip-flops, its structure and principle of operation are known, described in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22).

The decoder 12, which is part of the general block diagram, is designed to convert the binary code of the contents of the main counter 11 to a decimal code in the interests of presenting (visualizing, displaying) the learner the attempt number using the indicator of the training number 17 scoreboard 4. The decoder 12 can be technically implemented as a serial the manufactured decoder, its structure and principle of operation are known, described in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22).

The main element OR 13, which is part of the general block diagram, is designed to combine the first control input 013 of the task block of the training program 1 with the external input “Start” of the device and the second output 34 of the main block of comparison 3 to initialize the start of a new training after the device is turned on or the student makes an error . The main element OR 13 can be technically implemented on the basis of a commercially available element OR, its structure and principle of operation are known, described in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22).

The OR installation element 18, which is part of the general block diagram, is designed to combine the external “Start” input of the device with the output 193 of the response comparison unit 19 in the interest of transferring the trigger 9 to a single state and introducing the “Exercise” mode. The installation element OR 18 is implemented as a typical OR element, its structure and principle of operation are known, described in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22).

The response unit of comparison 19, included in the general structural diagram, is intended to compare the number of obvious errors that the student made with a predetermined allowable number of obvious errors. The response unit of comparison 19 can be technically implemented as a commercially available comparison unit (digital comparator), its structure and principle of operation are known, described in the prototype (see RF patent No. 2281560, G098 9/00, 2006, bull. 22).

The register of the number 20, which is part of the general structural scheme, is intended to compare the initial and newly introduced permissible number of obvious errors, their recording and storage. The register of number 20 consists of a comparison element 20.1 and a storage element 20.2, its operating principle is known, the circuit is described in detail in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22, Fig. 4) and is shown in FIG. . 7 of this description.

The delay element 21, which is part of the general block diagram, is designed to synchronize the moments of reading information from the elements And that are part of the block of start elements And 8 and from the register number 20 to the response block 19. The synchronous trigger can be a special case of the technical implementation of the delay element 21 delays (D-trigger), its structure and principle of operation are known, are described in detail in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22).

The requirements correction block 22, which is part of the general block diagram, is intended for the dynamic correction of the number of allowed obvious errors allowed by the student in a row while developing complex control algorithms. It consists of a controller-recorder 22.1 and a storage element of a new number 22.2, its operating principle is known, the circuit is described in detail in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22, Fig. 2) and is shown in FIG. 8 of this description.

The command correction block 23, which is part of the general block diagram, is intended for the dynamic correction of learning micro-commands in accordance with the number of explicit errors allowed introduced in the operator training control dynamics. The command correction block 23 consists of a comparison element 23.1 and a corrected microcommand register 23.2, its operating principle is known, the circuit is described in detail in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, bull. 22, Fig. 3) and depicted in FIG. 9 of this description.

A device for training operators operates as follows.

It is known [1-5] that from the point of view of ensuring an increase in the degree of adequacy of the situations studied, increasing the level of reliability of the environment and training conditions, from the point of view of implementing analysis and warning procedures for the operator (trainee, user) about the possible emergency state of the control object, there is a possibility as part of operator training, to identify and verify the boundary and emergency (catastrophic) states of the control object with smooth changes in the parameters of the object due to the undertaken and the learner by control actions (the number of control micro-commands (micro-operations) that predetermine the smooth drift of the object's parameters towards a boundary and catastrophic state).

This feature is implemented on the basis of the principle of dynamic, step-by-step (tick-wise) control of the values (boundaries) of the number of micro-commands (micro-operations) of control (which are not clearly erroneous, but, in the aggregate, that predetermine a smooth drift of the object's parameters towards a boundary and catastrophic state), using methods catastrophe theory.

It is obvious that during operator training, when the parameters of the control object change smoothly under the influence of the control actions taken by the learner, not only the number of control micro-commands (micro-operations) that predetermine the smooth drift of the object parameters towards a boundary and catastrophic state, but also the current requirements of the operator objectively change in time (learner, user) to the need for warning (warning) about a possible emergency state of the control object. Under these conditions, when a smooth change in parameters can lead to an abrupt change in the state of the control object, the reliable and stable functioning of this object is difficult, which directly depends on the dynamics of the control actions taken by the learner and due to the specific situation.

An analysis of the works [1-5] devoted to algorithms and principles for the implementation of catastrophe theory methods in the management of the functioning of complex technical systems allows us to conclude that it is possible, within the framework of operator training, to adequately study situations and to increase the level of reliability of the environment and training conditions based on technical implementation of procedures for identification and verification of possible boundary and emergency (catastrophic) states of the control object in the conditions of continuous dynamics of smooth change the intensity of control actions, a smooth change in the number of input micro-commands (micro-operations) of control, which, by their nature, are not erroneous, but when exceeded, the control object is likely to go into emergency (catastrophic) state from any other state.

The construction of a device for training operators on the basis of the proposed principle of operation allows us to gain an advantage over the prototype, providing an increase in the degree of adequacy of the situations studied, increasing the level of reliability of the environment and training conditions, when in the dynamics of training the number of input micro-commands (micro-operations) of control can smoothly change under the influence of the managers impacts, creating a potential threat of blocking (collapse) of the control object.

The technical implementation of the principle of dynamic, step-by-step (tick-wise) control of the values (boundaries) of the number of microcommands (microoperations) of control that predetermine a smooth drift of the object's parameters towards the emergency state using catastrophe theory methods in the claimed device is carried out by introducing an external dynamic control of the value of the allowable number of such microcommands ( microoperations) control, in excess of which the control object is likely to go into emergency (catastrophic) state from any other state (in the claimed device - input “Control input” of the device and control unit 25), by introducing an external dynamic control by generating a logic zero signal or logical unit, which characterize the prohibition or permission of the operator (trainee, user), respectively issuing a warning signal about the presence of a possible catastrophic state of the control object (in the claimed device - the input "Control input" of the device and the control unit 25) and the introduction of the identifier data and verification of boundary and emergency (catastrophic) states of a managed object, as well as the formation of logical zero or logical unit signals (prediction and warning signals), characterizing, respectively, the absence or presence of a possible catastrophic state of a managed object (implemented in the claimed device as part of analysis block 24) .

With this in mind, in the claimed device, along with the correction (control) of the number of explicit errors allowed that are made by the student in a row when developing complex control algorithms, the identification and verification of boundary and emergency (catastrophic) states of the control object is carried out, as well as the controlled formation of values of the allowable amount microcommands (microoperations) of control, which are not clearly erroneous, but predetermining a smooth drift of the object's parameters towards the boundary and catastrophically of state, causing increase of the degree of adequacy of the studied cases, improving the reliability of the environment and conditions in which the functions controlled by a real object.

With the device turned on, the binary signal “1” (one) from the “Start” input is supplied to the second input 182 of the OR installation element 18, through the first input 71 of the start element OR 7 to the installation input “Set. “0” of the start counter 6. to the installation input “Set. “0” of the main counter 11 and to the first input 131 of the main element OR 13, from the output of which it is fed to the counting input “Set. "1" of the main counter AND, writing in it "1" (unit) and through the first control input 013 is fed to the first input 1.1-1 of the address register of the micro command 1.1 of the unit for setting the training program 1, which can be implemented in accordance with the scheme proposed on FIG. 4. The micro-command address register 1.1 initiates permission to issue the address of the next micro-command corresponding to the first operation of the control algorithm and from its M outputs 1.1-3 ₁ -1.1-3 _M in binary code transfers it to M inputs 1.2-1 ₁ -1.2-1 _M memory item 1.2.

Upon receipt of this signal, the address of the microcommand corresponding to the first operation of the control algorithm is selected in the memory element of the firmware 1.2 of block 1. The selected micro-command is overwritten via M outputs 1.2-2 ₁ -1.2-2 _M of the microprogram 1.2 memory element on M inputs 1.3-3 ₁ -1.3-3 m of the micro-command register 1.3 of block 1. The micro-command register 1.3 of block 1 selects the control micro-operation corresponding to the address.

From the information outputs 1.32 ₁ -1.32 _M of the micro-command register 1.3 through the information outputs 012 ₁ -012 _M of the task block of the training program 1, the address corresponding microoperation of control in binary code is supplied to the information inputs 231 ₁ -231 _M of the command correction block 23, which can be implemented in according to the circuit of FIG. 9.

If during the training of operators there is no need for external dynamic control of the training process with the indication of obvious errors, it is impractical to initiate a dynamic correction of the allowed number of obvious errors made by the operator (trainee) in a row when developing control algorithms (for example, if the operator is knowingly prepared poorly and increase the starting level of complexity training impractical), on the M (K ₁ -K _m ) inputs of the “Correction” of the device, and therefore on the inputs 221 ₁ -221 _M , corrective 223 ₁ -223 _M and control 222 ₁ -222 _M output There are no signals at the odes of the requirements correction block 22, as well as at the control inputs 234 ₁ -234 _M of the command correction block. In this case, the register of the number 20 continues to store unchanged the previously recorded numerical value of the initial (starting) number of permissible obvious errors.

In this case, the command correction unit 23 shown in FIG. 9, acts as a transit node and operates as follows. Having not received any signals through the control inputs 234 ₁ -234 _{M of} block 23 to their control inputs 23.1-2 ₁ -23.1-2 _M , and at the same time, having received through the information inputs 231 ₁ -231 _M to their information inputs 23.1-1 ₁ -23.1 -1 _{M the} corresponding control microoperation code from block 1, the comparison element 23.1 identifies this control microoperation as uncorrectable and translates (rewrites) it through its outputs 23.1-3 ₁ -23.1-3 _M to the inputs 23.2-1 ₁ -23.2-1 _M register corrected microcommands 23.2 of block 23. Moreover, in the element of comparison 23.1 verification of compliance odov characterizing the initial allowable number of obvious errors and the new number of permitted manifest error does not occur. The register of corrected microcommands 23.2 of block 23 blocks its indicator outputs 23.2-2 ₁ -23.2-2 _M and from its information outputs 23.2-3 ₁ -23.2-3 _M , through the information outputs 233 ₁ -233 _{M of} block 23 sends the contents of this data in binary code non-correctable microoperation of the control to the information inputs 32 ₁ -32 _{M of the} main comparison unit 3. At the same time, from the indicator outputs 1.3-1 ₁ -1.3-1 _M of the micro-command register 1.3 the contents of the first non-correctable microoperation through the indicator outputs 011 ₁ -011 _M of the program task block Learning 1 enters The incoming inputs 241 ₁ -241 _M of the analysis unit 24 for starting the procedures for identification and verification of boundary and emergency (catastrophic) states of the control object.

If during the training of operators there is a need for external dynamic control of the training process with the indication of obvious errors, it is advisable to initiate a dynamic correction of the allowed number of obvious errors made by the operator (trainee) in a row when developing control algorithms from an external device in binary code (or using a human instructor (teacher), or using a special control device), through M (K ₁ -K _M ) inputs of the “Correction” of the device to the inputs 221 ₁ -221 _M of the requirements correction unit 22 t new, additionally introduced in the dynamics of operator training management, the number of explicit errors allowed.

The requirements correction unit 22 is described in the prototype and can be implemented in accordance with the circuit shown in FIG. 8. Dynamic correction of the number of allowed explicit errors allowed by the trainee in a row during the development of complex control algorithms is carried out in block 22, as a result, block 22 from its information outputs 222 ₁ -222 _M transmits in binary code the contents of the command characterizing the new number of allowed obvious errors to control inputs 234 ₁ -234 _M block 23 and through their correcting outputs 223 ₁ -223 _M block 22 to the correcting inputs 203 ₁ -203 _M register number 20. The operation of the register number 20 is described in detail in the prototype (see RF patent No. 2281560, G09B 9/00, 2006, b Yul. 22), it can be implemented in accordance with the circuit depicted in FIG. 7 and is responsible for comparing the initial and newly introduced permissible number of obvious errors, their recording and storage. As a result, in the memory cells of the storage element 20.2 of the register of the number 20, at any time after the device is started, it is (permanently) stored in binary code either a previously entered (recorded) admissible number of obvious errors (dynamic correction of the learning algorithm with explicit errors is not used), or new, introduced in the dynamics of operator training management, the number of explicit errors allowed (a corrected training algorithm involving explicit errors is involved).

From the control outputs 222 ₁ -222 _{M of the} block 22 to the control inputs 234 ₁ -234 _{M of the} block 23 (Fig. 9), the binary code contains the contents of the command characterizing the new number of allowed obvious errors (correction signal code). At the same time, through the information inputs 231 ₁ -231 _{M, the} corresponding control microoperation code from block 1 is received, the command correction unit 23 compares these codes (checks the didactic correspondence of the number of resolved obvious errors to the complexity level of the next control microoperation), and if they do not match, they identify this control microoperation as being corrected and transmits (overwrites) it through its outputs 23.1-3 ₁ -23.1-3 _M to the inputs 23.2-1 ₁ -23.2-1 _{M of the} register of the corrected microcommand 23.2 of block 23.

In this case, the corrected microcommand register 23.2 of block 23, implemented as a reverse shift register for shifting to the right (on JK-triggers in RS-flip-flops mode), dynamically corrects the next instructional micro-command - generates based on the data stored in the second-stage memory cells JK -triggers, the code of the new training micro-command (more complex or simpler), didactically corresponding to the new, introduced in the dynamics of the operator’s training control, the number of explicit errors allowed. The code of the new micro-command (micro-operation) of training is recorded in M memory cells of the first stage of the JK-triggers of the register of the corrected micro-command 23.2 (Fig. 9).

The contents of this corrected microoperation in binary code comes from the indicator outputs 23.2-2 ₁ -23.2-2 _{M of the} register of the corrected microcommands 23.2 through the indicator outputs 232 ₁ -232 _{M of} block 23 to the control inputs 241 ₁ -241 _M of analysis block 24 for identification and verification of boundary and emergency (catastrophic) states of the control object. At the same time, the contents of the corrected microoperation in binary code comes from the information outputs 233 ₁ -233 _{M of} block 23 to the information inputs 32 ₁ -32 _{M of the} main comparison unit 3.

If the codes match, when there is a didactic correspondence between the new number of resolved obvious errors and the level of complexity of the next control microoperation, the comparison element 23.1 of the command correction block 23 identifies this control microoperation as uncorrectable and reacts in the same way as in the absence of external dynamic control of the learning process (correction microcommands are not needed, only the number of explicit errors allowed has been changed and rewritten into the register of the number 20). In this case, the register of the corrected microcommand 23.2 of block 23 blocks its indicator outputs 23.2-2 ₁ -23.2-2 _M and from its information outputs 23.2-3 ₁ -23.2-3 _M , sends it in binary code through the information outputs 233 ₁ -233 _{M of} block 23 the contents of this (non-correctable) microoperation of the control to the information inputs 32 ₁ -32 _{M of the} main comparison unit 3. At the same time, as in the case with the absence of external dynamic control of the learning process, from the indicator outputs 1.3-1 ₁ -1.3-1 _M register of the microcommand 1.3 of the block 1 contents of the first (uncorrectable ) Through the micro-operation indicator outputs 011 ₁ -011 _M courses setting unit 1 is supplied to the control inputs 241 ₁ -241 _M analysis block 24 for identification and verification procedures and emergency boundary (catastrophic) states of the control object.

Thus, the information inputs 32 ₁ -32 _{M of the} main comparison unit 3 from the information outputs 233 ₁ -233 _M of the command correction block 23 receive in binary code the contents of the (unadjustable or correctable) control microoperation corresponding to the next stage of the learner's control algorithm. At the same time, either from the indicator outputs 011 ₁ -011 _M block 1 (non-correctable learning with obvious errors), or from the indicator outputs 232 ₁ -232 _M block 23 (dynamically corrected teaching with obvious errors), to control inputs 241 ₁ The -241 _M analysis block 24 receives the content in binary code and keeps track of the number of micro-commands (micro-operations) of control that are not clearly erroneous, but that predetermine a smooth drift of object parameters towards a boundary and catastrophic state. After the block 24 carries out identification and verification procedures for the boundary and emergency (catastrophic) states of the control object, the contents of the (non-correctable or correctable) micro-control operations from the control outputs 242 ₁ -242 _M of the analysis block 24 are transmitted in binary code to the indicator inputs 43 ₁ -43 _M display 4 and inputs 141 ₁ -141 _{M of} the display panel 14 in the interest of visualization information about the current operation of the control algorithm.

Thus, at the control inputs 241 ₁ -241 _M of the analysis unit 24, we have in binary code not only the content, but also the number of micro-commands (microoperations) of the control, which are not clearly erroneous, but that predetermine the smooth drift of the object's parameters towards a boundary and catastrophic state.

Dynamic control of the value of the allowable number of such microcommands (microoperations) of control, when it is exceeded, the control object is likely to go into an emergency (catastrophic) state from any other state, identification and verification of boundary and emergency (catastrophic) states of the object, as well as the formation of logical zero signals or logical unit (prediction and warning signal), characterizing respectively the absence or presence of a possible catastrophic state control object is implemented within the analysis unit 24 and control unit 25 as follows.

The control unit 25 (Fig. 3) is designed to form a control code sequence (consisting of elements of the set N _M (see expression (1), where N _m is the permissible (threshold, maximum), an _m is the real one for each mth state value of the number of microinstructions (microoperations) of control that predetermine a smooth drift of the parameters of this object towards disaster), exceeding which the control object is likely to go into an emergency (catastrophic) state from any other state, and to generate a logical zero signal or logical unit, which respectively characterize the prohibition or permission of the trainee (user, operator) to issue a warning signal about the presence of a possible catastrophic state of the control object.The control unit 25 consists of a test RAM 25.0, a counter 25.1 and can be implemented according to the scheme, shown in Fig. 3. The formation of the control code sequence of valid values for the number of micro-commands (microoperations) control, predetermining a smooth drift of steam etrov object side crash, and forming logic zero or logic one signal is produced as follows. From an external source, through the input “Control input” of the device, control input 251 of the control unit 25 and control input 25.0-1 in the memory cells of the test RAM 25.0, the set of admissible (threshold) values is sequentially written in binary code to the number of not clearly erroneous, but threatening disaster in subsequently, micro-commands (micro-operations) of control, as well as recording a logical zero or logical unit, characterizing respectively the prohibition or permission to issue a warning signal about the presence of a possible catastrophic th state of the control object.

Counts of steps (cycles) within the training cycle, in other words, the steps of checking (controlling) the correspondence of the permissible values of the number of micro-commands (micro-operations) of control, which determine the smooth drift of the object parameters towards the catastrophe, their real number per training cycle, come from the output of 212 delay elements 21, being, by physical nature, signals about the presence (signals "error") or the absence in the actions of the operator of an obvious error. They come from the second output 34 of the main unit of comparison 3 through the element And 5 to the counting input "Set. “1” of the start counter 6 (increasing its content by one), as well as through the delay element 21, are sent to the control input 201 of the register 20, to the information inputs 82 ₁ -82 _{M of the} block of starting elements And 8 and to the clock inputs 243 and 253 of the block analysis 24 and the control unit 25, respectively, being the measures (steps) of the reference within the training cycle. These signals (samples) are received through the clock input 253 of the control unit 25 to the clock input 25.1-1 of the counter 25.1 and determine, from the clock output 25.1-3 of the counter 25.1 to the clock input 25.0-3 of the test RAM 25.0, the moment of the start of sequential reading in binary code stored in the test RAM 25.0 N _M - a set of permissible (threshold) values for any m-th state of the number of control micro-commands (micro-operations) that are not obviously erroneous, but that predetermine a smooth drift of the object parameters in the direction of emergency (catastrophic) with condition. Sequential reading is carried out through the test output 25.0-4 of the test RAM 25.0 and the output 252 of the control unit 25 to the test input 24.2-2 of the ROM 24.2 of the analysis unit 24 (Fig. 2), and also determines the start of the reading of logical zero or logic stored in the test RAM 25.0 units. Reading a logical zero or logical unit is also performed from the test output 25.0-4 of the test RAM 25.0 and the output 252 of the control unit 25 to the second input 24.7-2 of the AND element 24.7 of the analysis unit 24 (Fig. 2). From the reset output 25.0-2 of the test RAM 25.0 (Fig. 3) to the reset input 25.1-2 of the counter 25.1 at the time of reading the sequence of admissible (threshold) values of the number of microcommands (microoperations) of control that are not clearly erroneous, and reading the logical zero (logical unit) ) receives a signal, resets the counter 25.1 and 25.1 meter giving a command to start a new countdown to the newly introduced control actions (N _M - sequences acceptable (threshold) for any m-th values of the state quantities md instructions (micro-operations) management, it is not manifestly erroneous, but predetermine smooth process parameters to drift toward disaster (catastrophic) state, and the newly introduced control actions - a logic zero (logical unit).

The analysis unit 24 is designed to carry out identification and verification procedures for the boundary and emergency (catastrophic) states of the control object with smooth changes in the parameters of the control actions taken by the student, as well as to generate logical zero or logical unit signals (prediction and warning signals) characterizing, respectively, the absence or the presence of a possible catastrophic state of the object. Analysis unit 24 may be implemented according to the circuit shown in FIG. 2. The identification and verification of the boundary and emergency (catastrophic) states of the control object during smooth changes in the parameters of the control actions taken by the student, as well as the generation of logical zero or logical unit signals (prediction and warning signals) are carried out in block 24 as follows.

From indicator outputs 011 ₁ -011 _M block 1 (non-correctable learning with obvious errors), or from indicator outputs 232 ₁ -232 _M block 23 (dynamically corrected learning with obvious errors) via control inputs 241 ₁ -241 _M of analysis block 24 on the M control inputs 24.0-1 ₁ -24.0-1 _{M of the} central RAM 24.0 are received in binary code and signals are recorded in the memory cells that characterize at the (k + 1) -th step of the learning cycle both the content and the number of microcommands (microoperations) of control which are not clearly erroneous, but predetermining smooth drift toward the object parameters and boundary catastrophic condition (see. Fig. 2).

From the second output 34 of the main comparison unit 3 through the delay element 21, through the clock input 243 of the block 24, the clock signal is received to the clock input 24.2-1 of the ROM 24.0 and to the clock input 24.2-1 of the ROM 24.2, initiating an obvious error, initiating sequential reading from the memory cells of the central RAM 24.0 of each n of N values of the number of micro-commands (microoperations) of control that are not clearly erroneous, but that predetermine a smooth drift of the object parameters towards the boundary and catastrophic state at the (k + 1) -th step o teaching, namely those corresponding to the set (1) and have physical significance threshold is exceeded the system capacity in terms of reliability and stability and, as a result, a high probability of transition to the emergency control object (The catastrophic) state.

The values of the number n of the total number N of microinstructions (microoperations) of control, which are not clearly erroneous, but that predetermine a smooth drift of the object parameters towards the boundary and catastrophic state at the (k + 1) -th training step (for each m-th state, the number n _m from the total number N _m microcommands) are sequentially read from each m-th of the executive outputs 24.0-4 ₁ -24.0-4 _{M of the} central RAM 24.0 to the inputs of the corresponding m-th executive RAM 24.1 ₁ -24.1 m, as well as to the first input 24.3-1 elements of iterative comparison 24.3 and on in the second input 24.4-2 of the comparison element 24.4. From the output of each m-th from the executive RAM 24.1 ₁ -24.1 _M to the second input 24.3-2 of the iterative comparison element 24.3 in binary code, the values of the number n stored in the memory cells from the total number N of microcontrols (microoperations) of control, which are not clearly erroneous, are sequentially read , but predetermining the smooth drift of the object’s parameters towards a boundary and catastrophic state (for each m-th state - the number n _m of the total number N _m microcommands) at the k-th (previous) learning step. In addition, the clock signal from the clock input 243 of block 24 to the clock input 24.2-1 of the ROM 24.2 initiates the reading in binary code from the memory cells of the ROM 24.2 to the first input 24.4-1 of the comparison element 24.4 of the previously recorded allowable value of the number of microcommands (microoperations) control for any m-th state, above which, in accordance with expression (2), the object is likely to go into emergency (catastrophic) state from any other state. Based on the comparison element 24.4, the procedure for identifying the boundary and emergency (catastrophic) states of the control object is carried out. This procedure is carried out by sequential (step-by-step) a priori estimation and comparison of the values of the number of each n of the total number N of micro-commands (micro-operations) of control, which are not clearly erroneous, but that predetermine a smooth drift of the object's parameters towards the boundary and catastrophic state (for each m-th state - values of the number n _m of the total number n _m of microinstructions included in the plurality of n _M (1)) on the (k + 1) th learning step, to determine the presence or absence of each possible state above tions these values n _m N _m permissible threshold according to expression (2).

Thus, the comparison element 24.4 performs step-by-step (step-by-step) comparison of sequentially arriving in binary code from the executive outputs 24.0-4 ₁ -24.0-4 _{M of the} central RAM 24.0 values of each n _m (k + 1), with the value of N _m received from the output ROM 24.2. The non-exceeding by any m-th (n _m (k + 1)) value of this threshold N _m characterizes the non-fulfillment of condition (4) and the result of the identification (comparison) procedure is expressed in the appearance at the output of the comparison element 24.4 of a logical zero, which is in binary code arrives at the first input 24.7-1 element And 24.7. Exceeding by any m-m (n _m (k + 1)) value of this threshold N _m characterizes the fulfillment of condition (4) and the beginning of a smooth change in the parameters of the object under the influence of the control actions implemented by the learner - a smooth change in the critical, threatening side of the number of microcommands (microoperations ) controls that are not clearly erroneous (for each mth state), and the result of the identification (comparison) procedure is expressed in the appearance of a logical unit at the output of the comparison element 24.4, which in binary code goes to the first input 24.7-1 ele cient and 24.7.

Based on the iterative comparison element 24.3, the intermediate RAM 24.5 and the intermediate element I 24.6, the verification procedure of the boundary and emergency (catastrophic) states of the control object is carried out. This procedure is carried out in two stages. The first stage is carried out on the basis of the iterative comparison element 24.3 by sequential step-by-step (beat) a priori estimation and comparison of each m-th value of the quantity n _m at this k-th learning step with the value of the quantity n _m at the next (k + 1) -th step in in accordance with the expression (3). To this end, in the iterative comparison element 24.3, a step-by-step comparison of sequentially and in pairs arriving in binary code from the outputs of M executive RAMs 24.1 ₁ -24.1 _{M of} each of the values n _m (k) of the number of micro-commands (microoperations) of control at this kth step is carried out with the corresponding the values of n _m (k + 1) of the number of micro-commands (microoperations) of control at the next (k + 1) -th step, coming from the executive outputs 24.0-4 ₁ -24.0-4 _{M of the} central RAM 24.0. Not exceeding by any m-th (n _m (k + 1)) of the values of the number of micro-commands (micro-operations) of the control that are not clearly erroneous at the (k + 1) -th step of the corresponding m-th (n _m (k)) of the values the number of microcommands (microoperations) of the control that are not clearly erroneous at the kth (previous) step is characterized by the non-fulfillment of condition (5) and the result of the first stage of the verification procedure (comparing the subsequent value with the previous one) is expressed in the appearance of an iterative comparison element 24.3 logical zero, which in binary code is input 24.5 g of the intermediate memory and the second input of AND 24.6-2 intermediate 24.6. Exceeding by any m-th (n _m (k + 1)) from the values of the number of microcommands (micro-operations) of the control that are not clearly erroneous at the (k + 1) -th step of the corresponding m-th (n _m (k)) from the values of the number microcommands (microoperations) of control, which are not clearly erroneous at the kth (previous) step, characterizes the fulfillment of condition (5). the physical meaning of the identified trend of increasing the probability of changing the object’s parameters under the influence of the control actions implemented by the learner towards the boundary and emergency (catastrophic) state, and the result of the first stage of the verification procedure (comparing the next value with the previous one) is expressed in the appearance of an iterative comparison element 24.3 logical units , which in binary code is fed to the input of the intermediate RAM 24.5 and to the second input 24.6-2 of the intermediate element And 24.6.

The second stage of the verification procedure in block 24 is carried out on the basis of the intermediate RAM 24.5 and the intermediate element And 24.6 by comparing in the intermediate element And 24.6 the result of the first stage obtained at the k-th step (logical zero or logical unit) stored in the intermediate RAM 24.5 and transmitted to the first input 24.6-1 of the intermediate element And 24.6, with the result of the first stage (logical zero or logical unit) obtained at the (k + 1) -th learning step and coming from the output of the iterative comparison element 24.3 to the second input 24.6-2 And the exact item 24.6. The physical meaning of the second stage of verification is to confirm (in fact, verification) the identified tendency to increase the probability of changes in the parameters of the object under the influence of the control actions implemented by the student towards the boundary and emergency (catastrophic) state of this object, and the result of the second stage of verification is expressed in the appearance of an intermediate element And 24.6 logical units or logical zero, which in binary code are supplied to the first input 24.7-1 of the AND element 24.7. If the result of the first stage (for example, a logical unit) obtained at the k-th step coincides with the result of the first stage (a logical unit) obtained at the (k + 1) -th step, the result of the second stage of the verification procedure is expressed in the appearance of an intermediate element And 24.6 logical units. If the result of the first stage obtained at the kth step (for example, a logical unit) does not coincide with the result of the first stage (a logical unit) obtained at the (k + 1) th step, or the result of the first stage obtained at the kth step is logical zero and coincides with the result of the first stage (logical zero) obtained at the (k + 1) th step, the result of the second stage of the verification procedure is expressed in the appearance of a logical zero at the output of the intermediate element AND 24.6.

The clock signal supplied to the clock input 253 of the control unit 25. initiates the reading from the test output 252 of the control unit 25 through the test input 244 of the analysis unit 24 to the second input 24.7-2 of the AND element 24.7 of a logical zero or logical unit, characterizing respectively the prohibition or permission of the operator ( learner, user) to issue a warning signal about the presence of a possible catastrophic state of the control object.

If a logical unit is received from the test input 244 of block 24 to the second input 24.7-2 of the And 24.7 element (notification of a possible catastrophic state is necessary) and the logical unit is received from the output of the comparison element 24.4 or from the output of the intermediate And 24.6 element, the result of identification and verification of the boundary and emergency (catastrophic) states of the control object is expressed in the appearance at the output of the AND element 24.7 logical units. The logical unit from the output of the element And 24.7 goes to the read input 24.0-5 of the central RAM 24.0 and locks the central RAM 24.0. not allowing the identified and verified signals characterizing both the content and the number of control micro-commands (microoperations) to be read from the control outputs 24.0-2 ₁ -24.0-2 _{M of the} central RAM 24.0 through the control outputs 242 ₁ -242 _M of the analysis unit 24 (see. Fig. 1) to the indicator inputs 43 ₁ -43 _M scoreboard 4 and to the inputs 141 ₁ -141 _{M of} the display panel 14 in the interest of visualization for the learner information about the current operation of the control algorithm.

In addition, the logical unit from the output of the And 24.7 element through the warning output 245 of block 24 is sent to the “Threat” output of the device, being a prediction and warning signal characterizing the presence of a possible catastrophic state of the control object and urging the student (user, operator) to make an external correction to the number of microcommands (microoperations) of the control, which are not clearly erroneous, but that predetermine a smooth drift of the object's parameters towards a boundary and catastrophic state (for example er, introduce a temporary prohibition or forced restriction on the number of these commands) or threshold, acceptable values for the number of such micro-commands (micro-operations) of control in order to prevent an emergency (catastrophic) abrupt change in the state of the control object with small disturbances caused by the actions of the student [2].

If a logical zero is received from the test input 244 of block 24 (see Fig. 2) to the second input 24.7-2 of the And 24.7 element (the student does not need to be notified of a possible catastrophic state), but from the output of the comparison element 24.4 or from the output of the intermediate And element 24.6, either a logical zero or a logical unit is obtained, the result of the identification and verification of the boundary and emergency (catastrophic) states of the control object is expressed in the appearance of a logical zero on the output of AND 24.7. If a logical unit is received from the test input 244 of block 24 to the second input 24.7-2 of the And 24.7 element (notification of a possible catastrophic state is necessary), and a logical zero is received from the output of the comparison element 24.4 or from the output of the intermediate element And 24.6, the result of identification and verification of the boundary and emergency (catastrophic) states of an object is expressed in the appearance of a logical zero on the output of AND element 24.7. Logical zero from the output of the AND 24.7 element goes to the readout input 24.0-5 of the central RAM 24.0 and opens the central RAM 24.0, allowing identified and verified signals characterizing both the content and the number of micro-commands (microoperations) of control, which are not clearly erroneous, but that determine smooth drift of object parameters towards a boundary and catastrophic state, read from the control outputs 24.0-2 ₁ -24.0-2 _{M of the} central RAM 24.0 through the control outputs 242 ₁ -242 _M of the analysis unit 24 (see Fig. 1) to the indicator The inputs are 43 ₁ -43 _M scoreboards 4 and to the inputs 141 ₁ -141 _{M of} the display panel 14 in the interest of visualization for the learner of information about the current operation of the control algorithm.

In addition, the logical zero from the output of the element And 24.7 through the warning output 245 of block 24 goes to the output “Threat” of the device, being a prediction and warning signal characterizing the absence of a possible catastrophic state of the control object. Thus, the presence of a logical unit signal at the warning output 245 of the analysis unit 24 and at the output “Threat” of the device serves as an indicator of blocking the device, and the presence of a logical zero signal at the warning output 245 of block 24 and at the output of “Threat” serves as an indicator of unlocking the device for training operators generally.

Identified and verified signals characterizing the content and number of microcommands (microoperations) of control, through the control outputs 242 ₁ -242 _M of the analysis unit 24 (see Fig. 1) are supplied to the indicator inputs 43 ₁ -43 _{M of the} display 4 and to the inputs 141 ₁ - 141 _{M of} the display panel 14, notifying the operator and visualizing in his interests information about the current operation of the control algorithm.

The operator (trainee), perceiving this information, takes into account that the identification and verification of the boundary and emergency (catastrophic) states of the object within the framework of the current operation of the control algorithm is carried out, it takes the next control action by typing the control action code on the keyboard of the response unit of operator 2, thereby forming a management decision.

The control action code from the M outputs 021 ₁ -021 _M of the response block of the operator 2 is supplied to the response inputs 31 ₁ -31 _{M of the} main comparison unit 3. At the same time, the content of the next one comes in binary code to the information inputs 32 ₁ -32 _{M of the} main comparison unit 3 non-correctable or correctable) microoperations issued from the information outputs 233 ₁ -233 _M of the command correction block 23.

In the main block of comparison 3, the error-freeness of the control action generated by the operator is evaluated by comparing the codes of the involved and the required control action, which is sent to block 3 via information inputs 32 ₁ -32 _M as part of the next (non-correctable or correctable) microoperation from the corrected micro-command register 23.2 of block 23. If the codes match, the operation is considered to be performed by the student without obvious errors and the binary signal “no error” appears on the first output 33 of block 3, otherwise learning, i.e. with a clear error in the operator’s actions, the comparison of the received codes does not occur, and the “error” signal is recorded on the second output 34 of the main comparison unit 3.

The signal “no error” from the first output 33 of the main block of comparison 3 is fed to the second input 72 of the start element OR 7 and through the second control input 014 of the unit for setting the training program 1 to the second input 1.1-2 of the micro-command 1.1 address register.

At the same time, in the address register of the microcommand 1.1 of the task block of the training program 1, there is a shift to the next cell of the register, where the code of the address of the microcommand corresponding to the next operation of the control algorithm is recorded, and the device’s operation cycle is repeated in the order described above.

If the operator (trainee) completes the entire control algorithm without obvious errors, from the control output 1.1-4 of the micro command address register 1.1 through the control output 015 of the instruction block 1 of the training program 1, the signal “no error” is sent to the information inputs 102 ₁ -102 _{M of the} block in binary code polling elements And 10, which can be implemented in accordance with the scheme proposed in FIG. 6. The signal “no error”, arriving at the information inputs 102 ₁ -102 _M block of polling elements And 10, initiates the transfer from its outputs 103 ₁ -103 _{M of the} contents of the main counter 11 (ie, “1” - units), inputs 122 ₁ -122 _{M of the} decoder 12. The initial signal "1" (unit) from the outputs 121 ₁ -121 _{M of the} decoder 12 in decimal code is supplied through the information inputs 44 ₁ -44 _{M of the} scoreboard 4 to the inputs 171 ₁ -171 _{M of} the training number indicator 17 for display to the operator.

In addition, if the operator completes the entire control algorithm without obvious errors, the signal “no error” in binary code also goes to the reset input 94 of trigger 9 from the control output 015 of the training program 1 block, initiating the appearance of the signal “no error” at its inverse output 92. This signal “no error” in binary code is supplied through the second control input 42 of the panel 4 to the input 161 of the banner “Training” 16, illuminating this banner. This signals that the student is being transferred from the Exercise mode to the Training mode.

If the operator (trainee) makes a clear error in the next operation, the error signal in binary code appears on the second output 34 of the main comparison unit 3. This signal is fed to the second input 132 of the main element OR 13 and further, from its output 133 to counting input "Set “1” of the main counter 11, adding one more unit to its contents. In addition, this signal from the output 133 of the main element OR 13 is supplied through the first control input 013 to the first input 1.1-1 of the address register of the micro command 1.1 of the task block of the training program 1, returning the student in the new training to the first operation of the algorithm. At the same time, the Exercise banner 15 remains illuminated, thereby signaling to the operator that he has not been transferred to a new training mode. The process continues until the student completes the entire control algorithm without obvious errors and the signal “no error” appears on the control output 1.1-4 of the micro command address register 1.1 and on the control output 015 of block 1, arriving at the reset input 94 of trigger 9 and initiating exposure of the “Training” banner 16.

If the student in his subsequent activities (that is, already in the "Training" mode) makes obvious mistakes, it means that he was transferred from the "Exercise" mode to the "Training" mode prematurely or accidentally, and the key criterion for the preparedness of the operator can be the number obvious mistakes made in a row. In any case - if the operator didn’t make or commit an obvious error, the signal about the presence (signal “error”) or the absence of an obvious error from the second output 34 of the main comparison unit 3 through element And 5 is fed to the counting input “Set. "1" start counter 6, increasing its contents by one. The same signal about the presence (signal "error") or the absence of an obvious error from the second output 34 of the main comparison unit 3 through the delay element 21 is fed to the clock inputs 243 and 253 of the analysis unit 24 and the control unit 25, respectively (being clock cycles (steps) of within the learning cycle), to the control input 201 of the register of the number 20 and to the information inputs 82 ₁ -82 _{M of the} block of starting elements AND 8, which can be implemented in accordance with the circuit proposed in FIG. 5.

The error signal is generated (initiated) at the outputs 83 ₁ -83 _{M of the} block of start elements AND 8 when the contents of the start counter 6 are increased by one and goes to the information inputs 191 ₁ -191 _{M of the} response block 19, in which the number of allowed and clear errors resolved in a row.

If the number of allowed and the number of currently allowed (uncorrelated or corrected number recorded and stored in the register number 20) obvious errors do not match (there are fewer obvious errors), and there is a logical output on the warning output 245 of block 24 and on the output “Threat” of the device zero, which is the result of identification and verification - a prediction and warning signal, characterizing the absence of a possible catastrophic state of the control object, the learning cycle continues in In accordance with the previously described procedure, except that if, after an obvious error, the next action is performed by the operator correctly, then the signal from the first output 33 of the main comparison unit 3 through the start element OR 7 will reset the contents of the start counter 6. This signal about the absence of an obvious error is an analogue of the signal arriving (along with the error signal) from the second output 34 of the main comparison unit 3. Thus, along with the introduced identification and verification procedures, the procedures laid down in the prototype are also implemented - the number of obvious mistakes made by the operator in a row both during the development of skills, taking into account the dynamics of the functioning of the control object (dynamics of changing threshold values of the state of the automated control system) - with correction, and during the development of skills by the student without A set of these factors is without correction.

If the number of obvious errors made and resolved at the moment in a row (uncorrected or corrected number recorded and stored in the register of the number 20) coincides, and at the warning output 245 of block 24 and at the output “Threat” of the device there is a logical zero, which is the result of identification and verification - a prediction and warning signal characterizing the absence of a possible catastrophic state of the control object, then the binary signal “error” from output 193 of the response comparison unit 19 sends through the installation element OR 18 to the installation input 93 of the trigger 9. The trigger 9 transmits this signal in binary code from its direct output 91, through the first control input 41 of the display 4 to the input 151 of the banner “Exercise”, initiating the exposure of this banner and returning, by the learner to the "Exercise" mode.

If the number of errors made and the number of currently allowed ones (uncorrected or adjusted number, recorded and stored in the register of number 20) does not coincide with obvious errors (there are no obvious errors or few), or it coincides (there are many obvious errors), but at warning output 245 of block 24 and at the output “Threat” of the device there is a logical unit, this is an indicator of the device’s blocking, a prediction and warning signal characterizing the presence of a possible catastrophic state of the control object and is required from a learner (user, operator) performing external correction of the required number of control micro-commands (micro-operations) that are not clearly erroneous, but that predetermine a smooth drift of the object parameters towards a boundary and catastrophic state, in order to prevent an emergency (catastrophic) jump-like change in the state of the control object when small disturbances caused by the actions of the student [2].

As a result, as part of monitoring the learning outcomes and reinforcing operator skills, at each stage of the training control algorithm, in addition to the binary signal “no error” at the first 33 output of the main comparison unit 3, or the “error” signal recorded in binary code, the output 193 is comparison block 19, characterizing the assessment of the correctness (without obvious errors) of the learner’s actions, we have at the warning output 245 of block 24 and at the output “Threat” of the device in binary code a logical zero or logical unit, obtained on the basis of identifier fication and verifying the states of the control object using the methods and catastrophe theory describing respectively the absence or presence of the trainee actions induced smooth drift of the parameters of the object to the side of the boundary and catastrophic condition.

An analysis of the principle of operation of the inventive device for training operators shows the obviousness of the fact that, along with the saved capabilities for analyzing operator actions based on the dynamically adjusted number of resolved obvious errors made by the learner, the device is able to implement the learning algorithm in the event of boundary and emergency (catastrophic) states of the object control, with smooth changes in the parameters of this object under the influence of control actions taken by the learner (microcommands (microoperations)), which, by their nature, are not erroneous, but provide a high probability of the transition of the control object to an emergency (catastrophic) state from any other state. In addition, the claimed device is able to notify (warn) the learner (user, operator) of the control object about its possible emergency condition based on identification and verification data.

This device provides an increase in the degree of adequacy of the situations studied, an increase in the level of reliability of the environment and learning conditions, when in the dynamics of training the number of input micro-commands (micro-operations) of control can smoothly change under the influence of the control actions taken by the student, creating a potential threat of blocking (collapse) of the control object. This significantly expands the scope of the device, expands the functionality of the training equipment, where the claimed device for training operators will be used.

INFORMATION SOURCES

1. Arnold V.I. Catastrophe theory. - M .: Nauka, 1990 .-- 128 s;

2. Poston T., Stuart I. The theory of disasters and its applications. Per. from English - M .: Mir, 1980 .-- 608 s;

3. Petrov Yu.P., Petrov L.Yu. Unexpected in mathematics and its connection with accidents and catastrophes of recent years. - SPb .: NIIH SPbSU, 1999. - 108 s;

4. Parashchuk IB, Dyakov SV. Mathematics of catastrophe theory as applied to problems of analyzing the reliability of communication network elements. / Communication systems. Analysis. Synthesis. Control. / Ed. prof. Postyushkova V.P. Issue 5. - St. Petersburg: Publishing House "Theme", 2001. - 84 p., S. 47-49;

5. Paraschuk I.B., Dyakov S.V. Prospects for assessing the stability of telecommunication networks using disaster theory methods. // 56th scientific and technical conference dedicated to Radio Day. Conference proceedings. - SPb .: SPbGETU "LETI", 2001, S. 56-57.

Claims (3)

1. A device for training operators, containing a block for setting a training program (1), a block for operator response (2), start (7), main (13) and installation (18) OR elements, delay element (21), main (3 ) and response (19) comparison blocks, blocks of start (8) and interrogation (10) elements AND, number register (20), start (6) and main (11) counters, decoder (12), trigger (9), element And (5), a requirements correction block (22), a command correction block (23) and a scoreboard (4), M≥2 information inputs (44 ₁ -44 _M ) of which are connected to the corresponding M outputs (121 ₁ -121 _M ) of the decoder (one 2), M inputs (122 ₁ -122 _M ) of which are connected to the corresponding M outputs (103 ₁ -103 _M ) of the block of polling elements AND (10), M counting inputs (101 ₁ -101 _M ) of which are connected to the corresponding M outputs ( 111 ₁ -111 _M ) of the main counter (11), installation input “Set. "0" of which is connected to the first input (71) of the OR start element (7), the second input (182) of the OR installation element (18), the first input (131) of the main OR element (13) and is the "Start" device input, output (133) of the main element OR (13) is connected to the counting input “Set. “1” of the main counter (11) and the first control input (013) of the unit for setting the training program (1), the first control input (41) of the board (4) is connected to the direct output (91) of the trigger (9), inverse output (92) which is connected to the first input (51) of the AND element (5) and the second control input (42) of the display panel (4), the first output (33) of the main comparison unit (3) is connected to the second input (72) of the starting element OR (7) and the second control input (014) of the training program task unit (1), the second output (34) of the main comparison unit (3) is connected to the second input (132) of the main OR element (1) 3), the input (211) of the delay element (21) and the second input (52) of the AND element (5), the output (53) of which is connected to the counting input “Set. “1” of the start counter (6), installation input “Set. "0" of which is connected to the output (73) of the start element OR (7), M counting inputs (81 ₁ -81 _M ) of the block of start elements AND (8) are connected to the corresponding M outputs (61 ₁ -61 _M ) of the start counter (6 ), M outputs (83 ₁ -83 _M ) of the block of starting elements AND (8) are connected to the corresponding M information inputs (19 ₁ -191 _M ) of the response comparison unit (19), M of the response inputs (192 ₁ -192 _M ) of which are connected with the corresponding M outputs (202 ₁ -202 _M ) of the number register (20), the output (193) of the response comparison unit (19) is connected to the first input (181) of the OR installation element (18), the output (183) of which connected to the installation input (93) of the trigger (9), the reset input (94) of which is connected to the control output (015) of the unit for setting the training program (1) and to M information inputs (102 ₁ -102 _M ) of the block of interrogating elements And ( 10), M outputs (021 ₁ -021 _M ) of the operator response block (2) are connected to the corresponding M response inputs (31 ₁ -31 _M ) of the main comparison block (3), M information outputs (233 ₁ -233 _M ) of the block correction commands (23) are connected to respective data inputs of M (32 ₁ -32 _M) of the main comparator unit (3), M data inputs (231 ₁ -231 _M) blo and correction commands (23) are connected to the respective M outputs information (012 ₁ -012 _M) courses setting unit (1), M control inputs (234 ₁ -234 _M) command correction unit (23) connected to the respective M outputs of the control ( 222 ₁ -222 _M ) of the requirements correction block (22), M correction inputs (203 ₁ -203 _M ) of the number register (20) are connected to the corresponding M correction outputs (223 ₁ -223 _M ) of the requirements correction block (22), M inputs (221 ₁ -221 _M ) which are the corresponding M inputs (K ₁ -K _M ) "Correction" of the device, the first control input (41) (4) connected to the input (151) of the Exercise banner (15), the second control input (42) of the scoreboard (4) is connected to the input of the Training banner (16), and M information inputs (44 ₁ -44 _M ) of the scoreboard (4) connected to the corresponding M inputs (171 ₁ -171 _M ) of the training number indicator (17), characterized in that an analysis unit (24) and a control unit (25) are additionally introduced, while the output (212) of the delay element (21 ) is connected to the control input (201) of the number register (20), with M information inputs (82 ₁ -82 _M ) of the block of start elements AND (8), with the clock input (253) of the control unit (25) and the clock the input input (243) of the analysis unit (24), the test input (244) of which is connected to the output (252) of the control unit (25), the control input (251) of which is the input “Control input” of the device, M indicator outputs (011 ₁ - 011 _M ) of the instruction block of the training program (1) are connected to the corresponding M indicator outputs (232 ₁ -232 _M ) of the command correction block (23) and connected to the corresponding M control inputs (241 ₁ -241 _M ) of the analysis block (24), M control outputs (242 ₁ -242 _M) are connected to respective M inputs of an indicator (43 ₁ -43 _M) board (4) which are connected to a Resp M inputs (141 ₁ -141 _M) indicating panel (14), and a warning output (245) of the analysis block (24) is an output "danger" device. 2. A device for training operators according to claim 1, characterized in that the analysis unit (24) consists of a central random access memory (RAM) (24.0), M executive RAM (24.1 ₁ -24.1 _M ), read-only memory (ROM) (24.2), an iterative comparison element (24.3), a comparison element (24.4), an intermediate RAM (24.5), an intermediate element And (24.6) and an element And (24.7), while M control inputs (24.0-1 ₁ -24.0-1 _M) of the central memory (24.0) are the respective control inputs of M (241 ₁ -241 _M) analysis unit (24), M control outputs (24.0-2 ₁ -24.0-2 _M) Price eral RAM (24.0) are the respective M control outputs (242 ₁ -242 _M) analysis unit (24), a clock input (24.0-3) of the central memory (24.0) is connected to the clock input (24.2-1), ROM (24.2) and is the clock input (243) of the analysis unit (24), M executive outputs (24.0-4 ₁ -24.0-4 _M ) of the central RAM (24) are connected to the inputs M of the corresponding executive RAM (24.1 ₁ -24.1 _M ), the inputs of the M executive RAM ( 24.1 ₁ -24.1 _M ) are combined and connected to the first input (24.3-1) of the iterative comparison element (24.3) and the second input (24.4-2) of the comparison element (24.4), the outputs of M executive RAM (24.1 ₁ -24.1 _M ) are combined and connected to the second input (24.3-2) of the iterative comparison element (24.3), the ROM output (24.2) is connected to the first input (24.4-1) of the comparison element (24.4), the output of the iterative comparison element (24.3) connected to the input of the intermediate RAM (24.5) and the second input (24.6-2) of the intermediate element And (24.6), the first input (24.6-1) of which is connected to the output of the intermediate RAM (24.5), the output of the intermediate element And (24.6) is connected to the output the comparison element (24.4) and the first input (24.7-1) of the AND element (24.7), the second input of which (24.7-2) is connected to the test input (24.2-2) П At (24.2) it is the test input (244) of the analysis unit (24), the output of the AND element (24.7) is connected to the read input (24.0-5) of the central RAM (24.0) and is a warning output (245) of the analysis unit (24) and output "Threat" of the device. 3. A device for training operators according to claim 1, characterized in that the control unit (25) consists of a test RAM (25.0) and a counter (25.1), while the clock output (25.1-3) of the counter (25.1) is connected to the clock input (25.0-3) test RAM (25.0), the reset output (25.0-2) of which is connected to the reset input (25.1-2) of the counter (25.1), the clock input (25.1-1) of which is the clock input (253) of the control unit ( 25), the test output (25.0-4) of the test RAM (25.0) is the output (252) of the control unit (25), the control input (25.0-1) of the test RAM (25.0) is the control input ( 251) of the control unit (25) and the input "Control input" of the device.

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