RU2610836C1 - Multichannel code division receiver for receiving of quadrature-modulated high structural concealment signals - Google Patents

Abstract

FIELD: wireless communications.

SUBSTANCE: invention relates to radio communication field and can be used in wireless access systems, land mobile and satellite communication, intended for operation under conditions of electronic warfare. Multichannel code division receiver for receiving of quadrature-modulated high structural concealment signals includes, in particular, first, second and third switching devices, as well as masking orthogonal code sequence generator, channel orthogonal code sequences generator, repeated signal detection device, insulation element and corresponding connections between them to provide reliable reception of quadrature-modulated signals, which signal-code structure varies during communication system operation, and repeated signal detection in case of system timing failure.

EFFECT: technical result is provision of reliable reception of signals with high structural security in advanced communication systems under conditions of their long-term operation.

1 cl, 3 dwg

Description

The invention relates to the field of radio communications and can be used in wireless access systems, land mobile and satellite communications, in radio control systems and other systems designed to function in electronic warfare.

One of the main requirements for promising communication systems is the requirement to use signals with high structural secrecy in them, which makes it difficult for the opposing side to create effective interference (interference similar to a signal) to suppress these systems, as well as protect these communication systems from extraneous interventions to intercept information or impose false information.

One of the promising directions for increasing the structural secrecy of signals is the use of non-linear code sequences from an ensemble of complete code rings for their formation.

Known devices that generate quadrature-modulated signals with increased structural secrecy [1], as well as devices that provide reliable reception of such signals [2].

However, with the long-term operation of these communication systems, the capabilities of third parties to disclose the structure of the signals intercepted by them increase significantly due to an increase in the monitoring time of the systems, on the one hand, and an increase in the computing power of systems for processing intercepted information, on the other.

Known devices that generate quadrature modulated signals, the signal-code design of which changes during operation [3]. However, there are no devices that can provide such signals.

Known devices that provide reliable reception of quadrature modulated signals of increased structural secrecy [2], but they have the following disadvantages:

there is no possibility to receive quadrature-modulated signals whose signal-code design changes during operation;

there is no possibility of re-detection of a signal in case of failure of synchronization.

Closest to the proposed invention is a device [2] (prototype), which includes K channels for information extraction, where K takes values from 1 to N-1, and N = 2 ⁿ for n≥1, one of which is allocated for synchronization a receiver, wherein each information isolation channel includes a first quadrature correlator of an information extraction channel connected in series, a first integrator and a first comparator, and a second quadrature correlator of an information extraction channel connected in series, a second integrator and the second comparator, the first inputs of the first and second quadrature correlators of the information extraction channel are combined and are the first input of the k-th information extraction channel, where k takes values from 1 to K, the second inputs of the first and second quadrature correlators of the information extraction channel are combined and are the second input k -th channel of information extraction, the output of the first comparator is connected to the first input of the decoder and is the first and ninth outputs of the information extraction channel, the output of the second comparator is connected to the second input ohm of the decoder is the second and tenth outputs of the information extraction channel, the first output of the decoder is the third output of the information extraction channel, the second output of the decoder is the fourth output of the information extraction channel, the output of the first quadrature correlator of the information extraction channel is the fifth output of the information extraction channel, the output of the second quadrature correlator the information extraction channel is the sixth output of the information extraction channel, the second inputs of the first and second integrator and the third deco input the dera are combined and are the seventh input of the information extraction channel, the fourth input of the decoder is the sixth input of the information extraction channel, the output of the first adder modulo two is connected to the third input of the first quadrature correlator of the information extraction channel and is the eighth output of the information extraction channel, the output of the second adder modulo two connected to the third input of the second quadrature correlator of the information extraction channel and is the seventh output of the information extraction channel, the first input of the first sum modulo two is the third input of the information extraction channel, the first input of the second adder modulo two is the fourth input of the information extraction channel, the second inputs of the first and second adders modulo two are combined and are the fifth input of the information extraction channel, as well as the first intermediate filter connected in series frequency, the input of which is connected to the output of the first frequency converter, the third frequency converter, the first broadband low-pass filter and the first analog-to-digital converter An indexer connected in series with a second intermediate-frequency filter, the input of which is connected to the output of the second frequency converter, a fourth frequency converter, a second broadband low-pass filter and a second analog-to-digital converter, serially connected to a fifth frequency converter, the first input of which is connected to the output of the first intermediate frequency filter the third broadband low-pass filter, the third analog-to-digital converter, the sixth converter connected in series a frequency divider, the first input of which is connected to the output of the second intermediate-frequency filter, the fourth broadband low-pass filter and the fourth analog-to-digital converter, the second inputs of the fourth and fifth frequency converters being combined and connected through the second phase shifter to π / 2 to the output of the reference oscillator, the second the inputs of the third and sixth frequency converters are combined and connected to the output of the reference generator, connected in series to the first quadrature correlator of the carrier tracking chain the first and the first multiplier, the output of which is connected to the first input of the first adder, the second quadrature correlator of the carrier frequency tracking circuit and the second multiplier, the output of which is connected to the second input of the first adder, the second input of the first multiplier is connected to the 9th output of the information extraction channel allocated for synchronization of the receiver, and the second input of the second multiplier is connected to the 10th output of the channel for allocating information allocated for synchronization of the receiver, the output of the first the adder is connected to the input of the phase error filter, the first inputs of the first and second quadrature correlators of the carrier frequency tracking circuit are combined and connected to the output of the fourth analog-to-digital converter, the second inputs of the first and second quadrature correlators of the carrier frequency tracking circuit are combined and connected to the output of the third analog -digital converter, the third input of the first quadrature correlator of the carrier frequency tracking circuit is connected to the eighth output of the information extraction channel, highlighted To synchronize the receiver, the third input of the second quadrature correlator of the carrier frequency tracking circuit is connected to the seventh output of the information allocation channel dedicated to synchronize the receiver, the first inputs of all information extraction channels, as well as the first inputs of the first and second correlators of the clock tracking circuit are combined and connected to the output of the first analog-to-digital converter, the second inputs of all channels of information extraction, as well as the second inputs of the first and second correlators of the tracking circuit for t are combined and connected to the output of the second analog-to-digital converter, the output of the first correlator of the clock tracking circuit is connected to the first input of the third multiplier, and the output of the second correlator of the clock tracking circuit is connected to the first input of the fourth multiplier, the third input of the k-th channel information extraction is connected to the i-th output of the channel orthogonal code sequence generator, where i takes the value k, the fourth input of the k-th information extraction channel is connected to j- m output of the generator of channel orthogonal code sequences, where j takes the value K-k + 1, and if i equals j, then j takes the value k + 1, the fifth inputs of all channels of information extraction are combined and connected to the first output of the generator of the masking orthogonal code sequence, sixth inputs of all channels of information extraction are combined and connected to the second output of the masking orthogonal code sequence generator, (K + 1) -th output of the channel orthogonal code sequence generator the circuit is connected to the seventh inputs of all the channels of information selection and to the second input of the third integrator, the fifth output of the channel of information separation allocated for synchronization of the receiver, through the first quadrator is connected to the first input of the second adder, and the sixth output of the channel of information selection allocated for synchronization of the receiver, the second quadrator is connected to the second input of the second adder, the output of which through the third integrator and the first threshold device is connected to the combined second inputs of the first, second and of electronic keys, the ninth output of the information isolation channel allocated for synchronizing the receiver is connected to the second input of the third multiplier, the output of which is connected to the first input of the third adder, and the tenth output of the information allocation channel allocated for synchronization of the receiver is connected to the second input of the fourth multiplier, the output of which is connected to the second input of the third adder, the output of the third adder through the first electronic key is connected to the input of the error filter by delay, as well as the fifth multiplier and the fifth broadband lowpass filter, the output of which is connected to the first input of the fourth adder, the sixth multiplier and the sixth broadband lowpass filter, the output of which is connected to the second input of the fourth adder, the first and second inputs of the fifth multiplier are combined and connected to the output of the first intermediate frequency filter, the first and second inputs of the sixth multiplier are combined and connected to the output of the second intermediate filter often s, a matched filter, a third quadrator, a third electronic key, and a second threshold device, the output of which is connected to the first inputs of the channel orthogonal code sequence generator and the mask orthogonal code sequence generator, the third adder modulo two, the seventh multiplier, and the second electronic key are sequentially connected the output of which is connected to the input of the delay error filter, the output of the fourth adder is connected to the input of the matched filter and with the second input of the seventh multiplier, the output of the matched filter is connected to the input of the first inverter and to the first input of the fourth electronic key, the output of the first inverter is connected to the first input of the fifth electronic key, the output of which is connected to the input of the second inverter, the outputs of the second inverter and fourth electronic key are combined and connected to the first input of the third adder modulo two, (K + 2) -th output of the channel orthogonal code sequence generator is connected to the combined second inputs of the four of the second and fifth electronic keys, the output of the controlled clock generator is connected to the second inputs of the third adder modulo two, the generator of channel orthogonal code sequences, the generator of the masking orthogonal code sequence, and also to the second inputs of the fourth and fifth adders modulo two, the seventh output of the channel information selection allocated to synchronize the receiver is connected to the first input of the fourth adder modulo two, the output of which is connected to the third input of the second a relay for tracking the clock frequency, the eighth output of the channel for extracting information allocated for synchronizing the receiver is connected to the first input of the fifth adder modulo two, the output of which is connected to the third input of the first correlator of the tracking chain for the clock frequency, a phase error filter connected in series, the first control an element and a controlled generator, the output of which through the first phase shifter is connected to the second input of the second frequency converter, the second input of the first frequency converter ene-controlled oscillator with the output, the first inputs of first and second inverters are combined and input devices, and series-connected delay error filter, a second control element, controlled by a clock generator.

The aim of the present invention is to develop a multi-channel device that allows for reliable reception of quadrature modulated signals, the signal-code structure of which changes during operation, and re-detection of the signal in case of failure of synchronization.

выход генератора канальных ортогональных кодовых последовательностей соединен с

входами второго и третьего коммутационных устройств, где

принимает значения от 1 до L, (L+1)-ый выход генератора канальных ортогональных кодовых последовательностей соединен с объединенными седьмыми входами всех каналов выделения информации и с вторым входом третьего интегратора, (L+2)-ой выход генератора канальных ортогональных кодовых последовательностей соединен с объединенными вторыми входами четвертого и пятого электронных ключей, k-ый выход второго коммутационного устройства соединен с третьим входом k-ого канала выделения информации, где k принимает значения от 1 до К, k-ый выход третьего коммутационного устройства соединен с четвертым входом k-ого канала выделения информации, выход первого порогового устройства соединен с первым входом устройства повторного обнаружения сигнала, а через элемент развязки - с вторыми входами первого, второго и третьего электронных ключей, второй вход устройства повторного обнаружения сигнала соединен с выходом управляемого тактового генератора, выход устройства повторного обнаружения сигнала соединен с объединенными вторыми входами первого, второго и третьего электронных ключей.This goal is achieved by the fact that in the circuit of the known device, including K channels for the selection of information, where K takes values from 1 to N-1, and N = 2 ⁿ for n≥1, one of which is allocated for synchronization of the receiver, each the information extraction channel includes a series-connected first quadrature correlator of the information extraction channel, a first integrator and a first comparator, as well as a series-connected second quadrature correlator of the information extraction channel, a second integrator and a second comparator, the first inputs of the first and second quadrature correlators of the information extraction channel are combined and are the first input of the k-th information extraction channel, where k takes values from 1 to K, the second inputs of the first and second quadrature correlators of the information extraction channel are combined and are the second input of the k-th channel information extraction, the output of the first comparator is connected to the first input of the decoder and is the first and ninth outputs of the information extraction channel, the output of the second comparator is connected to the second input of the decoder and is are the second and tenth outputs of the information extraction channel, the first output of the decoder is the third output of the information extraction channel, the second output of the decoder is the fourth output of the information extraction channel, the output of the first quadrature correlator of the information extraction channel is the fifth output of the information extraction channel, the output of the second quadrature correlator of the information extraction channel is the sixth output of the information extraction channel, the second inputs of the first and second integrator and the third input of the decoder are combined and I are the seventh input of the information extraction channel, the fourth input of the decoder is the sixth input of the information extraction channel, the output of the first adder modulo two is connected to the third input of the first quadrature correlator of the information extraction channel and is the eighth output of the information extraction channel, the output of the second adder modulo two is connected to the third the input of the second quadrature correlator of the information extraction channel and is the seventh output of the information extraction channel, the first input of the first adder modulo two is the third input of the information extraction channel, the first input of the second adder modulo two is the fourth input of the information extraction channel, the second inputs of the first and second adders modulo two are combined and are the fifth input of the information extraction channel, as well as the first intermediate frequency filter, the input of which is connected in series connected to the output of the first frequency converter, a third frequency converter, a first broadband low-pass filter and a first analog-to-digital converter, subsequently the second intermediate frequency filter, the input of which is connected to the output of the second frequency converter, the fourth frequency converter, the second broadband low-pass filter and the second analog-to-digital converter, the fifth frequency converter in series, the first input of which is connected to the output of the first intermediate frequency filter, third broadband low-pass filter, third analog-to-digital converter, serially connected sixth frequency converter, first the first input of which is connected to the output of the second intermediate-frequency filter, the fourth broadband low-pass filter and the fourth analog-to-digital converter, the second inputs of the fourth and fifth frequency converters being combined and connected through the second phase shifter to π / 2 to the output of the reference oscillator, the second inputs of the third and sixth frequency converters are combined and connected to the output of the reference generator, connected in series to the first quadrature correlator of the carrier frequency tracking circuit and the first a multiplier whose output is connected to the first input of the first adder, a second quadrature correlator of the carrier frequency tracking circuit and a second multiplier, the output of which is connected to the second input of the first adder, the second input of the first multiplier is connected to the 9th output of the information allocation channel dedicated to synchronization of the receiver, and the second input of the second multiplier is connected to the 10th output of the channel allocation information allocated for synchronization of the receiver, the output of the first adder is connected with the phase error filter input, the first inputs of the first and second quadrature correlators of the carrier frequency tracking circuit are combined and connected to the output of the fourth analog-to-digital converter, the second inputs of the first and second quadrature correlators of the carrier frequency tracking circuit are combined and connected to the output of the third analog-digital converter, the third input of the first quadrature correlator of the carrier frequency tracking circuit is connected to the eighth output of the channel for selecting information allocated for synchronization and a receiver, the third input of the second quadrature correlator of the carrier frequency tracking circuit is connected to the seventh output of the information allocation channel dedicated to synchronize the receiver, the first inputs of all information extraction channels, as well as the first inputs of the first and second correlators of the clock tracking circuit are combined and connected to the output of the first analog-to-digital converter, the second inputs of all channels of information extraction, as well as the second inputs of the first and second correlators of the tracking circuit for the clock frequency o are connected and connected to the output of the second analog-to-digital converter, the output of the first correlator of the clock tracking circuit is connected to the first input of the third multiplier, and the output of the second correlator of the clock tracking circuit is connected to the first input of the fourth multiplier, the third input of the k-th channel of information allocation connected to the i-th output of the channel orthogonal code sequence generator, where i takes the value k, the fourth input of the k-th channel of information extraction is connected to the j-th output of the generator channel orthogonal code sequences, where j takes the value K-k + 1, and if i equals j, then j takes the value k + 1, the fifth inputs of all channels of information extraction are combined and connected to the first output of the masking orthogonal code sequence generator, the sixth inputs all channels of information extraction are combined and connected to the second output of the masking orthogonal code sequence generator, the (K + 1) -th output of the channel orthogonal code sequence generator is connected to seven through the first input of the third integrator, the fifth output of the information extraction channel allocated for synchronization of the receiver is connected through the first quadrator to the first input of the second adder, and the sixth output of the information allocation channel allocated for synchronization of the receiver is connected through the second quadrator with the second input of the second adder, the output of which through the third integrator and the first threshold device is connected to the combined second inputs of the first, second and third electronic x keys, the ninth output of the channel for extracting information allocated for synchronizing the receiver is connected to the second input of the third multiplier, the output of which is connected to the first input of the third adder, and the tenth output of the channel for extracting information allocated for synchronizing the receiver is connected to the second input of the fourth multiplier, output which is connected to the second input of the third adder, the output of the third adder through the first electronic key is connected to the input of the error filter by delay, and is also connected in series e fifth multiplier and fifth broadband low-pass filter, the output of which is connected to the first input of the fourth adder, the sixth multiplier and the sixth broadband low-pass filter, the output of which is connected to the second input of the fourth adder, the first and second inputs of the fifth multiplier are combined and connected to the output the first intermediate frequency filter, the first and second inputs of the sixth multiplier are combined and connected to the output of the second intermediate frequency filter, in series connected matched filter, third quadrator, third electronic key and second threshold device, the output of which is connected to the first inputs of the channel orthogonal code sequence generator and the mask orthogonal code sequence generator, the third adder modulo two is connected in series, the seventh multiplier and the second electronic key, the output of which connected to the input of the delay error filter, the output of the fourth adder is connected to the input of the matched filter and to the second input of the seventh multiplier, the output of the matched filter is connected to the input of the first inverter and to the first input of the fourth electronic key, the output of the first inverter is connected to the first input of the fifth electronic key, the output of which is connected to the input of the second inverter, the outputs of the second inverter and fourth electronic key are combined and connected to the first the input of the third adder modulo two, (K + 2) -th output of the channel orthogonal code sequence generator is connected to the combined second inputs of the fourth and fifth ele throne keys, the output of the controlled clock generator is connected to the second inputs of the third adder modulo two, the generator of channel orthogonal code sequences, the generator of the masking orthogonal code sequence, and also to the second inputs of the fourth and fifth adders modulo two, the seventh output of the channel of information allocation allocated for synchronization of the receiver, connected to the first input of the fourth adder modulo two, the output of which is connected to the third input of the second correlator circuit tracking clock frequency, the eighth output of the channel for extracting information allocated for receiver synchronization is connected to the first input of the fifth adder modulo two, the output of which is connected to the third input of the first correlator of the clock frequency tracking circuit, a phase error filter, a first control element, and controlled generator, the output of which through the first phase shifter is connected to the second input of the second frequency converter, the second input of the first frequency converter is connected to the control output generator, the first inputs of the first and second frequency converters are combined and are the device input, as well as a delay delay filter connected in series, the second control element is controlled by a clock generator, the following changes have been made, namely: the following are excluded from the device diagram: masking orthogonal code sequence generator , a generator of channel orthogonal code sequences and the connection between the output of the first threshold device and the second inputs of the first, second and t of electronic keys, and the device circuitry additionally includes: a masking orthogonal code sequence generator, a channel orthogonal code sequence generator, first, second and third switching devices, a signal re-detection device and an isolation element, and the following connections between device elements are established: the first input of the masking generator the orthogonal code sequence is connected to the output of the second threshold device, the second input of the generator masking about of the orthogonal code sequence is connected to the output of the controlled clock generator, the i-th output of the masking orthogonal code sequence generator is connected to the i-th input of the first switching device, where i takes values from 1 to I (I can take values 2, 3, ...), ( The I + 1) -th output of the masking orthogonal code sequence generator is connected to the combined sixth inputs of all information extraction channels, the output of the first switching device is connected to the combined fifth inputs of all catch allocation information generator first input channel orthogonal code sequences coupled to an output of the second threshold device, the second input of the generator channel orthogonal code sequences managed connected to the output of the clock generator,

the output of the channel orthogonal code sequence generator is connected to

the inputs of the second and third switching devices, where

takes values from 1 to L, the (L + 1) -th output of the channel orthogonal code sequence generator is connected to the combined seventh inputs of all information extraction channels and to the second input of the third integrator, the (L + 2) -th output of the channel orthogonal code sequence generator is connected with the combined second inputs of the fourth and fifth electronic keys, the k-th output of the second switching device is connected to the third input of the k-th channel of information allocation, where k takes values from 1 to K, the k-th output of the third a mutation device is connected to the fourth input of the k-th channel of information extraction, the output of the first threshold device is connected to the first input of the signal re-detection device, and through the decoupling element, to the second inputs of the first, second and third electronic keys, the second input of the signal re-detection device is connected to the output of a controlled clock generator, the output of the device for re-detection of the signal is connected to the combined second inputs of the first, second and third electronic keys.

Distinctive features of the proposed device are new elements introduced into the receiver circuit, namely: a masking orthogonal code sequence generator, channel orthogonal code sequence generator, first, second and third switching devices, first, second and third electronic keys, a signal re-detection device and corresponding communications between them, due to which it was possible to ensure reliable reception of quadrature modulated signals, the signal-code design of which rykh changes during continuous operation, as well as re-detection of the signal in case of failure of synchronization, which meets the criterion of "novelty."

Since the totality of the introduced elements and their relationship to the filing date of the application in the patent and scientific literature are not found, the proposed technical solution corresponds to the "inventive step".

The structural diagram of the inventive device is shown in FIG. 1 and 2. In order to simplify the circuit of FIG. 1 shows only one k-th (k = 1) channel of information extraction, as well as elements that ensure the functioning of the device and allow to explain its operation as a whole. In FIG. 1 presents a General diagram of the device, in which the numbers denote:

1, 16 - phase shifter on π / 2 (PV);

2 - controlled generator (UG);

3, 52 - control element (RE);

4 - phase error filter (FFO);

5, 15, 18, 20, 32, 34 - frequency converter (IF);

6, 14, 21, 31, 37, 39 — broadband low-pass filter (CFC);

7, 13, 22, 30 - analog-to-digital converter (ADC);

8, 12 — quadrature correlator of a chain for tracking the carrier frequency (QF LF);

9, 11, 38, 40, 49, 59, 60 - multiplier (P);

10, 36, 61, 64 - adder (cm);

17 - reference generator (OG);

19, 33 - intermediate frequency filter (FPC);

23, 29 - quadrature correlator of the channel for the allocation of information (KK KVI);

24, 28, 63 - integrator (Int.);

25, 27 - comparator (KM);

26 - decoder (DK);

35 - matched filter (SF);

41, 42, 48, 54, 55 - adder modulo two (cm2);

43, 50, 56, 69, 70 - electronic key (EC);

45, 65, 66 - quadrator (HF);

46 - channel orthogonal code sequence generator (GKOKP);

47 - generator masking orthogonal code sequence (GMOKP);

51 - controlled clock (UTG);

53 - delay error filter (FDF);

57, 58 — quadrature correlator of a clock tracking chain (CC PM);

44, 62 - threshold device (PU);

67, 68 - channel information allocation (CVI);

71, 72 - inverter (Inv.);

73, 74, 75 - the first, second and third switching devices (KU);

76 - device re-detection of the signal (UPOS);

77 - element of denouement.

In FIG. Figure 2 shows the structural scheme of the UPOS (76). The numbers in FIG. 2 are indicated:

1 - frequency divider (DF);

2 - subtracting counter (Wh);

3 - decoder (L)

4 - inverter (Inv.).

The work of the receiver. Let us consider the operating procedure of the receiver according to the block diagram shown in FIG. one.

When considering the operation of the receiver, we will proceed from the following:

1. At the input of the receiving device receives an additive mixture of signal and noise of the form

where s (t) is the group signal actually received by the receiver;

n (t) is the noise at the input of the receiver.

The received signal at the input of the K-channel receiver is presented in the form:

where A is the signal amplitude;

ω _o - carrier angular frequency of the signal;

t is the current time;

- i-ая канальная ортогональная кодовая последовательность в синфазном k-ом КВИ на

интервале времени;

- i-th channel orthogonal code sequence in in-phase k-th KVI on

time interval;

- j-ая канальная ортогональная кодовая последовательность в квадратурном k-ом КВИ на

интервале времени;

- j-th channel orthogonal code sequence in quadrature k-th KVI on

time interval;

k is the number of CVI, k takes values from 1 to K, and K takes values from 1 to N-1, a N = 2 ⁿ for n≥1;

i is the number of one of the channel orthogonal code sequences from the ensemble of sequences generated by GKKP (46), i takes the values 1, 2, ... K, ... L;

j is the number of one of the channel orthogonal code sequences from the ensemble of sequences generated by GKKP (46), j takes the values 1, 2, ... K, ... L; where i ≠ j.

- длительность канальной ортогональной кодовой последовательности, генерируемой ГКОКП (46), равная длительности информационного символа;

- the duration of the channel orthogonal code sequence generated by GKKP (46), equal to the duration of the information symbol;

, где m - число канальных ортогональных кодовых последовательностей, укладывающихся на интервале маскирующей ортогональной кодовой последовательности;П0 _i - one of the masking orthogonal code sequences generated by GMOKP (47), i takes the values 1, 2, ... I; simultaneously performs the function of cyclic synchronization, and its duration S is a multiple of the duration of the channel orthogonal code sequence generated by GKKP (46), i.e.

where m is the number of channel orthogonal code sequences that fit on the interval of the masking orthogonal code sequence;

- фрагмент i-ой маскирующей ортогональной кодовой последовательности, генерируемой ГМОКП (47) на интервале

;

- a fragment of the i-th masking orthogonal code sequence generated by GMOKP (47) in the interval

;

- фаза сигнала в синфазном k-ом КВИ на

интервале времени. Причем значение фазы на

интервале времени постоянно, зависит от знака информационного символа и может принимать значения 0 или π;

- phase of the signal in common mode k-th KVI on

time interval. Moreover, the phase value at

the time interval is constant, it depends on the sign of the information symbol and can take the values 0 or π;

- фаза сигнала в квадратурном k-ом КВИ на

интервале времени. Причем значение фазы постоянно на

интервале времени, зависит от знака информационного символа и может принимать значения π/2 или -π/2.

- phase of the signal in quadrature k-th KVI on

time interval. Moreover, the phase value is constantly on

the time interval depends on the sign of the information symbol and can take the values π / 2 or -π / 2.

The noise component at the input of the K-channel receiver has the form

;where ψ (t) is the phase of the noise components n _cs (t) and n _sn (t), which is a random process uniformly distributed over the interval

;

n _cs (t), n _sn (t) are the amplitudes of the noise components in the in-phase and quadrature channels, respectively.

Moreover, n (t), n _cs (t), n _sn (t) are random processes distributed according to the normal law with a zero mean value. The spectral power density of the process n (t) is N ₀ , and for the processes n _cs (t) and n _sn (t) - N _0/2 ; dispersion n (t) process is σ ^2, and processes n _cs (t) and n _sn (t) - σ ^2/2, i.e.

2. At the output of the UG (2), a signal of the form

where ω _g is the frequency of UG;

ϕ is the initial phase of the UG frequency relative to the frequency of the received signal.

At the output of the PV (1), the signal has the form

. Каждому информационному символу соответствует канальная ортогональная последовательность. Для повышения структурной скрытности каждый информационный блок «закрывается» маскирующей последовательностью, длина которой равна S.3. Information in the channel is transmitted by blocks of the S-th length, each block includes m information symbols, the duration of each of which is equal to

. Each information symbol corresponds to a channel orthogonal sequence. To increase structural secrecy, each information block is “closed” by a masking sequence whose length is S.

4. To ensure high structural secrecy in the group signal received at the input of the receiving device, in the explicit form, there is no pilot signal (synchronization signal). To solve the problems of signal detection, synchronization, as well as tracking the carrier and clock frequencies, the information circulating in the received group signal is used. Moreover, in the baseband signal necessarily contains two channel orthogonal code sequences m gives the sequence whose product P _C. The SF is also tuned to this sequence (35). The same sequence П _С with the (L + 2) -th output of GKKPP (46) is supplied to the first input of Sm2 (48) through the corresponding open EC (69) or (70).

5. At the moment of switching on the receiving device, the beginning of the sequences generated by GKOKP (46) and GMOKP (47) do not coincide with each other, and also, as a rule, do not coincide with the beginning of the sequences received at the input of the receiving device.

6. The beginning of the masking sequence arriving at the input of the receiving device coincides with the beginning of the information block arriving at the input of the receiving device and with the beginning of the first channel sequence in the information block.

7. After the receiving device is turned on, the electronic keys, (43) and (50) are open, the EC (56), (69) and (70) are closed, and the subtracting counter (2) in the UPOS (76) (see Fig. 2) zeroed (i.e. all counter cells are in the zero state).

8. The threshold value of the control panel (62) in the general case is determined by the required value of the probability of false alarms and is selected based on the following conditions:

, не должно превышать величины выбранного порога;the total value of the interfering components of the in-phase and quadrature channels (interfering components from 5 and 6 outputs of the CVI (67)), accumulated Int. (63) on the interval of the duration of the information symbol

, must not exceed the value of the selected threshold;

, чтобы обеспечить закрытие ЭК (43) и (50) и открытие ЭК (56) до момента появления очередного импульса с выхода СФ (35).the total value of the energy of the components of the useful signal of the in-phase and quadrature channels (components of the useful signal from 5 and 6 outputs of the CVI (67)), accumulated Int. (63), must exceed the value of the selected threshold for a time interval of less than

in order to ensure the closure of EC (43) and (50) and the opening of EC (56) until the appearance of the next pulse from the output of the SF (35).

9. At the exhaust gas output (17), a signal of the form

and at the output of the PV (16) a signal of the form

where _ωg is the frequency of the exhaust gas, and its value corresponds to the value of the intermediate frequency ω _pr at the output of the phase-transfer filter (19) and (33).

10. To increase the structural secrecy of the signals, we assume that in each k-th CVI two different channel orthogonal code sequences from the ensemble of sequences generated by GKOKP (46) should be used, i.e. in the in-phase channel of the k-th KVI, the sequence with the number i is used, and in the quadrature channel of the k-th KVI - the sequence with the number j. The volume of the ensemble of sequences generated by GKKPP (46) is L.

с выхода ПУ (62) на первый вход УПОС (76) не поступил ни один импульс.11. We assume that the device exited the synchronization mode, if in the time interval

from the output of the control unit (62) to the first input of the control device (76) did not receive a single pulse.

12. KU (73) provides the connection of the outputs of the GMOKP (47) to the fifth inputs of the corresponding channels, KU (74) provides the connection of the outputs of the GKOKP (46) to the third inputs of the corresponding channels, and KU (75) provides the connection of the outputs of the GMOKP (46) to the fourth the inputs of the respective channels, and the switching of the inputs and outputs of the control units (74) and (75) is carried out in such a way that different channel orthogonal code sequences arrive at the third and fourth inputs of any CVI.

In the general case, the operation of the receiver consists in solving the following problems: signal detection;

establishment and maintenance of receiver synchronization on carrier and clock frequencies;

highlighting information;

re-detection of a signal in case of failure of synchronization.

The work of the receiver. Let an additive mixture of the signal s (t) (2) and noise n (t) (3) be supplied to the input of the receiver, and, consequently, to the first inputs of the inverter (18) and (34).

At the same time, to the second input of the inverter (18) directly, and to the second input of the inverter (34) through the PV (1) from the output of the UG (2), signals of the form (5) and (6) are applied, respectively.

Then the signal component in the in-phase channel can be represented as

and the noise component - in the form

and in the quadrature channel the signal component is in the form

and the noise component - in the form

As a result of transformations of the signal and noise components in the inverter (18) and in the inverter (34), the components of the total (ω _Σ = ω _o + ω _g ) and difference (ω _p = ω _o -ω _g ) signal and noise frequencies will appear at their outputs . The components of the total frequency ω _{Σ of the} signal and noise are suppressed by the filters of the intermediate frequency (19) and (33), and the components of the difference frequency sr (let's call it the intermediate frequency ω _pr ) pass through the phase-transfer filter (19) and (33).

Then the signal component at the output of the PLL (19) (common mode channel) will have the form

and the noise component is

where u _шcs - the amplitude of the noise in the common mode channel;

u _ssn - noise amplitude in the quadrature channel.

And the signal component at the output of the PLL (33) (quadrature channel) will have the form

and the noise component is

Receiver operation in signal detection mode. The signal from the output of the PLL (19) (common mode channel) of the form (13) and (14) is fed to the first and second inputs P (38), and the output of the PLL (33) (quadrature channel) is a signal of the form (15) and (16) - to the first and second inputs P (40).

The signal at the output P (38) can be represented as

After squaring, expression (17) takes the form

, где

, а

и

выражениеTaking into account that

where

, but

and

expression

, где

, а

и

выражениеTaking into account that

where

, but

and

expression

, где

, а

;

;

, где

- одна из последовательностей, генерируемых ГКОКП (46), то выражениеGiven that

where

, but

;

;

where

is one of the sequences generated by GKKPP (46), then the expression

, где

, а

;

;

, где

- одна из последовательностей, генерируемых ГКОКП (46), выражениеGiven that

where

, but

;

;

where

- one of the sequences generated by GKKPP (46), the expression

, где

, а

;

;

, где

- одна из последовательностей, генерируемых ГКОКП (46), выражениеGiven that

where

, but

;

;

where

- one of the sequences generated by GKKPP (46), the expression

Expression

Expression

Expression

Expression

Expression

Expression

From the analysis of the above expressions it follows that in the multiplier (38) as a result of multiplying the signals received at its inputs, components of the total and difference frequencies of the signal and noise appear at its output.

The components of the total signal frequency and common-mode channel noise are suppressed by the low-pass filter (37), and the low-frequency components pass through the low-pass filter (37). Then the signal at the output of the LPF (37) takes the form

и

могут принимать значения только 0 или π, a

и

- только π/2 или -π/2, тогда

,

и

, то сигнал на выходе ШФНЧ (37) можно представить в видеTaking into account that

and

can take values only 0 or π, a

and

- only π / 2 or -π / 2, then

,

and

, then the signal at the output of the LPF (37) can be represented as

представляет собой последовательность П_с, на которую настроен СФ (35), слагаемые в фигурных скобках представляют собой шумовую составляющую сигнала в синфазном канале. Этот сигнал поступает на первый вход См (36).From the analysis of expression (17c) it follows that the terms in parentheses are a constant value, the terms in square brackets are direct or inverse orthogonal code sequences from an ensemble of sequences generated by GKKP (46), and the fourth term

represents the sequence P _s , to which the SF is configured (35), the terms in curly brackets represent the noise component of the signal in the in-phase channel. This signal is fed to the first input, see (36).

The signal at the output P (40) can be represented as

After squaring, expression (18) takes the form

If we carry out transformations with expression (18a) similar to the transformations carried out with expression (17a), it will become clear that in the multiplier (40) as a result of multiplying the signals received at its inputs, the components of the total and difference frequencies of the signal appear at its output and noise.

The components of the total frequency of the signal and the noise of the quadrature channel are suppressed by the LPF (39), and the low-frequency components pass through the LPF (39). Then the signal at the output of the LPF (39) takes the form

представляет собой последовательность П_с, на которую настроен СФ (35), слагаемые в фигурных скобках представляют собой шумовую составляющую сигнала в квадратурном канале. Этот сигнал поступает на второй вход См (36).From the analysis of expression (18b) it follows that the terms in parentheses are a constant value, the terms in square brackets are direct or inverse orthogonal code sequences from an ensemble of sequences generated by GKKP (46), and the fourth term

represents the sequence P _s , to which the SF is configured (35), the terms in braces represent the noise component of the signal in the quadrature channel. This signal is fed to the second input, see (36).

The resulting signal at the output of cm (36) can be represented as

A signal of the form (19) is fed to the input of the SF (35) and to the second input P (49).

Given that the sequence P _C can be either direct or inverse, a positive or negative impulse appears at the output of the matched filter (35).

The signal from the output of the SF (35) through the quadrator (45) and the open EC (43) is fed to the input of the control unit (44), in which the levels of the incoming signal and the set threshold are compared. When the signal exceeds the threshold value, a decision is made to detect the signal and a voltage pulse appears at the output of the control unit (44), which is fed to the first inputs of the GKOKP (46) and GMOKP (47). This signal sets them to their original state. From this moment we can assume that:

the beginnings of all channel orthogonal code sequences generated by GKKPP (46), namely, the sequences at the outputs 1 ... L and the sequences at the (L + 2) -th output, coincide with the beginning of the received channel orthogonal code sequences (including the beginning of the sequence П _с , coming from the (L + 2) -th output of GKOKP (46) to the first input of Sm2 (48), coincides with the beginning of the sequence of 77 s, which comes from the output of Sm (36) to the second input of P (49));

the beginnings of channel orthogonal code sequences, both generated by GKOCP (46) and received, coincide with the beginning of a masking orthogonal code sequence generated by GMKKP (47).

It should be noted that the match is provided within the interval of the duration of the elementary symbol of the channel and masking sequences, namely, in the range (-T _o / 2≤τ≤ + T _o / 2), where T _o is the duration of the elementary symbol of the sequences, and τ - the amount of delay.

Only the beginning of the masking sequence generated by GMOCP (47) does not coincide with the beginning of the received masking sequence.

The next pulse generated at the output of the control unit (44) is also fed to the first inputs of the GKOKP (46) and the GMOKP (47) and sets them to their initial state if they are in a different state. But since the beginnings of the channel sequences generated by GKKP (46) and the beginnings of the channel sequences received by the receiver already coincide (this provided the first impulse, i.e., GKKP (46) is already in the initial state at this moment), then this impulse does not change the operation mode of GKKP (46). But this impulse, received at the first input of the GMOCP (47), sets it again to its original state, and it begins to form a masking sequence first. And this process will take place until the beginning of the masking sequence generated by GMOCP (47) coincides with the beginning of the accepted masking sequence.

Joint synchronous operation of the generators GMOKP (47) and GKOKP (46) is provided by the UTG (51), from the output of which clock pulses are fed to their second inputs.

From the analysis of expression (19) it follows that the first term is a constant and, therefore, this component is orthogonal to the characteristic of the matched filter (35), i.e. they do not miss. The second term is a useful signal and a matched filter is tuned to it. The third term is the noise component, which SF (35) is averaged.

Then the ratio of the signal power to the noise power at the output of the SF (35) can be represented as

where N is the number of elementary symbols in the channel orthogonal code sequence;

And _d , u _{d shes} - the effective values of the amplitudes of the signal and noise on the interval of the elementary symbol, respectively;

u ² _{d shes} = Р _shes - the average value of the noise power in the interval of an elementary symbol;

And ² _d = R _SES - the value of the signal power in the interval of an elementary symbol.

From the analysis of expression (20) it follows that when a signal is detected, there are no losses, i.e. the proposed signal detection circuit is an optimal device.

Simultaneously with the process of establishing coincidences of the beginnings of the received and generated GMOCP (47) of masking sequences (i.e., simultaneously with the process of establishing synchronization by the masking sequence), the UTG clock frequency is monitored (51). Why does the channel direct or inverse sequence P _s go to the first input of Sm2 (48) from the (L + 2) -th output of GKOKP (46) through open EC (69) or (70), and its second input receives clock pulses from the output of the UTG (51).

If a negative impulse appears at the output of the SF (35), (in this case, the inverse sequence П _{с s} arrives at the second input P (49) from the output of Cm (36)), then this pulse through Inv. (71) opens EC (70) and the sequence P _s , s (L + 2) -th output of GKKP (46) through open EC (70) and Inv. (72) enters the first input of Sm2 (48).

If a positive impulse appears at the output of the SF (35), (in this case, the direct sequence P _s arrives from the output of Cm (36) to the second input P (49)), then this pulse opens EC (69) and the sequence P _s , s ( The L + 2) -th output of GKOKP (46) through the open EC (69) goes to the first input of Sm2 (48).

и

.In Sm2 (48), the flows arriving at its first and second inputs are modulo two. The total signal from the output of Sm2 (48) is supplied to the first input P (49), the second input of which receives the signal from the output of Sm (36), which contains the sequence P _s (direct or inverse) obtained by multiplying the received sequences

and

.

In the multiplier (49), a convolution of the received signals is carried out and at its output, along with the noise component, there is a signal that carries information about the magnitude of the mismatch in the clock delay of the received and generated GKOKP (46) sequences. The signal from the output P (49) through the open EC (50) is fed to the input of the PhD (53). The delayed error protection phase signal (53) is fed to the UE input (52), which, acting on the UTG (51), adjusts its clock frequency to the clock frequency of the received sequence P _s , leading to a delay error τ of zero.

Thus, even at the initial stage of receiver synchronization (there is no synchronization in the masking sequence П0 yet), tracking of the clock frequency is ensured.

At the end of each cycle of generating channel orthogonal code sequences, pulses appear at the (L + 1) -th output of GKKP (46), the repetition rate of which is determined by the period of the generated sequence. This stream of pulses arrives at the seventh inputs of all channels of information allocation and the second input Int. (63) and ensures the joint operation of all channel integrators (as applied to the first channel, it is Int. (24), (28)) and the integrator (63), and also provides sequential input of information to the decoding device of each CVI (as applied to the first CVI, it is a DC (26)) and serial output of information from it.

As soon as the beginning of the masking sequence formed by GMOKP (47) coincides with the beginning of the accepted masking sequence, the process of extracting information begins in CVI (67) and information samples (voltage responses) appear on its 5th and 6th outputs, which are received at KV inputs (65) and (66), respectively. In HF (65) and (66), the incoming signal is squared and from their outputs goes to the first and second inputs of Cm (64), respectively. The total signal output Cm (64) is fed to the first input Int. (63) in which the accumulation of energy occurs. The resulting value of the stored energy output Int. (63) constantly goes to the input of the control panel (62), in which this value is compared with a threshold. At the moment of exceeding the value of the stored energy of the set threshold, a signal appears at the output of the control unit (62), which sets the UPOS (76) to the operating state (the operation of the UPOS will be discussed below), and through the isolation element (77) it closes the EC (43) and (50) and opens EC (56).

Closed EC (43) prevents further fine tuning of GMOCP (47), since the beginning of the masking sequence generated by GMOCP (47) already coincides with the beginning of the received masking sequence.

One of the i masking orthogonal code sequences formed by GMOKP (47), where i takes values from 1 to I, through the first switching device (73) is fed to the fifth inputs of all CVI. At the end of each cycle of generating a masking orthogonal code sequence, pulses appear at the (I + 1) th output of the GMOCP (47), the repetition rate of which is determined by the period of the generated sequence. This stream of pulses is fed to the 6th inputs of all channels of information extraction and provides cyclic synchronization of decoders of these channels.

Closed EC (50) and open EC (56) provide switching the tracking mode for the clock frequency. A closed EC (50) eliminates the possibility of tracking the clock frequency according to the sequence P _C allocated in the process of signal detection (since EC (50) breaks the circuit between the output P (49) and the input of the PhD (53)), and the open EC ( 56) provides the connection of the output Cm (61), on which information is generated on the magnitude of the mismatch of the clock frequencies on the received information signal, to the input of the PhD (53). The process of generating a signal about the magnitude of the mismatch of clock frequencies for the received information signal will be discussed below.

The operation of the receiver in the mode of selection of information. The operation of the receiver in the mode of extracting information can conditionally be divided into two stages. At the first stage, a group video signal is extracted from the received group radio signal, and at the second stage, from the received group video signal, each CVI extracts the actual information transmitted on this channel.

I stage. Signals (signal and noise components of the form (13), (14) and (15) and (16) from the output of the intermediate frequency filters (19) and (33) are fed to the first IF inputs (20) and (32), respectively. the second input of the inverter (20) and (32) receives a harmonic signal from the exhaust gas (17), and directly to the inverter (20), and through the inverter (32) through the PV (16).

As a result of transformations of the signal and noise components in the inverter (20) and (32), the components of the total and difference frequencies of the signal and noise will appear at their outputs. The components of the total frequency of the signal and noise are suppressed by the LPF (21) and (31), and the components of the difference frequency (video signal) pass through the LPF (21) and (31) and are fed to the ADC inputs (22) and (30), respectively, in which the video signal digitized. From the output of the ADC (22), the video signal is digitally fed to the first inputs of all the CVI and to the first inputs of the CC CC (57) and (58), and from the output of the ADC (30) - to the second inputs of all CVI and to the second inputs of the CC CC ( 57) and (58).

The above transformations can be analytically presented as follows.

The signal component at the inverter output (20) s _outs (t) (common mode channel) in general can be represented as

and taking into account expressions (7) and (13), as well as the condition that ω _og = ω _pr expression (21) will take the form

A signal of the form (22) is fed to the input of the high-pass filter (21), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the LPF (21), at its output, the signal component will have the form

The noise component at the inverter output (20) n _output (t) (common mode channel) can be represented in general form as

Taking into account expressions (7) and (14), as well as the condition that ω _σ = ω _pr, expression (24) takes the form

A signal of the form (25) is fed to the input of the LPF (21), and after transformations to the LPF (21), the noise component at its output will have the form

The signal component at the output of the inverter (32) s _outsn (t) (quadrature channel) in general can be represented as

and taking into account expressions (8), (15), as well as the condition that ω _og = ω _pr expression (27) will take the form

A signal of the form (28) is fed to the input of the LPF (31), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the LPF (31) at its output, the signal component will have the form

The noise component at the inverter output (32) n _{output ssn} (t) (quadrature channel) in general can be represented as

Taking into account expressions (8) and (16), as well as the condition that ω _σ = ω _pr, expression (30) takes the form

A signal of the form (31) is fed to the input of the LPF (31), and after transformations to the LPF (31), the noise component at its output will have the form

II stage. The work of the channel for highlighting information.

Isolation of information by channels begins from the moment of coincidence of the beginnings of the masking sequence generated by GMOKP (47) and the accepted masking sequence. Let us consider the operation of the information extraction channel according to the block diagram of the CVI (67) shown in FIG. one.

The first input of the CVI (67), and, consequently, the first inputs of the CC KVI (23) and (29) from the output of the ADC (22), is fed a digital signal, and the second input of the CVI (67), and, therefore, and the second inputs of the CC KVI (23) and (29) from the output of the ADC (30) also receive a video signal in digital form.

), а на четвертый вход КВИ (67), а, следовательно, и на первый вход См2 (42) с первого выхода третьего коммутационного устройства (75) поступает одна из L опорных канальных ортогональных кодовых последовательностей, генерируемых ГКОКП (46) (пусть это будет последовательность

)One of the L channel reference orthogonal code sequences generated by GKKP (46) is supplied to the third input of the CVI (67), and, therefore, to the first input of Sm2 (41) from the first output of the second switching device (74) (let it be a sequence

), and the fourth input of the CVI (67), and, consequently, the first input of Sm2 (42) from the first output of the third switching device (75) receives one of the L reference channel orthogonal code sequences generated by GKOKP (46) (let this there will be a sequence

)

One of the masking orthogonal code sequences comes to the fifth input of the CVI (67), and, consequently, to the second inputs of Sm2 (41) and Sm2 (42) from the output of the first switching device (73) (let it be the sequence П0).

. Результирующая последовательность

с выхода См2 (41) подается на третий вход КК КВИ (23) и через восьмой выход КВИ (67) - на третий вход КК НЧ (8) и на первый вход См2 (55).In Sm2 (41), the modulo two two sequences П0 and

. Resulting sequence

from the output of Sm2 (41) it is fed to the third input of the KK KVI (23) and through the eighth output of the KVI (67) - to the third input of the KK LF (8) and to the first input of Sm2 (55).

. Результирующая последовательность 7/02=770 0772/1 к с выхода См2 (42) подается на третий вход КК КВИ (29) и через седьмой выход КВИ (67) - на третий вход КК НЧ (12) и на первый вход См2 (54).In Sm2 (42), the modulo two two sequences П0 and

. The resulting sequence 7/02 = 770 0772/1 k from the output of Sm2 (42) is fed to the third input of the KK KVI (29) and through the seventh output of the KVI (67) to the third input of the KK LF (12) and to the first input of Sm2 (54) )

In the CVI quadrature correlators (23) and (29), the received signals (digital video signals) are multiplied with the resulting sequences P01 and P02, as well as the information component of the signal transmitted in the in-phase channel is extracted from the video signal received in the in-phase and quadrature channels (CC) CVI (23)) and extracting the information component of the signal transmitted in the quadrature channel from the video signal received in the in-phase and quadrature channels (CC CVI (29)). Implementation options for quadrature correlators of CVI and a description of the principle of their operation are presented in [2].

The total value of the samples from the output of the QC KVI (23) is supplied to the first input Int. (24) and to the fifth output of the CVI (67), and from the output of the CC KVI (29) to the first input of Int. (28) and to the sixth exit of KVI (67).

The samples at the fifth and sixth outputs of the CVI (67) provide switching of the tracking mode for the clock frequency according to the sequence П _С to the tracking mode for the clock frequency according to the received information signal.

In integrators (24) and (28), all samples arriving at the interval of the duration of the information symbol (the interval of the duration of the channel orthogonal sequence) are summed. At the end of the cycle of formation of channel orthogonal sequences (end of the information symbol) from the (L + l) -th output of GKKPP (46) to the second inputs of Int. (24) and (28) a pulse arrives that transfers the contents of the integrators in the form of a pulse of positive or negative polarity to the corresponding inputs of the comparators (25) and (27).

Given the above, as well as expressions (23), (26), (29), (32), the values of the information and noise components at the output of the integrator (24) (common mode channel) can be represented as:

for voltage signal component

and for the power of the signal component

for the noise component, taking into account that when passing through the quadrature correlator its statistical characteristics do not change, the value of its power can be represented as

Then the ratio of signal power to noise power at the output of the integrator, and, therefore, at the output of the information channel will be

Expression (36) gives reason to believe that the reception of information is optimal, since there is no signal energy loss.

Similar considerations hold true for the quadrature channel (i.e., with respect to the ratio of signal power to noise power at the output of Int. (28)).

In the comparators (25) and (27), the flow of bipolar pulses arriving at their inputs from the corresponding outputs of the integrators (24) and (28) is converted into a sequence of information symbols.

From the output of the CM (25), a sequence of information symbols is fed to the first output of the CVI (67), to the first input of the DC (26) and through the ninth output of the CVI (67) to the second inputs P (9) and P (59), and from the output of the CM (27) - to the second output of the CVI (67), to the second input of the DC (26) and through the tenth output of the CVI (67) to the second inputs P (11) and P (60).

The decoder (26) decodes the information received at its first and second inputs. An embodiment of the decoder and a description of the principle of its operation are presented in [2].

So, the first and second outputs of CVI (67) are outputs of not decoded information of in-phase and quadrature channels, respectively, and its third and fourth outputs are outputs of decoded information of in-phase and quadrature channels, respectively.

The operation of the receiver in the tracking mode of the clock frequency of the received information signal. Tracking the clock frequency by the information signal starts from the moment the output of CM (61) is connected, in which information about the magnitude and sign of the clock frequency mismatch is generated, to the input of the phase sensing input (53).

The process of generating a signal about the magnitude of the mismatch of clock frequencies for the received information signal is as follows.

The first input of Sm2 (54) from the seventh output of CVI (67) receives the resulting sequence of the form П02, and from the eighth output of CVI (67) to the first input of Sm2 (55) the resulting sequence of the form П01. The second inputs of Sm2 (54) and (55) from the output of the UTG (51) receive a sequence of clock pulses. The results of addition in Cm2 (54) and (55) (we denote the results of addition as the sequences П02 _t and П01 _t, respectively) from their outputs go to the third inputs of the corresponding CC CC (58) and (57). The first inputs of the CC CC (57) and (58) receive a video signal of the form (23) and a noise component of the form (26) (common mode channel), and the second inputs of the CC CC (57) and (58) receive a video signal of the form (29) and noise component of the form (32) (quadrature channel). In CC CC (57) and (58), the signals received at their inputs are convolved and signals that carry information about the time offset of the clock frequencies of the received and reference signals appear at their outputs. An implementation option for CC PM (57), (58) and a description of the principle of their operation are presented in [2].

The signals from the outputs of the CC CC (57), (58) are fed to the corresponding first inputs P (59) and (60), the second inputs of which receive signals from the ninth and tenth outputs of the CVI (67), respectively. In the multipliers (59) and (60), the information component is removed from the signals received at their first inputs, i.e. the influence of the transmitted information on the estimation of the delay τ is excluded. Further, the signals from the outputs of the multipliers (59) and (60) are supplied to the first and second inputs of Cm (61), respectively, in which the resulting error signal is generated, proportional to the value of the time mismatch of the clock frequencies of the received and reference signals.

In the proposed clock tracking scheme, there are no losses in the signal-to-noise ratio, i.e. This tracking scheme is optimal [2].

The operation of the receiver in the tracking mode of the carrier frequency. The process of generating a signal about the magnitude of the mismatch between the carrier and the reference frequency occurs as follows.

The signal from the output of the PLL (19) (common mode channel) is fed to the first input of the inverter (5), and the output of the PLL (33) (quadrature channel) is fed to the first input of the inverter (15). At the second inputs of the inverter (5) and inverter (15), a signal is output from the exhaust gas (17). Moreover, to the second input of the inverter (5) directly, and to the second input of the inverter (15) - through the PV (16).

In IF (5) and (15) as a result of multiplying the signals received at their inputs, components of the total and difference frequencies of the signal and noise appear at their outputs.

The components of the total frequency of the signal and noise are suppressed by the LPF (6) and (14), and the components of the difference frequency (video signal) pass through the LPF (6) and (14) and are fed to the ADC inputs (7) and (13), respectively, in which the video signal digitized.

The above transformations can be analytically represented as follows.

The signal component at the inverter output (5) s _output5 (t) (common mode channel) in general can be represented as

and taking into account expressions (8) and (13), as well as the condition that ω _σ = ω _pr, expression (37) takes the form

A signal of the form (38) is fed to the input of the LPF (6), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the LPF (6) at its output, the signal component will have the form

The noise component at the inverter output (5) n _output5 (t) (common mode channel) in general can be represented as

Taking into account expressions (8) and (14), as well as the condition that ω _og = ω _pr expression (40) takes the form

A signal of the form (41) is fed to the input of the LPF (6), and after transformations to the LPF (6), the noise component at its output will have the form

The signal component at the inverter output (15) s _out15 (t) (quadrature channel) in general can be represented as

and taking into account expressions (7), (15), as well as the condition that ω _og = ω _pr expression (43) will take the form

A signal of the form (44) is fed to the input of the LPF (14), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the CPSF (14), at its output, the signal component will have the form

The noise component at the inverter output (15) n _o15 (t) (quadrature channel) in general can be represented as

Taking into account expressions (7) and (16), as well as the condition that ω _og = ω _pr expression (46) will take

A signal of the form (47) is fed to the input of the LPF (14), and after transformations to the LPF (14), the noise component at its output will have the form

From the output of the ADC (13), the video signal is digitally fed to the first inputs of the QC LF (8) and (12), and from the output of the ADC (7) - to the second inputs of the QC LF (8) and (12).

At the third input of the QC LF (8) from the eighth output of the CVI (67), the resulting sequence P01 is received, and at the third input of the QC LF (12) from the seventh output of the CVI (67), the resulting sequence 7702 is received.

In CC LF (8) and (12), a convolution of the signals received at their inputs is carried out and signals appear on their outputs that carry information about the size of the mismatch between the received carrier and reference frequencies, and which have the form [2]:

From the output of the QC LF (8), a signal of the form (49) is supplied to the first input P (9). The second input P (9) receives a signal from the ninth output of the CVI (67), which compensates for the influence of the information component on the estimate of the magnitude of the signal about the mismatch between the carrier and the reference frequencies, and then the signal at the output P (9) will have the form

From the output of the QC LF (12), a signal of the form (50) is supplied to the first input P (11). The second input P (11) receives a signal from the tenth output of the CVI (67), which compensates for the influence of the information component on the estimate of the magnitude of the signal about the mismatch between the carrier and the reference frequencies, and then the signal at the output P (11) will have the form

A signal of the form (51) from the output P (9) goes to the first input of Cm (10), and a signal of the form (52) to the second input of Cm (10). The signal at the output of Sm (10) will have the form

A signal of the form (53) from the output of Sm (10) goes to the input of the phase error filter (4) and after filtering the signal in it, the resulting error voltage from its output through the control element (3) goes to the input of the UG (2), closing the tracking loop after the carrier frequency, and changes its frequency in such a way as to eliminate the existing phase error of the frequency of the input signal relative to the frequency of the reference oscillator.

An implementation option of the CC LF (8) and (12) and a description of the principle of their operation are presented in [2].

Using expression (53), we estimate the ratio of signal power and noise at the input of the FFO (4) at the maximum allowable phase difference between the received and reference signals, i.e. for ϕ = ± π / 2

It follows from expression (54) that in the carrier tracking circuit there is an optimal filtering of the carrier frequency with an increase in the signal power by a factor of N.

The operation of the receiver in the mode of repeated detection of a signal in case of failure of synchronization. The main element of the receiver, which provides the process of re-detecting the signal and establishing synchronization, is the USER (76), which is presented in FIG. 2. The UPOS (76) is transferred to the operating state by the first pulse arriving at its first input from the output of the control unit (62) (that is, after the synchronization process has been established by the clock and carrier frequencies and the selection of information in the channels has begun).

We consider the operation of the UPOS (76) according to the structural diagrams presented in FIG. 1 and FIG. 2.

Each pulse arriving at the first input of the safety control device (76) and, therefore, at the first input of the high-frequency converter (2) set its cells to state “1” (that is, the maximum number is recorded in the counter).

To the second input of the UPOS (76), and, therefore, to the second input of the VSh (2) (through the PM (1)), clock pulses from the output of the UTG (51) are received. Upon receipt of each clock pulse, the number recorded in the counter decreases by one. The introduction of a frequency divider in the UPRO reduces the requirements for the circuit implementation of the HF (2).

на первый вход УПОС (76) не поступит ни один импульс (это значит, что система вышла из синхронизма), то тактовые импульсы, поступающие на второй вход ВСч (2) с выхода УТГ (51), установят ячейки счетчика в состояние (определенная комбинация «1» и «0» в ячейках счетчика), на которую настроен дешифратор (3). При появлении этой комбинации в счетчике на выходе Дш (3) а, следовательно, и на выходе УПОС (76) (пройдя через инвертор (4)) появляется отрицательный импульс, который, поступает на вторые входы ЭК (43), (50) и (56). При этом ЭК (43) и (50) открываются, а ЭК (56)закрывается. Таким образом приемное устройство переведено в режим повторного обнаружения сигнала. Работа приемника в режиме обнаружения сигнала описана выше.If in the time interval

not a single pulse arrives at the first input of the UOS (76) (this means that the system is out of synchronism), then the clock pulses arriving at the second input of the VSh (2) from the output of the UTG (51) will set the counter cells to the state (a certain combination “1” and “0” in the counter cells), on which the decoder (3) is configured. When this combination appears in the counter at the output Дш (3) and, consequently, at the output of the УСОС (76) (passing through the inverter (4)), a negative pulse appears, which goes to the second inputs of the EC (43), (50) and (56). In this case, EC (43) and (50) open, and EC (56) closes. Thus, the receiving device is switched to the mode of re-detection of the signal. The operation of the receiver in signal detection mode is described above.

The operation of the device in the mode of ensuring high structural secrecy during the period of long-term operation. High structural secrecy of the transmitted signals in the proposed device is ensured by the introduction of its circuit KU (73), (74) and (75). KU (74) and (75) are a connecting connector with L inputs and K outputs (see Fig. 3a), with L> K, and patch pads that provide switching inputs of the connecting connector with its corresponding outputs (see Fig. 3b and 3c), and KU (73) is a connecting connector with I inputs and one output (see Fig. 3d) and a connection block that provides switching of the corresponding input of the connecting connector with its output (see Fig. 3d).

High structural secrecy of the transmitted signals during the period of long-term operation is achieved by periodically changing the switching blocks in the switching devices (73), (74) and (75), due to which the operational switching of the GKOKP outputs (46) with the 3rd and 4th inputs of all KVI is carried out (using KU (74) and (75)) and outputs of GMOKP (47) with 5th inputs of all KVI (using KU (73)).

Each switchgear is equipped with several connection blocks. Their number and the period of use of each block depends on the duration of the operation of the system and the performance of the information processing facilities.

A comparative assessment of the structural secrecy of the signals in the inventive device and in the prototype. A comparative assessment of the structural secrecy of the signals used in the inventive device and prototype, we will carry out by assessing the capabilities of third parties to disclose the structure of the transmitted signals. It is known that high structural secrecy depends on the size of the ensemble of signals used, the operating time of the system, and the performance of the means for processing intercepted information.

When comparing the structural secrecy of the claimed device and prototype, we will proceed from the following conditions:

1. The size of the ensemble of nonlinear code sequences generated by the SOC of devices A ₁ and A ₂ is the same and when the size of the SOCC registers m = 6 is 2 ²⁶ [4, p. thirty]).

2. In each channel of the devices there are two nonlinear orthogonal code sequences A ₁ and A ₂ .

3. To reveal the structure of any nonlinear code sequence 2 ^m long, it is necessary to determine all 2 ^m elements of this sequence.

4. The number of operations A for revealing the structure of two non-linear sequences of the orthogonal code of one channel with a bit width of the register of the generator of non-linear orthogonal codes m = 6 will be

A = A ₁ * A ₂ * 2 ^m = 2 ²⁶ * 2 ²⁶ * 2 ⁶ = 2 ⁵⁸ ≈10 ¹⁷ .

5. The productivity of the means of processing the intercepted information P is 10 ⁹ ... 10 ¹⁰ operations per second [5].

From the above conditions it follows that for the disclosure of the structure of non-linear sequences of the orthogonal code of one device channel (prototype and the claimed device), a time interval ΔT = A / P = 10 ¹⁷ / (10 ⁹ ... 10 ¹⁰ ) = (10 ⁸ ... 10 ⁷ ) is required seconds, which corresponds to a time interval from 3 years to 3 months.

Therefore, after a calculated period of time ΔT, a third party is able to control the transmitted information in the prototype device, and in the inventive device due to the change of wiring pads in KU (48), (49) and (50) he does not have such an opportunity, since in the controlled his channel uses another pair of nonlinear orthogonal code sequences and the process of disclosing the structure of the transmitted signals to him begins from the very beginning.

Thus, due to the periodic change of switching blocks in the KU (48), (49) and (50) in the inventive device provides a high structural secrecy of the transmitted signals during long-term operation.

Literature.

1. Patent for invention No. 2494550, priority of the invention 12/19/2011, published: 09/27/2013, Bull. Number 27.

2. Patent No. 2544767, priority of the invention on November 8, 2013, published: March 20, 2015, Bull. No. 8 (prototype).

3. Patent No. 2553055, priority of the invention 07.07.2014, published: 06/10/2015, Bull. No. 16.

4. Interference immunity of radio systems with complex signals / Ed. G.I. Tuzova - M .: Radio and communications, 1985 .-- 264 p. (p. 29).

5. Voevodin VV Supercomputers: yesterday, today, tomorrow // Science and Life, 2000, No. 5, p. 76-83.

Claims (2)

1. A multi-channel code division receiver for receiving quadrature modulated signals of increased structural secrecy, which includes K information extraction channels, where K takes values from 1 to N-1, and N = 2 ⁿ for n≥1, one of which are allocated for synchronization of the receiver, each channel for selecting information includes a series-connected first quadrature correlator of a channel for extracting information, a first integrator and a first comparator, as well as a series-connected second quadrature the information allocation channel correlator, the second integrator and the second comparator, the first inputs of the first and second quadrature information extraction channel correlators are combined and are the first input of the k-th information extraction channel, where k takes values from 1 to K, the second inputs of the first and second quadrature channel correlators information extraction is combined and is the second input of the k-th information extraction channel, the output of the first comparator is connected to the first input of the decoder and is the first and ninth outputs of the inf formations, the output of the second comparator is connected to the second input of the decoder and is the second and tenth outputs of the information extraction channel, the first output of the decoder is the third output of the information extraction channel, the second output of the decoder is the fourth output of the information extraction channel, the output of the first quadrature correlator of the information extraction channel is the fifth output information extraction channel, the output of the second quadrature correlator of the information extraction channel is the sixth output of the information extraction channel, second the first inputs of the first and second integrator and the third input of the decoder are combined and are the seventh input of the information extraction channel, the fourth input of the decoder is the sixth input of the information extraction channel, the output of the first adder modulo two is connected to the third input of the first quadrature correlator of the information extraction channel and is the eighth channel output information extraction, the output of the second adder modulo two is connected to the third input of the second quadrature correlator of the information extraction channel and is the seventh output the channel of the information extraction channel, the first input of the first adder modulo two is the third input of the information extraction channel, the first input of the second adder modulo two is the fourth input of the information extraction channel, the second inputs of the first and second adders modulo two are combined and are the fifth input of the information extraction channel as well as series-connected the first intermediate frequency filter, the input of which is connected to the output of the first frequency converter, the third frequency converter, the first wide a low-pass filter and a first analog-to-digital converter connected in series to a second intermediate-frequency filter, the input of which is connected to the output of the second frequency converter, a fourth frequency converter, a second broadband low-pass filter and a second analog-to-digital converter, connected in series to the fifth frequency converter, the first the input of which is connected to the output of the first intermediate-frequency filter, the third broadband low-pass filter, the third analog-to-digital conversion an alternator connected in series with a sixth frequency converter, the first input of which is connected to the output of the second intermediate-frequency filter, the fourth broadband low-pass filter and the fourth analog-to-digital converter, the second inputs of the fourth and fifth frequency converters being combined and connected through the second phase shifter to π / 2 with the output of the reference generator, the second inputs of the third and sixth frequency converters are combined and connected to the output of the reference generator, connected in series the first quadrature correlator of the carrier frequency tracking circuit and the first multiplier, the output of which is connected to the first input of the first adder, the second quadrature correlator of the carrier frequency tracking circuit and the second multiplier, the output of which is connected to the second input of the first adder, the second input of the first multiplier is connected to The 9th output of the channel selection information allocated for synchronization of the receiver, and the second input of the second multiplier is connected to the 10th output of the channel selection information allocated for synchronization of the receiver, the output of the first adder is connected to the phase error filter input, the first inputs of the first and second quadrature correlators of the carrier frequency tracking circuit are combined and connected to the output of the fourth analog-to-digital converter, the second inputs of the first and second quadrature correlators of the carrier frequency tracking circuit combined and connected to the output of the third analog-to-digital converter, the third input of the first quadrature correlator of the carrier frequency tracking circuit is connected to the eighth output of the information extraction channel dedicated to synchronizing the receiver, the third input of the second quadrature correlator of the carrier frequency tracking circuit is connected to the seventh output of the information isolation channel allocated to the receiver synchronization, the first inputs of all information isolation channels, as well as the first inputs of the first and second correlators of the circuit clock tracking combined and connected to the output of the first analog-to-digital Converter, the second inputs of all channels of information allocation, as well as the second the inputs of the first and second correlators of the clock tracking circuit are combined and connected to the output of the second analog-to-digital converter, the output of the first correlator of the clock tracking circuit is connected to the first input of the third multiplier, and the output of the second clock tracking correlator is connected to the first input of the fourth multiplier, the fifth output of the channel for selecting information allocated for synchronization of the receiver, through the first quadrator is connected to the first input of the second adder, and the sixth output to the information extraction channel allocated for synchronization of the receiver through the second quadrator is connected to the second input of the second adder, the output of which through the third integrator is connected to the input of the first threshold device, the ninth output of the channel for selecting information allocated for synchronization of the receiver is connected to the second input of the third multiplier, output which is connected to the first input of the third adder, and the tenth output of the channel for selecting information allocated for synchronization of the receiver is connected to the second input of the fourth the second multiplier, the output of which is connected to the second input of the third adder, the output of the third adder through the first electronic key is connected to the input of the error filter by delay, as well as the fifth multiplier and the fifth broadband low-pass filter connected in series, the output of which is connected to the first input of the fourth adder, in series connected by a sixth multiplier and a sixth broadband low-pass filter, the output of which is connected to the second input of the fourth adder, the first and second inputs of the fifth the multiplier are combined and connected to the output of the first intermediate frequency filter, the first and second inputs of the sixth multiplier are combined and connected to the output of the second intermediate frequency filter, a matched filter in series, a third quadrator, a third electronic key and a second threshold device, a third modulo-two adder connected in series , the seventh multiplier and the second electronic key, the output of which is connected to the input of the delay error filter, the output of the fourth adder is connected to the input matched filter and with the second input of the seventh multiplier, the output of the matched filter is connected to the input of the first inverter and the first input of the fourth electronic key, the output of the first inverter is connected to the first input of the fifth electronic key, the output of which is connected to the input of the second inverter, the outputs of the second inverter and fourth electronic the keys are combined and connected to the first input of the third adder modulo two, the output of the controlled clock is connected to the second input of the third adder modulo two, also with the second inputs of the fourth and fifth adders modulo two, the seventh output of the channel for extracting information allocated for synchronizing the receiver is connected to the first input of the fourth adder modulo two, the output of which is connected to the third input of the second correlator of the clock tracking circuit, the eighth channel output extracting information allocated for receiver synchronization is connected to the first input of the fifth adder modulo two, the output of which is connected to the third input of the first correlator of the cycle tracking circuit the first frequency element, the phase error filter, the first control element and the controlled generator, the output of which through the first phase shifter is connected to the second input of the second frequency converter, the second input of the first frequency converter is connected to the output of the controlled generator, the first inputs of the first and second frequency converters are combined and are the input of the device, as well as a series-connected delay error filter, a second control element, a controlled clock generator, distinguishing I mean that the receiver circuitry additionally includes: a generator of a masking orthogonal code sequence, the first input of which is connected to the output of the second threshold device, the second input of a generator of a masking orthogonal code sequence is connected to the output of a controlled clock generator, the ith output of the generator of a masking orthogonal code sequence is connected with the i-th input of the first switching device, where i takes values from 1 to I (I can take values 2, 3, ...), (I + 1) -th output generator masking an orthogonal code sequence is connected to six inputs of the combined allocation information channel, generator channel orthogonal code sequences, a first input coupled to an output of the second threshold device, the second input of the generator channel orthogonal code sequences managed connected to the output of the clock generator,

the output of the channel orthogonal code sequence generator is connected to

the inputs of the second and third switching devices, where

takes values from 1 to L, the (L + 1) -th output of the channel orthogonal code sequence generator is connected to the combined seventh inputs of all information extraction channels and to the second input of the third integrator, the (L + 2) -th output of the channel orthogonal code sequence generator is connected with the combined second inputs of the fourth and fifth electronic keys, the output of the first switching device is connected to the combined fifth inputs of all channels of information allocation, the k-th output of the second switching device connected to the third input of the k-th channel of information extraction, where k takes values from 1 to K, the k-th output of the third switching device is connected to the fourth input of the k-th channel of information extraction, and L> K, as well as a signal re-detection device and decoupling element, wherein the output of the first threshold device is connected to the first input of the signal re-detection device, and through the decoupling element - to the second inputs of the first, second and third electronic keys, the second input of the signal re-detection device is union of a yield managed clock generator, the output signal re-detection device is connected to the combined second inputs of the first, second and third electronic switches. 2. The device according to claim 1, characterized in that the signal re-detection device includes a subtracting counter, the first input of which is the first input of the signal re-detection device, and its second input is connected to the output of the frequency divider, the input of which is the second input of the device signal detection, the i-th output of the subtracting counter is connected to the i-th input of the decoder, where i takes values from 1 to m, and m is the number of bits of the subtracting counter, the output of the decoder is connected to the input of the inverter, the output of which It is the output of the repeated signal detecting apparatus.

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