RU2544767C1 - Multichannel code division receiver for receiving quadrature-modulated high structural concealment signals - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: device comprises K information selection channels, two π/2 phase changers, a controlled generator, two control elements, a phase error filter, six frequency converters, six broadband low-pass filters, four analogue-to-digital converters, a reference generator, two quadrature correlators of a carrier frequency monitoring circuit, seven multipliers, four adders, two intermediate frequency filters, three integrators, a matched filter, five electronic switches, three squaring devices, two threshold devices, a controlled clock generator, a delay error filter, two quadrature correlators of a clock frequency monitoring circuit, five half adders, a channel orthogonal code sequence generator, a masking orthogonal code sequence generator, all units connected to each other by corresponding connections.

EFFECT: reliable reception of quadrature-modulated high structural concealment signals.

4 cl, 6 dwg

Description

The invention relates to the field of information transmission by means of electromagnetic waves and can be used in cellular, wireless and satellite radio communication systems, telemetry, in radio control systems, etc., designed to function under electronic warfare conditions (i.e., under the conditions of organized interference , extraneous interference in the operation of systems for intercepting information and imposing false information).

One of the main requirements for advanced communication systems is the requirement to use signals with high structural secrecy in them, which makes it difficult for the opposing side to create effective interference (interference similar to a signal) to suppress these systems, as well as protect these communication systems from outside interference in order to intercept information or impose false information.

Cellular and satellite communication systems using pseudo-random signals are known, namely: IS-95 standard mobile cellular communication system based on code division multiple access (CDMA) technology, (in foreign terminology - CDMA); Globalstar satellite communications system (USA), SAT-CDMA (South Korea), SW-CDMA (European Space Agency-ESA) [1], CDMA-2000, WCDMA, HDPA standard CDMA systems, as well as a device [ 2], which have the following disadvantages:

the period of code sequences that determines the speed of information transfer has a short duration, which negatively affects the noise immunity of communication channels;

the many pseudo-random signals used are determined by linear code sequences whose ensemble is limited;

there is an explicit synchronization signal corresponding to one of the used code sequences;

the insignificant length of the used code sequences and their insignificant ensemble does not solve the problems of ensuring the required structural secrecy of the signals used;

To synchronize the system, a pilot signal is used, transmitted simultaneously with the information, which determines its availability for opening by an outside observer. Thus, all of these analogues are characterized by low structural secrecy of the signals used.

[3], где n - разрядность регистра сдвига, формирующего нелинейную кодовую последовательность из ансамбля полных кодовых колец. Тогда, при n=6 имеем

, а это уже внушительная величина.One of the promising directions for increasing the structural secrecy of signals is the use of non-linear code sequences for their formation, the ensemble volume of which is estimated as

[3], where n is the width of the shift register forming a nonlinear code sequence from an ensemble of complete code rings. Then, for n = 6, we have

, and this is an impressive amount.

Known methods and principles [3, 4], which allow generating signals with increased structural secrecy, which is achieved through the use of non-linear code orthogonal sequences from an ensemble of full code rings when generating them.

However, there are no devices that can ensure reliable reception of such signals.

Closest to the proposed invention is a device [2] (prototype), which includes a series-connected first frequency converter, a first broadband low-pass filter, a first analog-to-digital converter, serially connected a second frequency converter, a second wide-band low-pass filter, a second analog -digital converter, the first inputs of the first and second frequency converters are combined and are the input of the device, as well as series-connected filters tr phase error, the first control element and a controlled generator, the output of which is connected through a phase shifter to the second input of the second frequency converter, the second input of the first frequency converter is connected to the output of the controlled generator, a low-pass filter and a decoder connected in series, the output of which is the output of the receiver, the first output the first quadrature correlator is connected to the input of the low-pass filter, the second output of the first quadrature correlator is connected to the input of the phase error filter, in the output of the first analog-to-digital converter is connected to the second input of the first quadrature correlator, the output of the second analog-to-digital converter is connected to the first input of the first quadrature correlator, a digital adder, a delay error filter, a second control element, a controlled clock and a reference signal generator, the first input of the digital adder is connected to the second output of the second quadrature correlator, the second input of the digital adder is connected to the second output of of this quadrature correlator, the first and second inputs of the second quadrature correlator are combined and connected to the output of the first analog-to-digital converter, the first and second inputs of the third quadrature correlator are combined and connected to the output of the second analog-to-digital converter, the first output of the reference signal generator is connected to the fourth input of the second quadrature correlator, the second output of the reference signal generator is connected to the third input of the first quadrature correlator and the fourth input of the third adraturnogo correlator, a third reference signal generator output is connected to a fourth input of the first quadrature correlator and a third input of the second quadrature correlator and the fourth reference signal generator output connected to the third input of the third quadrature correlator.

The aim of the present invention is to develop a multichannel device that allows for reliable reception of quadrature modulated signals of increased structural secrecy.

This goal is achieved by the fact that in the known device, which includes a series-connected first frequency converter, a first broadband low-pass filter, a first analog-to-digital converter, serially connected a second frequency converter, a second wide-band low-pass filter, a second analog-to-digital converter, the first the inputs of the first and second frequency converters are combined and are the input of the device, as well as the phase error filter connected in series, the first control the main element and the controlled generator, the output of which is connected through the first phase shifter to the second input of the second frequency converter, the second input of the first frequency converter is connected to the output of the controlled generator, the low-pass filter and the decoder connected in series, the output of which is the output of the receiver, the first output of the first quadrature correlator is connected with the input of the low-pass filter, the second output of the first quadrature correlator is connected to the input of the phase error filter, the output of the first analog a digital converter is connected to the second input of the first quadrature correlator, the output of the second analog-to-digital converter is connected to the first input of the first quadrature correlator, a digital adder connected in series, a delay error filter, a second control element, a controlled clock and a reference signal generator, the first input of a digital adder connected to the second output of the second quadrature correlator, the second input of the digital adder is connected to the second output of the third quadrature the correlator, the first and second inputs of the second quadrature correlator are combined and connected to the output of the first analog-to-digital converter, the first and second inputs of the third quadrature correlator are combined and connected to the output of the second analog-to-digital converter, the first output of the reference signal generator is connected to the fourth input of the second quadrature correlator , the second output of the reference signal generator is connected to the third input of the first quadrature correlator and the fourth input of the third quadrature correlate pa, the third reference signal generator output connected to a fourth input of the first quadrature correlator and a third input of the second quadrature correlator and the fourth reference signal generator output is connected to a third input of the third quadrature correlator, following changes in the scheme:

excluded from the scheme: quadrature correlators, a low-pass filter, a decoder, a digital adder, a reference signal generator, a first broadband low-pass filter, a first analog-to-digital converter, a second broadband low-pass filter and a second analog-to-digital converter, and are additionally introduced into the device circuit : K channels of information extraction (K takes values from 1 to N-1, and N = 2 ⁿ for n≥1), one of which is allocated for synchronization of the receiver, and each channel of information extraction includes sequentially connected the first quadrature correlator of the information extraction channel, the first integrator and the first comparator, as well as sequentially connected the second quadrature correlator of the information extraction channel, the second integrator and the second comparator, the first inputs of the first and second quadrature correlators of the information extraction channel are combined and are the first input of the k-th channel information extraction, where k takes values from 1 to K, the second inputs of the first and second quadrature correlators of the information extraction channel are combined and explicit are the second input of the k-th information extraction channel, the output of the first comparator is connected to the first input of the decoder and is the first and ninth outputs of the information extraction channel, the output of the second comparator is connected to the second input of the decoder and is the second and tenth outputs of the information extraction channel, the first output of the decoder is the third output of the information extraction channel, the second output of the decoder is the fourth output of the information extraction channel, the output of the first quadrature correlator of the information extraction channel is the fifth output of the information extraction channel, the output of the second quadrature correlator of the information extraction channel is the sixth output of the information extraction channel, the second inputs of the first and second integrator and the third input of the decoder are combined and are the seventh input of the information extraction channel, the fourth input of the decoder is the sixth input of the information extraction channel, the output of the first adder modulo two is connected to the third input of the first quadrature correlator channel information allocation and is the eighth output channel information extraction, the output of the second adder modulo two is connected to the third input of the second quadrature correlator of the information extraction channel and is the seventh output of the information extraction channel, the first input of the first adder modulo two is the third input of the information allocation channel, the first input of the second adder modulo two is the fourth the input of the channel for selecting information, the second inputs of the first and second adders modulo two are combined and are the fifth input of the channel for selecting information, as well as the first intermediate frequency filter, the input of which is connected to the output of the first frequency converter, the third frequency converter, the first broadband low-pass filter and the first analog-to-digital converter, the second intermediate filter, the input of which is connected to the output of the second frequency converter, the fourth converter frequency, a second broadband low-pass filter and a second analog-to-digital converter, connected in series to the fifth conversion frequency generator, the first input of which is connected to the output of the first intermediate-frequency filter, the third wide-band low-pass filter, the third analog-to-digital converter, the sixth frequency converter, the first input of which is connected to the output of the second intermediate-frequency filter, the fourth wide-band low-pass filter and the fourth an analog-to-digital converter, the second inputs of the fourth and fifth frequency converters being combined and connected through the second phase shifter to π / 2 the output of the reference generator, the second inputs of the third and sixth frequency converters are combined and connected to the output of the reference generator, the first quadrature correlator of the tracking chain for the carrier frequency and the first multiplier, the output of which is connected to the first input of the first adder, the second quadrature correlator of the tracking chain in series carrier frequency and a second multiplier, the output of which is connected to the second input of the first adder, the second input of the first multiplier is connected n with the 9th output of the channel for extracting information allocated for synchronizing the receiver, and the second input of the second multiplier is connected to the 10th output of the channel for extracting information allocated for synchronizing the receiver, the output of the first adder is connected to the input of the phase error filter, the first inputs of the first and second carrier frequency tracking quadrature correlators are combined and connected to the output of the fourth analog-to-digital converter, second inputs of the first and second carrier hour tracking quadrature correlators the totals are combined and connected to the output of the third analog-to-digital converter, the third input of the first quadrature correlator of the carrier frequency tracking circuit is connected to the eighth output of the information allocation channel dedicated to synchronize the receiver, the third input of the second quadrature correlator of the carrier frequency tracking circuit is connected to the seventh channel output allocation of information allocated for receiver synchronization, the first inputs of all channels of information extraction, as well as the first inputs of the first and second correlator clock tracking circuits are combined and connected to the output of the first analog-to-digital converter, the second inputs of all information extraction channels, as well as second inputs of the first and second correlators, clock tracking circuits are combined and connected to the output of the second analog-to-digital converter, the output of the first correlator the clock tracking circuit is connected to the first input of the third multiplier, and the output of the second correlator the clock tracking circuit is connected to the first input of the fourth scissors, the third input of the k-th channel of information extraction is connected to the i-th output of the channel orthogonal code sequence generator, where i takes the value k, the fourth input of the k-th channel of information extraction is connected to the j-th output of the channel orthogonal code sequence generator, where j takes the value (K-k + 1), and i ≠ j, if i = j, then j = k + 1, the fifth inputs of all channels of information extraction are combined and connected to the first output of the masking orthogonal code sequence generator, the sixth inputs of all channels information extraction is combined and connected to the second output of the masking orthogonal code sequence generator, the (K + 1) -th output of the channel orthogonal code sequence generator is connected to the seventh inputs of all information extraction channels and to the second input of the third integrator, the fifth output of the information extraction channel allocated for synchronization of the receiver, through the first quadrator is connected to the first input of the second adder, and the sixth output of the channel allocation information allocated for synchronization with Mnika, through the second quadrator is connected to the second input of the second adder, the output of which through the third integrator and the first threshold device is connected to the combined second inputs of the first, second and third electronic keys, the ninth output of the information isolation channel dedicated to synchronize the receiver is connected to the second input of the third a multiplier, the output of which is connected to the first input of the third adder, and the tenth output of the channel for selecting information allocated for synchronization of the receiver is connected to the second input the fourth multiplier, the output of which is connected to the second input of the third adder, the output of the third adder through the first electronic key is connected to the input of the error filter by delay, as well as the fifth multiplier and the fifth broadband low-pass filter connected in series, the output of which is connected to the first input of the fourth adder, in series connected by the sixth multiplier and the sixth broadband low-pass filter, the output of which is connected to the second input of the fourth adder, the first and second inputs of the fifth of the second multiplier are combined and connected to the output of the first intermediate frequency filter, the first and second inputs of the sixth multiplier are combined and connected to the output of the second intermediate frequency filter, the matched filter and the third quadrature connected in series, the output of which is connected through the third electronic key to the input of the second threshold device, the output which is connected to the combined first inputs of the generator of channel orthogonal code sequences and the generator of the masking orthogonal code of the first sequence, the output of the matched filter is connected to the input of the first inverter and to the first input of the fourth electronic key, the output of the first inverter is connected to the first input of the fifth electronic key, the output of which is connected to the input of the second inverter, the outputs of the second inverter and fourth electronic key are combined and connected to the first the input of the third adder is modulo two, the output of the fourth adder is connected to the input of the matched filter and to the second input of the seventh multiplier, connected in series to this adder modulo two, the seventh multiplier and the second electronic key, the output of which is connected to the input of the delay error filter, the (K + 2) -th output of the channel orthogonal code sequence generator is connected to the combined second inputs of the fourth and fifth electronic keys, the output of a controlled clock the generator is connected to the second inputs of the third adder modulo two, the generator of channel orthogonal code sequences, the generator of the masking orthogonal code sequence, and about the second inputs of the fourth and fifth adders modulo two, the seventh output of the information allocation channel dedicated to synchronize the receiver is connected to the first input of the fourth adder modulo two, the output of which is connected to the third input of the second correlator of the clock tracking circuit, the eighth output of the allocation channel information allocated for receiver synchronization is connected to the first input of the fifth adder modulo two, the output of which is connected to the third input of the first correlator of the clock tracking circuit often that one.

Distinctive features of the proposed device are new elements introduced into the receiver circuit, namely: K channels for extracting information, two phase shifters per π / 2, a controlled oscillator, two control elements, a phase error filter, six frequency converters, six broadband low-pass filters, four analog -digital converters, reference generator, two quadrature correlators of the carrier frequency tracking circuit, seven multipliers, four adders, two intermediate-frequency filters, three integrators, according to A plug-in filter, five electronic keys, three quadrants, two threshold devices, a controlled clock generator, a delay error filter, two quadrature correlators for the clock tracking circuit, five adders modulo two, a channel orthogonal code sequence generator, a masking orthogonal code sequence generator, and the corresponding connections between them, due to which it was possible to ensure reliable reception of quadrature modulated signals of increased structural secrecy.

Since the totality of the introduced elements and their relationship to the filing date of the application in the patent and scientific literature are not found, the proposed technical solution corresponds to the "inventive step".

The structural diagram of the inventive device is presented in figure 1 and figure 2. In order to simplify the circuit, figure 1 shows only one k-th (k = 1) channel for information extraction, as well as elements that ensure the functioning of the device and allow to explain its operation as a whole. In figure 1, the numbers denote:

1, 16 - phase shifter on π / 2 (PV);

2 - controlled generator (UG);

3, 52 - control element (RE);

4 - phase error filter (FFO);

5, 15, 18, 20, 32, 34 - frequency converter (IF);

6, 14, 21, 31, 37, 39 — broadband low-pass filter (CFC);

7, 13, 22, 30 - analog-to-digital converter (ADC);

8, 12 — quadrature correlator of a chain for tracking the carrier frequency (QF LF);

9, 11, 38, 40, 49, 59, 60 - multiplier (P);

10, 36, 61, 64 - adder (cm);

17 - reference generator (OG);

19, 33 - intermediate frequency filter (FPC);

23, 29 - quadrature correlator of the channel for the allocation of information (KK KVI);

24, 28, 63 - integrator (Int.);

25, 27 - comparator (KM);

26 - decoder (DK);

35 - matched filter (SF);

41, 42, 48, 54, 55 - adder modulo two (cm2);

43, 50, 56, 69, 70 - electronic key (EC);

45, 65, 66 - quadrator (KB);

46 - channel orthogonal code sequence generator (GKOKP);

47 - generator masking orthogonal code sequence (GMOKP);

51 - controlled clock (UTG);

53 - delay error filter (FDF);

57, 58 — quadrature correlator of a clock tracking chain (CC PM);

44, 62 - threshold device (PU);

67, 68 - channel information allocation (CVI);

71, 72 - inverter (Inv.).

On figa shows a quadrature correlator KVI. The numbers in figa indicated:

1, 4 - multiplier (P);

2, 5 - digital low-pass filter (DSP);

3 - adder (cm);

6 - inverter (Inv.).

Figure 2b shows a quadrature correlator of the tracking frequency tracking chain. The numbers in FIG. 2b indicate:

1, 5 - multiplier (P);

2, 6 - digital low-pass filter (DSP);

3 - adder (cm);

4 - delay line (LZ).

On figv shows a quadrature correlator circuit tracking the clock frequency. The numbers in FIG. 2c indicate:

1, 5 - multiplier (P);

2, 6 - digital low-pass filter (DSP);

3 - adder (cm).

4 - delay line (LZ);

7 - inverter (Inv.).

The work of the receiver. The operation of the receiver will consider the structural diagrams, which are shown in figure 1, figure 2 and figure 3.

When considering the operation of the receiver, we will proceed from the following:

1. At the input of the receiving device receives an additive mixture of signal and noise of the form

where s (t) is the group signal actually received by the receiver;

n (t) is the noise at the input of the receiver.

The received signal at the input of the K-channel receiver is presented in the form:

where A is the signal amplitude;

ω _o - carrier angular frequency of the signal;

t is the current time;

_{П1 lki} - the i-th channel orthogonal code sequence in the in-phase k-th KVI on the l-th time interval;

P2 _lkj - j-th channel orthogonal code sequence in quadrature k-th KVI on the l-th time interval;

k is the number of CVI, k takes values from 1 to K, and K takes values from 1 to N-1, a N = 2 ⁿ for n≥1;

i is the number of the channel orthogonal code sequence from the ensemble of sequences generated by GKKP (46), let i = k;

j is the number of the channel orthogonal code sequence from the ensemble of sequences generated by GKKP (46), let j = K-k + 1;

l is the duration of the channel orthogonal code sequence generated by GKKP (46), equal to the duration of the information symbol;

P0 is the masking orthogonal code sequence generated by GMOCP (47), at the same time performs the function of cyclic synchronization, and its duration L is a multiple of the duration of the channel orthogonal code sequence generated by GKOKP (46), i.e. L = ml, where m is the number of channel orthogonal code sequences that fit on the interval of the masking orthogonal code sequence;

П0 _l - a fragment of a masking orthogonal code sequence generated by GMOKP (47), in the interval l;

θ1 _lk is the phase of the signal in the in-phase k-th CVI on the l-th time interval. Moreover, the phase value on the l-th time interval is constant, depends on the sign of the information symbol and can take values 0 or π;

θ2 _lk is the phase of the signal in the quadrature kth CVI on the lth time interval. Moreover, the phase value is constant on the l-th time interval, depends on the sign of the information symbol and can take the values π / 2 or -π / 2.

The noise component at the input of the K-channel receiver has the form

;where ψ (t) is the phase of the noise components n _cs (t) and n _sn (t), which is a random process uniformly distributed over the interval

;

n _cs (t) n _sn (t) are the amplitudes of the noise components in the in-phase and quadrature channels, respectively.

Moreover, n (t), n _cs (t), n _sn (t) are random processes distributed according to the normal law with a zero mean value. The spectral power density of the process n (t) is N ₀ , and for the processes n _cs (t) and n _sn (t) - N _0/2 ; dispersion n (t) process is σ ^2, and processes n _cs (t) and n _sn (t) - σ ^2/2, i.e.

2. At the output of the UG (2), a signal of the form

where ω _g is the frequency of UG;

φ is the initial phase of the UG frequency relative to the frequency of the received signal.

At the output of the PV (1), the signal has the form

3. Information in the channel is transmitted by blocks of L-th length, each block includes m information symbols, the duration of each of which is equal to l. Each information symbol corresponds to a channel orthogonal sequence. To increase structural secrecy, each information block is “closed” by a masking sequence whose length is L.

4. To ensure high structural secrecy in the group signal received at the input of the receiving device, in the explicit form, there is no pilot signal (synchronization signal). To solve the problems of signal detection, synchronization, as well as tracking the carrier and clock frequencies, the information circulating in the CVI allocated for these purposes is used. In our case, the first channel is allocated for these purposes (k = 1).

The third and fourth inputs of the first CVI (67) receive the sequences P1 _l11 and P2 _l1K , respectively. The product of these sequences provides the sequence P _C. The SF is also tuned to this sequence (35). The same sequence П _С with (K + 2) -th output of GKKPP (46) is supplied to the first input of Sm2 (48) through the corresponding open EC (69) or (70).

5. At the moment of switching on the receiving device, the beginning of the sequences generated by GKOKP (46) and GMOKP (47) do not coincide with each other, and also, as a rule, do not coincide with the beginning of the sequences received at the input of the receiving device.

6. The beginning of the masking sequence arriving at the input of the receiving device coincides with the beginning of the information block arriving at the input of the receiving device and with the beginning of the first channel sequence in the information block.

7. After turning on the receiving device, the electronic keys, (43) and (50) are open, and the EC (56), (69) and (70) are closed.

8. The threshold value of the control panel (62) in the general case is determined by the required value of the probability of false alarms and is selected based on the following conditions:

the total value of the interfering components of the in-phase and quadrature channels (interfering components from 5 and 6 outputs of the CVI (67)), accumulated Int. (63) on the interval of the duration of the information symbol l, shall not exceed the value of the selected threshold;

the total value of the energy of the components of the useful signal of the in-phase and quadrature channels (components of the useful signal from 5 and 6 outputs of the CVI (67)), accumulated Int. (63), must exceed the value of the selected threshold for a time interval of less than l to ensure that the EC (43) and (50) are closed and the EC (56) is opened until the next pulse appears from the output of the SF (35).

9. At the exhaust gas output (17), a signal of the form

and at the output of the PV (16) a signal of the form

where _ωg is the frequency of the exhaust gas, and its value corresponds to the value of the intermediate frequency ω _pr at the output of the phase-transfer filter (19) and (33).

10. To increase the structural secrecy of the signals, we assume that in each k-th CVI two different channel orthogonal code sequences from the ensemble of sequences generated by GKOKP (46) should be used, i.e. in the in-phase channel of the k-th KVI, the sequence with the number i is used, and in the quadrature channel of the k-th KVI - the sequence with the number j. Let the volume of the ensemble of sequences generated by GKKP (46) be equal to K. Then, to implement the above condition, we take the following relationship between i, j and k: let i = k, a j = K-k + 1. If i = j, then in this case j = i + 1.

In the general case, the operation of the receiver consists in solving the following problems:

signal detection;

establishment and maintenance of receiver synchronization on carrier and clock frequencies;

highlighting information.

The work of the receiver. Let an additive mixture of the signal s (t) (2) and noise n (t) (3) be supplied to the input of the receiver, and, consequently, to the first inputs of the inverter (18) and (34).

At the same time, to the second input of the inverter (18) directly, and to the second input of the inverter (34) through the PV (1) from the output of the UG (2), signals of the form (5) and (6) are applied, respectively.

Then the signal component in the in-phase channel can be represented as

and the noise component - in the form

and in the quadrature channel the signal component is in the form

and the noise component - in the form

As a result of transformations of the signal and noise components in the inverter (18) and in the inverter (34), the components of the total (ω _∑ = ω _o + ω _g ) and difference (ω _p = ω _o -ω _g ) frequencies of the signal and noise will appear at their outputs . The components of the total frequency ω _{∑ of the} signal and noise are suppressed by the filters of the intermediate frequency (19) and (33), and the components of the difference frequency ω _p (let's call it the intermediate frequency ω _pr ) pass through the PLL (19) and (33).

Then the signal component at the output of the PLL (19) (common mode channel) will have the form

and the noise component is

where u _шcs - the amplitude of the noise in the common mode channel;

u _ssn - noise amplitude in the quadrature channel.

And the signal component at the output of the PLL (33) (quadrature channel) will have the form

and the noise component is

Receiver operation in signal detection mode. The signal from the output of the PLL (19) (common mode channel) of the form (13) and (14) is fed to the first and second inputs P (38), and the output of the PLL (33) (quadrature channel) is a signal of the form (15) and (16) - to the first and second inputs P (40).

The signal at the output P (38) can be represented as

After squaring, expression (17) takes the form

Taking into account that the cos ² α = _^1/2 (cos2α + 1), where α = (ω _{ave t + θ1 lk -φ), a} ( P0 _l) = 1 and ² (P1 _lki) ² = 1 expression

.

.

Taking into account that α = sin ^{2 _1/2} (1-cos2α), where α = (ω _ave t + θ2 _lk -φ), and (P0 _l) ² = 1 and (n2 _lkj) ² = 1 expression

, где α=(ω_прt+θ1_lk-φ), а β=(ω_прt+θ1_ln-φ); (П0_l)²=1; П1_lki П1_lni=П1_lkn, где П1_lkn - одна из последовательностей, генерируемых ГКОКП (46), то выражениеGiven that

where α = (ω _pr t + θ1 _lk -φ), and β = (ω _pr t + θ1 _ln -φ); (P0 _l ) ² = 1; _{П1 lki П1 lni} = _{П1 lkn} , where _{П1 lkn} is one of the sequences generated by GKKP (46), then the expression

, где α=(ω_прt+θ2_lk-φ), а β=(ω_прt+θ2_ln-φ); (П0_l)²=1; П2_lkj П2_lnj=П2_lkn, где П2_lkn - одна из последовательностей, генерируемых ГКОКП (46), то выражениеGiven that

Where α = (ω _ave t + θ2 _lk -φ), and β = (ω _ave t + θ2 _ln -φ); (P0 _l ) ² = 1; P2 _lkj P2 _lnj = P2 _lkn , where P2 _lkn is one of the sequences generated by GKKPP (46), then the expression

, где α=(ω_прt+θ2_lk-φ), а β=(ω_прt+θ2_ln-φ); (П0_l)²=1; П1_lki П2_lnj=П12_lkn, где П12_lkn - одна из последовательностей, генерируемых ГКОКП (46), то выражениеGiven that

Where α = (ω _ave t + θ2 _lk -φ), and β = (ω _ave t + θ2 _ln -φ); (P0 _l ) ² = 1; _{П1 lki П2 lnj} = _{П12 lkn} , where _{П12 lkn} is one of the sequences generated by GKKP (46), then the expression

Expression

Expression

Expression

Expression

Expression

Expression

From the analysis of the above expressions it follows that in the multiplier (38) as a result of multiplying the signals received at its inputs, components of the total and difference frequencies of the signal and noise appear at its output.

The components of the total signal frequency and common-mode channel noise are suppressed by the low-pass filter (37), and the low-frequency components pass through the low-pass filter (37). Then the signal at the output of the LPF (37) takes the form

Taking into account that θ1 _lk and θ1 _ln can only take values 0 or π, and θ2 _lk and θ2 _{ln can} only take π / 2 or -π / 2, then cos (θ1 _lk -θ1 _ln ) = ± 1, cos ( θ2 _lk -θ2 _ln ) = ± 1 and sin (θ2 _ln -θ1 _lk ) = ± 1, then the signal at the output of the LPF (37) can be represented as

представляет собой последовательность П_с, на которую настроен СФ (35), слагаемые в фигурных скобках представляют собой шумовую составляющую сигнала в синфазном канале. Этот сигнал поступает на первый вход См (36).From the analysis of expression (17c) it follows that the terms in parentheses are a constant value, the terms in square brackets are direct or inverse orthogonal code sequences from an ensemble of sequences generated by GKKP (46), and the fourth term

represents the sequence P _s , to which the SF is configured (35), the terms in curly brackets represent the noise component of the signal in the in-phase channel. This signal is fed to the first input, see (36).

The signal at the output P (40) can be represented as

After squaring, expression (18) takes the form

If we carry out transformations with expression (18a) similar to the transformations carried out with expression (17a), it will become clear that in the multiplier (40) as a result of multiplying the signals received at its inputs, the components of the total and difference frequencies of the signal appear at its output and noise.

The components of the total frequency of the signal and the noise of the quadrature channel are suppressed by the TTFLF (39), and the low-frequency components pass through the PFNF (39). Then the signal at the output of the LPF (39) takes the form

представляет собой последовательность П_с, на которую настроен СФ (35), слагаемые в фигурных скобках представляют собой шумовую составляющую сигнала в квадратурном канале. Этот сигнал поступает на второй вход См (36).From the analysis of expression (18b) it follows that the terms in parentheses are a constant value, the terms in square brackets are direct or inverse orthogonal code sequences from an ensemble of sequences generated by GKKP (46), and the fourth term

represents the sequence P _s , to which the SF is configured (35), the terms in braces represent the noise component of the signal in the quadrature channel. This signal is fed to the second input, see (36).

The resulting signal at the output of cm (36) can be represented as

A signal of the form (19) is fed to the input of the SF (35) and to the second input P (49).

Given that the sequence P _C can be either direct or inverse, a positive or negative impulse appears at the output of the matched filter (35).

The signal from the output of the SF (35) through the quadrator (45) and the open EC (43) is fed to the input of the control unit (44), in which the levels of the incoming signal and the set threshold are compared. When the signal exceeds the threshold value, a decision is made to detect the signal and a voltage pulse appears at the output of the control unit (44), which is fed to the first inputs of the GKOKP (46) and GMOKP (47). This signal sets them to their original state. From this moment we can assume that:

the beginnings of all channel orthogonal code sequences generated by GKKPP (46), namely, the sequences at the outputs 1 ... K and the sequences at the (K + 2) th output, coincide with the beginning of the received channel orthogonal code sequences (including the beginning of the sequence П _с , coming from the (K + 2) -th output of GKKPP (46) to the first input of Sm2 (48), coincides with the beginning of the sequence P _s , which comes from the output of Sm (36) to the second input of P (49));

the beginnings of channel orthogonal code sequences, both generated by GKOCP (46) and received, coincide with the beginning of a masking orthogonal code sequence generated by GMKKP (47).

It should be noted that the match is ensured within the interval of the duration of the elementary symbol of the channel and masking sequences, namely, in the range (-T _o / 2≤τ≤ + T _o / 2), where T _about is the duration of the elementary symbol of the sequences, and τ - delay value.

Only the beginning of the masking sequence generated by GMOCP (47) does not coincide with the beginning of the received masking sequence.

The next pulse generated at the output of the control unit (44) is also fed to the first inputs of the GKOKP (46) and the GMOKP (47) and sets them to their initial state if they are in a different state. But since the beginnings of the channel sequences generated by GKKP (46) and the beginnings of the channel sequences received by the receiver already coincide (this provided the first impulse, i.e., GKKP (46) is already in the initial state at this moment), then this impulse does not change the operation mode of GKKP (46). But this impulse, received at the first input of the GMOCP (47), sets it again to its original state, and it begins to form a masking sequence first. And this process will take place until the beginning of the masking sequence generated by GMOCP (47) coincides with the beginning of the accepted masking sequence.

Joint synchronous operation of the generators GMOKP (47) and GKOKP (46) is provided by the UTG (51), from the output of which clock pulses are fed to their second inputs.

From the analysis of expression (19) it follows that the first term is a constant and, therefore, this component is orthogonal to the characteristic of the matched filter (35), i.e. they do not miss. The second term is a useful signal and a matched filter is tuned to it. The third term is the noise component, which SF (35) is averaged.

Then the ratio of the signal power to the noise power at the output of the SF (35) can be represented as

where N is the number of elementary symbols in the channel orthogonal code sequence;

And _d and _{d SHES} are the effective values of the amplitudes of the signal and noise on the interval of the elementary symbol, respectively;

and ² _{d shes} = P _shes is the average value of the noise power in the interval of an elementary symbol;

And ² _d = R _SES - the value of the signal power in the interval of an elementary symbol.

From the analysis of expression (20) it follows that when a signal is detected, there are no losses, i.e. the proposed signal detection circuit is an optimal device.

Simultaneously with the process of establishing coincidences of the beginnings of the received and generated GMOCP (47) of masking sequences (i.e., simultaneously with the process of establishing synchronization by the masking sequence), the UTG clock frequency is monitored (51). Why does the channel direct or inverse sequence P _s go to the first input of Sm2 (48) from the (K + 2) -th output of GKOKP (46) through the open EC (69) or (70), and the clock pulse to its second input from the output of the UTG (51).

If a negative impulse appears at the output of the SF (35), (in this case, the inverse sequence П _{с s} arrives at the second input P (49) from the output of Cm (36)), then this pulse through Inv. (71) opens EC (70) and the sequence P _s , s (K + 2) -th output of GKKP (46) through open EC (70) and Inv. (72) enters the first input of Sm2 (48).

If a positive impulse appears at the output of the SF (35), (in this case, the direct sequence P _s arrives from the output of Cm (36) to the second input P (49)), then this pulse opens EC (69) and the sequence P _s , s ( K + 2) -th output GKOKP (46) through an open EC (69) is supplied to the first input Sm2 (48).

In Sm2 (48), the flows arriving at its first and second inputs are modulo two. The total signal from the output of Sm2 (48) is supplied to the first input P (49), the second input of which receives the signal from the output of Sm (36), which contains the sequence P _s (direct or inverse) obtained by multiplying the received sequences P1 _l11 and P2 _l1K .

In the multiplier (49), a convolution of the received signals is carried out and at its output, along with the noise component, there is a signal that carries information about the magnitude of the mismatch in the clock delay of the received and generated GKOKP (46) sequences. The signal from the output P (49) through the open EC (50) is fed to the input of the PhD (53). The delayed error protection phase signal (53) is fed to the UE input (52), which, acting on the UTG (51), adjusts its clock frequency to the clock frequency of the received sequence P _s , leading to a delay error τ of zero.

Thus, even at the initial stage of synchronization of the receiver (there is still no synchronization in the masking sequence П0), tracking of the clock frequency is ensured.

At the end of each cycle of generating channel orthogonal code sequences, pulses appear at the (K + 1) -th output of GKKP (46), the repetition rate of which is determined by the period of the generated sequence. This stream of pulses arrives at the seventh inputs of all channels of information allocation and the second input Int. (63) and ensures the joint operation of all channel integrators (as applied to the first channel, it is Int. (24), (28)) and the integrator (63), and also provides sequential input of information to the decoding device of each CVI (as applied to the first CVI, it is a DC (26)) and serial output of information from it.

As soon as the beginning of the masking sequence formed by GMOKP (47) coincides with the beginning of the accepted masking sequence, the process of extracting information begins in CVI (67) and information samples (voltage responses) appear on its 5th and 6th outputs, which are received at KB inputs (65) and (66), respectively. In KB (65) and (66), the incoming signal is squared and from their outputs goes to the first and second inputs of Cm (64), respectively. The total signal output Cm (64) is fed to the first input Int. (63) in which the accumulation of energy occurs. The resulting value of the stored energy output Int. (63) constantly goes to the input of the control panel (62), in which this value is compared with a threshold. At the moment of exceeding the value of the stored energy of the set threshold, a signal appears at the output of the control unit (62), which closes the EC (43) and (50) and opens the EC (56).

Closed EC (43) prevents further fine tuning of GMOCP (47), since the beginning of the masking sequence generated by GMOCP (47) already coincides with the beginning of the received masking sequence.

Formed GMOKP (47) masking orthogonal code sequence through its first output goes to the fifth inputs of all KVI. At the end of each cycle of forming a masking orthogonal code sequence, pulses appear at the 2nd output of the GMOCP (47), the repetition rate of which is determined by the period of the generated sequence. This stream of pulses is fed to the 6th inputs of all channels of information extraction and provides cyclic synchronization of decoders of these channels.

Closed EC (50) and open EC (56) provide switching the tracking mode for the clock frequency. A closed EC (50) eliminates the possibility of tracking the clock frequency according to the sequence P _C allocated in the process of signal detection (since EC (50) breaks the circuit between the output P (49) and the input of the PhD (53)), and the open EC ( 56) provides the connection of the output Cm (61), on which information is generated on the magnitude of the mismatch of the clock frequencies on the received information signal, to the input of the PhD (53). The process of generating a signal about the magnitude of the mismatch of clock frequencies for the received information signal will be discussed below.

The operation of the receiver in the mode of selection of information. The operation of the receiver in the mode of extracting information can conditionally be divided into two stages. At the first stage, a group video signal is extracted from the received group radio signal, and at the second stage, from the received group video signal, each CVI extracts the actual information transmitted on this channel.

I stage. Signals (signal and noise components of the form (13), (14) and (15) and (16) from the output of the intermediate frequency filters (19) and (33) are fed to the first IF inputs (20) and (32), respectively. the second input of the inverter (20) and (32) receives a harmonic signal from the exhaust gas (17), and directly to the inverter (20), and through the inverter (32) through the PV (16).

As a result of transformations of the signal and noise components in the inverter (20) and (32), the components of the total and difference frequencies of the signal and noise will appear at their outputs. The components of the total frequency of the signal and noise are suppressed by the LPF (21) and (31), and the components of the difference frequency (video signal) pass through the LPF (21) and (31) and are fed to the ADC inputs (22) and (30), respectively, in which the video signal digitized. From the output of the ADC (22), the video signal is digitally fed to the first inputs of all the CVI and to the first inputs of the CC CC (57) and (58), and from the output of the ADC (30) - to the second inputs of all CVI and to the second inputs of the CC CC ( 57) and (58).

The above transformations can be analytically presented as follows.

The signal component at the inverter output (20) s _outs (t) (common mode channel) in general can be represented as

and taking into account expressions (7) and (13), as well as the condition that ω _og = ω _pr expression (21) will take the form

A signal of the form (22) is fed to the input of the high-pass filter (21), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the LPF (21), at its output, the signal component will have the form

The noise component at the inverter output (20) n _output (t) (common mode channel) can be represented in general form as

Taking into account expressions (7) and (14), as well as the condition that ω _σ = ω _pr, expression (24) takes the form

A signal of the form (25) is fed to the input of the LPF (21), and after transformations to the LPF (21), the noise component at its output will have the form

The signal component at the output of the inverter (32) s _outsn (t) (quadrature channel) in general can be represented as

and taking into account expressions (8), (15), as well as the condition that ω _og = ω _pr expression (27) will take the form

A signal of the form (28) is fed to the input of the LPF (31), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the LPF (31) at its output, the signal component will have the form

The noise component at the inverter output (32) n _{output ssn} (t) (quadrature channel) in general can be represented as

Taking into account expressions (8) and (16), as well as the condition that ω _σ = ω _pr, expression (30) takes the form

A signal of the form (31) is fed to the input of the LPF (31), and after transformations to the LPF (31), the noise component at its output will have the form

II stage. The work of the channel for highlighting information.

Isolation of information by channels begins from the moment of coincidence of the beginnings of the masking sequence generated by GMOKP (47) and the accepted masking sequence. We consider the operation of the information extraction channel according to the structural diagram of the CVI (67) shown in Fig. 1.

The first input of the CVI (67), and, consequently, the first inputs of the CC KVI (23) and (29) from the output of the ADC (22), is fed a digital signal, and the second input of the CVI (67), and, therefore, and the second inputs of the CC KVI (23) and (29) from the output of the ADC (30) also receive a video signal in digital form.

At the third input of the CVI (67), and, consequently, at the first input of Sm2 (41) from the first output of the GKOKP (46), the reference channel orthogonal code sequence П1 _{l11 is} received, and at the fourth input of the CVI (67), and, therefore, at the first input of Sm2 (42) from the Kth output of GKKPP (46), the reference channel orthogonal code sequence P2 _{l1K is received} .

The fifth input of the CVI (67), and, consequently, the second inputs of Sm2 (41) and Sm2 (42) from the first output of the GMOCP (47) receives the reference masking orthogonal code sequence П0.

In cm2 (41) takes place modulo two two posledovatelnoste⊕ P0 and P1 _l11. The resulting sequence P01 == P0 P1 _l11 from the output of Sm2 (41) is fed to the third input of the KK KVI (23) and through the eighth output of the KVI (67) to the third input of the KK LF (8) and to the first input of Sm2 (55).

In Sm2 (42), modulo two modulo two two sequences P0 and P2 _{l1K are added} . The resulting sequence П02 = П0⊕П2 _l1к from the output of СМ2 (42) is fed to the third input of КК КВИ (29) and through the seventh output of КВИ (67) - to the third input of КК LF (12) and to the first input СМ2 (54).

In the CVI quadrature correlators (23) and (29), the received signals (digital video signals) are multiplied with the resulting sequences P01 and P02, as well as the information component of the signal transmitted in the in-phase channel is extracted from the video signal received in the in-phase and quadrature channels (CC) CVI (23)) and extracting the information component of the signal transmitted in the quadrature channel from the video signal received in the in-phase and quadrature channels (CC CVI (29)). The work of the quadrature correlators KVI will consider the example of the work of KK KVI (23) according to the structural diagram shown in Fig.2A.

At the first input of the CC KVI (23), and therefore at the first input P (1), a digital video signal is received from the output of the ADC (22), at the second input of the CC KVI (23), and, therefore, at the first input P ( 4), the video signal is received in digital form from the output of the ADC (30), and to the third input of the CC KVI (23), and therefore to the second inputs P (1) and (4), the resulting sequence P01 is received from the output of Sm2 (41) .

As a result of multiplication in P (1) and (4) from the signals received at the first inputs P (1) and (4), the masking sequence P0 is “removed” and samples of the information component transmitted in the in-phase channel and noise appear on their outputs component that are supplied to the corresponding inputs of the DSP (2) and (5). Moreover, the readings of the information component at the outputs P (1) and P (4) have different signs. In the low-frequency filter (2) and (5), the high-frequency components received at their input are suppressed, and at the output there are samples of the information component averaged over the interval of the elementary symbol of the channel orthogonal sequence, and samples of the noise component. Thus, on the interval of the information symbol at the outputs of the DPSF (2) and (5), N samples will appear.

From the output of the DSCF (2), the samples are fed to the first input, see (3), and from the output of the DSCP (5) through Inv. (6) - to the second input, see (3), in which they are summed. The total value of the samples from the output of Sm (3) goes to the output of the QC KVI ((23). Similar transformations occur in the KK KVI (29).

The total value of the samples from the output of the QC KVI (23) is supplied to the first input Int. (24) and to the fifth output of the CVI (67), and from the output of the CC KVI (29) to the first input of Int. (28) and to the sixth exit of KVI (67).

The samples at the fifth and sixth outputs of the CVI (67) provide switching of the tracking mode for the clock frequency according to the sequence П _С to the tracking mode for the clock frequency according to the received information signal.

In integrators (24) and (28), all samples arriving at the interval of the duration of the information symbol (the interval of the duration of the channel orthogonal sequence) are summed. At the end of the cycle of forming channel orthogonal sequences (end of an information symbol) from the (K + 1) -th output of GKOKP (46) to the second inputs of Int. (24) and (28) a pulse arrives that transfers the contents of the integrators in the form of a pulse of positive or negative polarity to the corresponding inputs of the comparators (25) and (27).

Given the above, as well as the expressions (23), (26), (29), (32), the values of the information and noise components at the output of the integrator (25) (common mode channel) can be represented as:

for voltage signal component

and for the power of the signal component

for the noise component, taking into account that when passing through the quadrature correlator its statistical characteristics do not change, the value of its power can be represented as

Then the ratio of signal power to noise power at the output of the integrator, and, therefore, at the output of the information channel will be

Expression (36) gives reason to believe that the reception of information is optimal, since there is no signal energy loss.

Similar considerations hold true for the quadrature channel (i.e., with respect to the ratio of signal power to noise power at the output of Int. (28)).

In the comparators (25) and (27), the flow of bipolar pulses arriving at their inputs from the corresponding outputs of the integrators (24) and (28) is converted into a sequence of information symbols.

From the output of the CM (25), a sequence of information symbols is fed to the first output of the CVI (67), to the first input of the DC (26) and through the ninth output of the CVI (67) to the second inputs P (9) and P (59), and from the output of the CM (27) - to the second output of the CVI (67), to the second input of the DC (26) and through the tenth output of the CVI (67) to the second inputs P (11) and P (60).

The decoder (26) decodes the information received at its first and second inputs. We consider the operation of the decoder in the block diagram shown in figa. On the structural diagram, the numbers indicate:

26 - decoder channel information allocation (DC KVI);

8 - common-mode decoder in KVI (DK SK);

9 - quadrature channel decoder in CVI (DK KK);

1, 5 - shift register for m cells (PC _m );

3, 7 - register shift by n cells (PC _n );

2, 6 - decoding device (DU);

4 - frequency divider m / n (DF).

The first and second inputs of the DC KVI (26) receive information symbols from the corresponding outputs of the CM (25) and (26). Each incoming information symbol through the first inputs of the DC SK (8) and DC KK (9) are supplied to the corresponding first inputs PC _m (1) and (5) and are recorded in the first cell of the corresponding register. From the (k + 1) -th output of GKOKP (46) through the third input of the DC KVI (26), through the second inputs of the DC SK (8) and DC KK (9), pulses are received at the second inputs PC _m (1) and (5) which in the registers play the role of shear pulses, i.e. these impulses ensure the advancement of information in the register and the filling of its cells. After the arrival of m shift pulses, all the cells of the registers PC _m (1) and (5) are filled with the received information symbols. After every m shear pulses from the second output of the GMOKP (47) through the fourth input of the DC KVI (26) and the corresponding fourth inputs of the DC SK (8) and the DC KK (9) to the third inputs PC _m (1) and (5) receives a synchronizing pulse which all information symbols contained in cells PC _m (1) and (5) are supplied by a parallel code (through the 1, 2, ... mth outputs) to the corresponding inputs of the remote control (2) and (6). In the decoding devices (2) and (6), in accordance with the established algorithm, the received combination of symbols is decoded (elimination of redundancy, detection and elimination of erroneously received symbols, etc.). After decoding, information symbols with a parallel code (through the 1, 2, ... n-th outputs) are fed to the corresponding inputs of PC _n (3) and (7), of which information under the action of shear pulses arriving at their (n + 1) -th the inputs from the output of the DC (4), a serial code through the outputs of the DC SK (8) and DC KK (9), the first and second outputs of the DC KVI (26) are output to the third and fourth outputs of the CVI (67).

So, the first and second outputs of CVI (67) are outputs of not decoded information of in-phase and quadrature channels, respectively, and its third and fourth outputs are outputs of decoded information of in-phase and quadrature channels, respectively.

The operation of the receiver in the tracking mode of the clock frequency of the received information signal. Tracking the clock frequency by an information signal starts from the moment the output of Sm (61) is connected, on which information about the magnitude and sign of the clock frequency mismatch is generated, to the input of the FDO (53).

The process of generating a signal about the magnitude of the mismatch of clock frequencies for the received information signal is as follows.

The first input of Sm2 (54) from the seventh output of CVI (67) receives the resulting sequence of the form П02, and from the eighth output of CVI (67) to the first input of Sm2 (55) - the resulting sequence of the form П01. The second inputs of Sm2 (54) and (55) from the output of the UTG (51) receive a sequence of clock pulses. The results of addition in Cm2 (54) and (55) (we denote the results of addition as the sequences П02 _t and П01 _t, respectively) from their outputs go to the third inputs of the corresponding CC CC (58) and (57). The first inputs of the CC CC (57) and (58) receive a video signal of the form (23) and a noise component of the form (26) (common mode channel), and the second inputs of the CC CC (57) and (58) receive a video signal of the form (29) and noise component of the form (32) (quadrature channel). In CC CC (57) and (58), the signals received at their inputs are convolved and signals that carry information about the time offset of the clock frequencies of the received and reference signals appear at their outputs. We consider the work of CC CC (57) and (58) using the example of the work of CC CC (57) according to the block diagram shown in Fig.2c.

Let a video signal of the form (23) and an interference of the form (26) be supplied to the first input of the CC CC, and, consequently, to the first input of P (1), and the second input of CC CC, and, therefore, to the first input of P (5 ), a video signal of the form (29) and an interference of the form (32) are received, and to the third input of the QC PM, and therefore to the second inputs P (1) and (5), the resulting sequence of the form P01 _{t is} received from the output of Sm2 (55).

As a result of multiplication in P (1) and (5), the masking sequence P0 (provided that the clock frequencies are exactly the same) is "removed" from the signals received at their first inputs and samples of the information component transmitted in the common-mode channel appear noise component and component about the mismatch of the clock frequencies of the received and reference signals, which are fed to the corresponding inputs of the DSP (2) and (6).

In the low-frequency filter (2) and (6), the high-frequency components received at their input are suppressed, and the information component reads, the noise component and the component about the mismatch of the clock frequencies of the received and reference signals averaged over the interval of the information symbol appear at the output.

можно представить следующим образом:Analytically signal at the output of the DSP (2)

can be represented as follows:

Considering that N samples will appear on the output of the information symbol at the output P (1), expression (37) can be represented as

- усредненное значение составляющей о рассогласовании тактовых частот принятого и опорного сигналов в синфазном канале;Where

- the average value of the component about the mismatch of the clock frequencies of the received and reference signals in the common mode channel;

,

- отсчеты шумовых составляющих квадратурного и синфазного каналов соответственно.

,

- samples of the noise components of the quadrature and common mode channels, respectively.

можно представить следующим образомA signal at the output of the DSP (6)

can be represented as follows

Considering that on the interval of the information symbol at the output P (5) N samples will appear, expression (39) can be represented as

- усредненное значение составляющей о рассогласовании тактовых частот принятого и опорного сигналов в квадратурном канале;Where

- the average value of the component about the mismatch of the clock frequencies of the received and reference signals in the quadrature channel;

From the expressions (38) and (40) it follows that the components at the outputs of the low-pass filter (2) and the low-frequency filter (6) have different signs.

From the output of the DSCF (2), the samples are fed to the first input Cm (3), and from the output of the DSCP (6) through Inv. (7) - to the second input, see (3), in which they are summed. The result of adding s _o (τ) can be represented as

where r (τ) = r _cs (τ) + r _sn (τ) is the total average value of the components about the mismatch of the clock frequencies of the received and reference signals in the in-phase and quadrature channels.

A signal of the form (41) from the output of Sm (3) through the delay line (4), in which the signal is delayed for a time equal to the duration of the information symbol, is output to the CC CC (57).

Similar transformations occur in CC CC (58). Then the signal at the output of the QC PM (58) can be represented as

From the analysis of expressions (41) and (42) it follows that:

r (τ) determines the magnitude and sign of the mismatch of the clock frequencies of the received and reference signals of the receiver;

the delay estimate τ is affected by the tracking accuracy of the carrier phase φ, the value of which is compensated in the carrier tracking circuit (to be discussed below), as well as the information components θ1 and θ2, which are compensated in the multipliers (59) and (60).

The signals from the outputs of the CC CC (57), (58) are fed to the corresponding first inputs P (59) and (60), the second inputs of which receive signals from the ninth and tenth outputs of the CVI (67), respectively. In the multipliers (59) and (60) from signals of the form (41) and (42), the information component is removed, i.e. the influence of the transmitted information on the estimation of the delay value τ is excluded. Further, the signals from the outputs of the multipliers (59) and (60) are supplied to the first and second inputs of Cm (61), respectively, in which the resulting error signal is generated, proportional to the value of the time mismatch of the clock frequencies of the received and reference signals. Provided that φ = 0, the expression for the resulting error signal can be represented as

From the output of Cm (61) through the open EC (56), the resulting error signal of the form (43) is fed to the input of the FDO (53), closing the loop for tracking the clock frequency.

From the expression (43), we can estimate the ratio of the signal power and noise at the input of the PDO (53) at the maximum discrepancy of the clock frequencies, i.e. at a discrepancy of τ = ± T _o / 2, at which r (τ) = 1.

Expression (44) gives reason to believe that in the proposed scheme for tracking the clock frequency there are no losses in the signal-to-noise ratio, i.e. This tracking scheme is optimal.

The operation of the receiver in the tracking mode of the carrier frequency. The process of generating a signal about the magnitude of the mismatch between the carrier and the reference frequency occurs as follows.

The signal from the output of the PLL (19) (common mode channel) is fed to the first input of the inverter (5), and the output of the PLL (33) (quadrature channel) is fed to the first input of the inverter (15). At the second inputs of the inverter (5) and inverter (15), a signal is output from the exhaust gas (17). Moreover, to the second input of the inverter (5) directly, and to the second input of the inverter (15) - through the PV (16).

In IF (5) and (15) as a result of multiplying the signals received at their inputs, components of the total and difference frequencies of the signal and noise appear at their outputs.

The components of the total frequency of the signal and noise are suppressed by the LPF (6) and (14), and the components of the difference frequency (video signal) pass through the LPF (6) and (14) and are fed to the ADC inputs (7) and (13), respectively, in which the video signal digitized.

The above transformations can be analytically represented as follows.

The signal component at the inverter output (5) s _output5 (t) (common mode channel) in general can be represented as

and taking into account expressions (8) and (13), as well as the condition that ω _og = ω _pr expression (45) will take the form

A signal of the form (46) is fed to the input of the LPF (6), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the LPF (6) at its output, the signal component will have the form

The noise component at the inverter output (5) n _output5 (t) (common mode channel) in general can be represented as

Taking into account expressions (8) and (14), as well as the condition that ω _σ = ω _pr, expression (48) takes the form

A signal of the form (49) is fed to the input of the LPF (6), and after transformations to the LPF (6), the noise component at its output will have the form

The signal component at the inverter output (15) s _out15 (t) (quadrature channel) in general can be represented as

and taking into account expressions (7), (15), as well as the condition that ω _σ = ω _pr, expression (51) takes the form

A signal of the form (52) is fed to the input of the PFNF (14), in which the high-frequency components are suppressed and the video signal is selected. After these transformations in the CPSF (14), at its output, the signal component will have the form

The noise component at the inverter output (15) n _o15 (t) (quadrature channel) in general can be represented as

Taking into account expressions (7) and (16), as well as the condition that ω _og = ω _pr expression (54) takes the form

A signal of the form (55) is fed to the input of the LPF (14), and after transformations to the LPF (14), the noise component at its output will have the form

From the output of the ADC (13), the video signal is digitally fed to the first inputs of the QC LF (8) and (12), and from the output of the ADC (7) - to the second inputs of the QC LF (8) and (12). At the third input of the QC LF (8) from the eighth output of the CVI (67), the resulting sequence P01 is received, and at the third input of the QC LF (12) from the seventh output of the CVI (67), the resulting sequence P02 is received.

In CC LF (8) and (12), a convolution of the signals received at their inputs is carried out and signals appear on their outputs that carry information about the size of the mismatch between the received carrier and reference frequencies. The work of the QC LF (8) and (12) will consider the structural diagram presented in figb.

Work QC LF (8). Let the video input of the form (53) and the noise of the form (56) be supplied to the first input of the CC LF (8), and, consequently, to the first input P (1), and the second input of the CC LF (8), and, therefore, to the first input P (5), a video signal of the form (47) and a noise of the form (50) are received, and to the third input of the QC LF (8), and, consequently, to the second inputs of P (1) and (5), the resulting a sequence of the form P01.

As a result of multiplication in P (1) and (5), the masking sequence 770 is removed from the signals received at their first inputs (provided that there is no delay in the clock frequencies) and samples of the information component transmitted in the common-mode channel appear noise component and component about the mismatch of the carrier and the reference frequencies, which are supplied to the corresponding inputs of the DPC (2) and (6).

In the DFNCH (2) and (6), the high-frequency components received at their input are suppressed, and at the output there are samples of the information component, samples of the noise component and the component about the mismatch of the carrier and reference frequencies, averaged over the interval of the information symbol.

можно представить в видеAnalytically signal at the output of the DSP (2)

can be represented as

Considering that in the interval of the information symbol, at the input of the DPSF (2), N samples will appear, and the clock frequencies coincide in delay, expression (57) can be represented as

- в видеand at the output of the DSP (6)

- as

будет иметь видA signal of the form (58) from the output of the DPSF (2) is fed to the first input of the adder (3), and a signal of the form (59) from the output of the DPSF (6) is fed to the second input of the adder (3). In the adder (3), the above signals are added together and at the output of Cm (3) the total signal

will have the form

.A signal of the form (60) from the output of Sm (3) through the delay line (4), in which the signal is delayed for a time equal to the duration of the information symbol, is output to the QC LF (8), i.e.

.

Taking into account that θ1 _l1 takes values (0 or π), expression (60) can be represented as

The work of the QC LF (12). At the first input of the low frequency CC (12), and, consequently, at the first input of P (1), a video signal of the form (53) and an interference of the form (56) are received, and the second input of the low frequency CC (12), and, therefore, the first input is P (5), a video signal of the form (47) and an interference of the form (50) are received, and the third input of the QC LF (12), and therefore the second inputs of the P (1) and (5), receives the resulting sequence of the form P02 .

In the CC LF (12) with the signals received at its inputs, transformations occur similar to the transformations that were previously considered in the CC LF (8). However, taking into account that the resulting input of the LF LF (12) receives the resulting sequence of the form П02, and not П01, as in the LF LF (8), then the output of Cm (3), and, therefore, the output of the LF LF (12) ) the signal will look like

Taking into account that θ2 _lK takes values (π / 2 or -π / 2), expression (62) can be represented as

From the output of the QC LF (8), a signal of the form (61) is supplied to the first input P (9). The second input P (9) receives a signal from the ninth output of the CVI (67), which compensates for the influence of the information component on the estimate of the magnitude of the signal about the mismatch between the carrier and the reference frequencies, and then the signal at the output P (9) will have the form

From the output of the QC LF (12), a signal of the form (63) is supplied to the first input P (11). The second input P (11) receives a signal from the tenth output of the CVI (67), which compensates for the influence of the information component on the estimate of the magnitude of the signal about the mismatch between the carrier and the reference frequencies, and then the signal at the output P (11) will have the form

A signal of the form (64) from the output P (9) goes to the first input of Cm (10), and a signal of the form (65) to the second input of Cm (10). The signal at the output of Sm (10) will have the form

A signal of the form (66) from the output of Sm (10) goes to the input of the phase error filter (4) and after filtering the signal in it, the resulting error voltage from its output through the control element (3) goes to the input of the UG (2), closing the tracking loop for clock frequency, and changes its frequency in such a way as to eliminate the existing phase mismatch of the frequency of the input signal relative to the frequency of the reference oscillator, closing the loop for tracking the clock frequency.

Using expression (66), we estimate the ratio of signal power and noise at the input of the FFO (4) at the maximum allowable phase difference between the received and reference signals, i.e. for φ = ± π / 2

It follows from expression (67) that in the carrier tracking circuit there is an optimal filtering of the carrier frequency with an increase in the signal power by a factor of N.

Assessment of the effectiveness of the proposed technical solution. From the above it follows that the proposed technical solution (receiver) reliably provides not only the detection of signals and the selection of information, as well as tracking the carrier and clock frequencies. This conclusion follows from the analysis of expressions (20), (36), (44) and (67). So, according to expressions (20) and (36), the proposed schemes for detecting the signal and receiving information are optimal devices, since there are no signal energy losses during their operation, expression (44) allows us to assume that in the proposed clock tracking scheme frequency there are no losses in the signal-to-noise ratio, i.e. This tracking scheme is optimal, and expression (67) shows that in the carrier tracking chain there is an optimal filtering with an increase in the signal power by a factor of N.

The general principles for the creation of GKOKP (46) and GMOKP (47) are described in [3]. The implementation option GKOKP (46) is presented in the structural diagram (see figb). The numbers on the structural diagram indicate:

1 - shift register with nonlinear feedbacks, forming the M-sequence (PC);

2 - multiplier (P);

3 - decoder (Dsh);

46 is a generator of channel orthogonal code sequences.

The generated PC (1) non-linear channel orthogonal code sequences are removed from its K outputs (from the 1st to the Kth), which are simultaneously the K outputs of the GKOKP (46).

The first output PC (1) is connected to the first input P (2), and the Kth one is connected to the second input P (2). In the multiplier (2), there is a multiplication of two sequences P1 _l11 and P2 _l1K and at its output, which is the (K + 2) -th output of GKOKP (46), a sequence P _С appears for which the SF is tuned (35).

PC (1) outputs from (K + 1) -th to (K + n) -th are connected to the corresponding inputs (from 1st to n-th) Дш (3). It is known (see [5] p. 106) that any n-digit combination (by the number of register bits) characterizing the state of the shift register at any moment in time occurs only once in the period of the generated sequence. The decoder (3) is configured for a combination that determines the moment of the end of the M-sequence formation and when it appears in the register bits at the output of the decoder (3), which is the (K + 1) -th output of GKKP (46), an impulse appears. Thus, at the (K + 1) -th output of GKOKP (46), a pulse stream is formed, which, arriving at the seventh inputs of all KVI, ensures the synchronous operation of integrators and decoders, and also ensures the operation of Int. (63).

The first input of GKKPP (46), and, consequently, the first input of PC (1) receives a pulse from the output of the control unit (44), which sets PC (1) to its initial state, and to the second input of GKKPP (46), and therefore and the second input of the PC (1) receives clock pulses from the UTG (51), which for the PC (1) act as a shift pulse.

Literature.

1. New standards for broadband radio communications based on W-CDMA technology, M .: International Center for Scientific and Technical Information, 1999. (pp. 38-58).

2. Moiseev V.F., Sivov V.A. Patent No. 2226181 dated February 10, 2005. A quadrature modulated offset (OQPSK) receiver of a multi-channel code division multiplexing system.

3. Interference immunity of radio systems with complex signals / G.I. Aces, V.A. Sivov, V.I. Prytkov and others; Ed. G.I. Tuzova - M .: Radio and communications, 1985 .-- 264 p. (p. 29).

4. Mazurkov M.I. Broadband radio systems: textbook. allowance for students, universities. - O .: Science and technology, 2010 .-- 340 p.

5. Noise-like signals in information transmission systems. / V.B. Pestryakov, V.P. Afanasyev, V.L. Hurwitz et al .; Ed. prof. V.B. Pestryakova. - M .: “Owls. Radio ”, 1973. 424 p.

Claims (4)

1. A multi-channel code-division receiver for receiving quadrature modulated signals of increased structural secrecy, which includes a series-connected phase error filter, a first control element and a controlled generator, the output of which is connected through the first phase shifter to the second input of the second frequency converter, and the second input the first frequency converter is connected to the output of a controlled generator, the first inputs of the first and second frequency converters are combined and are swing device and serially connected filter error delay, a second control element, controlled by a clock generator, characterized in that the receiver circuit additionally introduced K allocating information channels, where K takes on the values from 1 to N-1 and N = 2 ⁿ at n≥1, one of which is allocated for synchronization of the receiver, and each channel for selecting information includes a series-connected first quadrature correlator of the channel for selecting information, the first integrator and the first comparator, as well as the second quadrature correlator of the information extraction channel, the second integrator and the second comparator, the first inputs of the first and second quadrature correlators of the information extraction channel are combined and are the first input of the k-th information extraction channel, where k takes values from 1 to K, the second inputs of the first and the second quadrature correlators of the information extraction channel are combined and are the second input of the k-th information extraction channel, the output of the first comparator is connected to the first input of the decoder and is the first and the ninth outputs of the information extraction channel, the output of the second comparator is connected to the second input of the decoder and is the second and tenth outputs of the information extraction channel, the first output of the decoder is the third output of the information extraction channel, the second output of the decoder is the fourth output of the information extraction channel, the output of the first quadrature channel correlator information extraction is the fifth output of the information extraction channel, the output of the second quadrature correlator of the information extraction channel is the sixth the output of the information extraction channel, the second inputs of the first and second integrator and the third input of the decoder are combined and are the seventh input of the information extraction channel, the fourth input of the decoder is the sixth input of the information extraction channel, the output of the first adder modulo two is connected to the third input of the first quadrature correlator of the information extraction channel and is the eighth output of the information extraction channel, the output of the second adder modulo two is connected to the third input of the second quadrature channel correlator information is the seventh output of the information extraction channel, the first input of the first adder modulo two is the third input of the information extraction channel, the first input of the second adder modulo two is the fourth input of the information extraction channel, the second inputs of the first and second adders modulo two are combined and are the fifth input of the information extraction channel, as well as the first intermediate frequency filter connected in series, the input of which is connected to the output of the first frequency converter, the third a frequency former, a first wideband low-pass filter and a first analog-to-digital converter connected in series to a second intermediate-frequency filter, the input of which is connected to the output of the second frequency converter, a fourth frequency converter, a second wideband low-pass filter and a second analog-to-digital converter connected in series to the fifth a frequency converter, the first input of which is connected to the output of the first intermediate frequency filter, the third broadband lower filter x frequency, a third analog-to-digital converter, a sixth frequency converter, the first input of which is connected to the output of the second intermediate-frequency filter, a fourth broadband low-pass filter and a fourth analog-to-digital converter, the second inputs of the fourth and fifth frequency converters being combined through the second the phase shifter on π / 2 is connected to the output of the reference generator, the second inputs of the third and sixth frequency converters are combined and connected to the output of the reference nerator, serially connected the first quadrature correlator of the carrier frequency tracking circuit and the first multiplier, the output of which is connected to the first input of the first adder, the second quadrature correlator of the carrier frequency tracking circuit and the second multiplier, the output of which is connected to the second input of the first adder in series, the second input the first multiplier is connected to the 9th output of the channel for selecting information allocated for synchronization of the receiver, and the second input of the second multiplier is connected The 10th output of the information isolation channel allocated for receiver synchronization, the output of the first adder is connected to the input of the phase error filter, the first inputs of the first and second quadrature correlators of the carrier frequency tracking circuit are combined and connected to the output of the fourth analog-to-digital converter, the second inputs of the first and the second quadrature correlators of the carrier frequency tracking circuit are combined and connected to the output of the third analog-to-digital converter, the third input of the first quadrature correlator is the carrier frequency tracking pi is connected to the eighth output of the information allocation channel dedicated to synchronize the receiver, the third input of the second quadrature correlator of the carrier frequency tracking circuit is connected to the seventh output of the information allocation channel allocated for receiver synchronization, the first inputs of all information isolation channels, and the first inputs of the first and second correlators of the clock tracking circuit are combined and connected to the output of the first analog-to-digital converter, the second inputs of all information extraction cores, as well as the second inputs of the first and second correlators of the clock tracking circuit, are combined and connected to the output of the second analog-to-digital converter, the output of the first correlator of the clock tracking circuit is connected to the first input of the third multiplier, and the output of the second correlator of the tracking circuit the clock frequency is connected to the first input of the fourth multiplier, the third input of the k-th channel of information extraction is connected to the i-th output of the channel orthogonal code sequence generator where i takes the value k, the fourth input of the k-th channel of information extraction is connected to the j-th output of the channel orthogonal code sequence generator, where j takes the value K-k + 1, and if i equals j, then j takes the value k + 1, the fifth inputs of all information extraction channels are combined and connected to the first output of the masking orthogonal code sequence generator, the sixth inputs of all information extraction channels are combined and connected to the second output of the masking orthogonal code generator of the first sequence, the (K + 1) -th output of the channel orthogonal code sequence generator is connected to the seventh inputs of all the information extraction channels and to the second input of the third integrator, the fifth output of the information extraction channel allocated for synchronizing the receiver is connected to the first input of the second via the first quad the adder, and the sixth output of the channel for extracting information allocated for synchronization of the receiver through the second quadrator is connected to the second input of the second adder, the output of which is through the third the grater and the first threshold device are connected to the combined second inputs of the first, second, and third electronic keys, the ninth output of the information extraction channel dedicated to synchronize the receiver is connected to the second input of the third multiplier, the output of which is connected to the first input of the third adder, and the tenth output of the allocation channel information allocated for receiver synchronization is connected to the second input of the fourth multiplier, the output of which is connected to the second input of the third adder, the output of the third sum through the first electronic key is connected to the delay error filter input, as well as the fifth multiplier and the fifth broadband low-pass filter connected in series, the output of which is connected to the first input of the fourth adder, the sixth multiplier and the sixth wide-band low-pass filter, the output of which is connected to the second input of the fourth adder, the first and second inputs of the fifth multiplier are combined and connected to the output of the first intermediate frequency filter, the first and second the strokes of the sixth multiplier are combined and connected to the output of the second intermediate frequency filter, a matched filter, a third quadrator, a third electronic key and a second threshold device, the output of which is connected to the first inputs of the channel orthogonal code sequence generator and the mask orthogonal code sequence generator, connected in series to the third modulo adder two, seventh multiplier and second electronic key, the output of which is connected to the input the filter has a delay error, the output of the fourth adder is connected to the input of the matched filter and to the second input of the seventh multiplier, the output of the matched filter is connected to the input of the first inverter and the first input of the fourth electronic key, the output of the first inverter is connected to the first input of the fifth electronic key, the output of which connected to the input of the second inverter, the outputs of the second inverter and the fourth electronic key are combined and connected to the first input of the third adder modulo two, (K + 2) -th output of the generator ka of orthogonal code sequences is connected to the combined second inputs of the fourth and fifth electronic keys, the output of the controlled clock is connected to the second inputs of the third adder modulo two, the channel orthogonal code sequence generator, the masking orthogonal code sequence generator, and also to the second inputs of the fourth and fifth adders modulo two, the seventh output of the channel for selecting information allocated for synchronization of the receiver is connected to the first the input of the fourth adder is modulo two, the output of which is connected to the third input of the second correlator of the clock tracking circuit, the eighth output of the information isolation channel dedicated to synchronize the receiver is connected to the first input of the fifth adder modulo two, the output of which is connected to the third input of the first correlator circuit tracking the clock frequency. 2. The device according to claim 1, characterized in that the quadrature correlator of the information extraction channel includes a first multiplier and a first digital filter connected in series, as well as a second multiplier and a second digital filter connected in series, the first input of the first multiplier is the first input of the quadrature correlator, the first input of the second multiplier is the second input of the quadrature correlator, the second inputs of the first and second multipliers are combined and are the third input of the quadrature correlator RA, the output of the first digital filter is connected to the first input of the adder, and the output of the second digital filter through an inverter is connected to the second input of the adder, the output of the adder is the output of the quadrature correlator of the information allocation channel. 3. The device according to claim 1, characterized in that the quadrature correlator of the carrier frequency tracking circuit includes a first multiplier and a first digital filter connected in series, as well as a second multiplier and a second digital filter connected in series, the first input of the first multiplier is the first quadrature input the carrier frequency correlation circuit, the first input of the second multiplier - the second input of the carrier frequency tracking quadrature correlator, the second inputs of the first and second trans multipliers are combined and are the third input of the quadrature correlator of the carrier frequency tracking circuit, the output of the first digital filter is connected to the first input of the adder, the output of the second digital filter is connected to the second input of the adder, the output of the adder is connected to the input of the delay line, the output of which is the output of the quadrature correlator of the tracking circuit beyond the carrier frequency. 4. The device according to claim 1, characterized in that the quadrature correlator of the clock tracking circuit includes a first multiplier and a first digital filter connected in series, as well as a second multiplier and a second digital filter connected in series, the first input of the first multiplier is the first quadrature input the correlator circuit for tracking the clock frequency, the first input of the second multiplier - the second input of the quadrature correlator circuit for tracking the clock frequency, the second inputs of the first and second the multipliers are combined and are the third input of the quadrature correlator of the clock tracking circuit, the output of the first digital filter is connected to the first input of the adder, and the output of the second digital filter through the inverter is connected to the second input of the adder, the output of the adder is connected to the input of the delay line, the output of which is the output of the quadrature correlator circuit tracking the clock frequency.

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