RU2568317C1 - Broadband bias circuit of static level in transistor stages of amplification and conversion of signals - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: broadband bias circuit of static level in transistor stages of amplification and conversion of signals includes input transistor (1), the base of which is connected to input signal source (2), the collector of which is connected to the first (3) power bus, and an emitter is connected through matching resistor (4) to output of device (5), auxiliary transistor (6), the collector of which is connected to output of device (5), emitter is connected through current-stabilising bipole (7) to the second (8) bus of the power supply, and base is connected to bias voltage source (9), balancing capacitor (10), non-inverting voltage amplifier (11), the input of which is connected to the output of device (5). Output of non-inverting voltage amplifier (11) is connected to emitter of auxiliary transistor (6) through balancing capacitor (10).

EFFECT: enlarging the range of working frequencies of the bias circuit of static level.

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Description

The invention relates to the field of radio engineering and communication and can be used in amplifiers for analogue RF and microwave signals, in the structure of analog microcircuits for various functional purposes (for example, as intermediate stages of broadband operational amplifiers implemented by new and promising technologies).

In modern microelectronics, as the intermediate stages of analog microcircuits, static level matching chains are widely used, implemented on the basis of emitter or source voltage followers [1-12], as well as more complex combinations of active and passive components [7, 8, 10, 11]. As a rule, their main task is to provide an offset of 1–5 V of the static level without loss of gain at high frequencies. In practice, especially for bias circuits in microwave devices, this problem does not have a satisfactory solution because of the influence of the output stray capacitance, which is caused by the collector-base capacitances and the capacitance on the substrate of the output transistors of the circuit.

Closest to the technical nature of the claimed device is a bias circuit (DS), FIG. 1, according to patent US 4,551.642.

A significant drawback of the known device, the architecture of which is also present in many broadband amplifiers, is that it has not high enough upper cutoff frequency f _in . This is due to the negative influence of stray capacitance on the substrate (C _p ) of the output transistor and its collector-base capacitance (C _kb ). The numerical values of C _p and C _kb for technological processes having, for example, increased radiation resistance [13], are one of the main factors determining the frequency range of broadband amplifiers based on a central oscillator, FIG. one.

The main objective of the invention is to expand the operating frequency range of the static level bias circuit.

The problem is solved in that in the bias circuit of the static level, FIG. 1, containing the input transistor 1, the base of which is connected to the input signal source 2, the collector is connected to the first 3 power bus, and the emitter is connected via the terminating resistor 4 to the output of device 5, the auxiliary transistor 6, the collector of which is connected to the output of device 5, the emitter is the current-stabilizing two-terminal 7 is connected to the second 8 bus of the power source, and the base is connected to a bias voltage source 9, a correction capacitor 10, a non-inverting voltage amplifier 11, the input of which is connected to the output of the device Twa 5, new elements are provided and communications - the noninverting output of the voltage amplifier 11 is connected to the emitter of the auxiliary transistor 6 via a compensation capacitor 10.

A diagram of the CA prototype is shown in FIG. one.

 In FIG. 2 presents a diagram of the inventive device in accordance with the claims.

In FIG. 3 is a diagram of FIG. 2 in the Cadence environment on models of integrated SiGe transistors of the SG25H1 process technology.

In FIG. 4 shows the logarithmic amplitude-frequency response of the transmission coefficient of the DS, FIG. 3, at different values of the correction capacitor C _to . From the analysis of these graphs it follows that the range of operating frequencies of the CA, FIG. 3, expands 5 times.

In FIG. 5 is a diagram of a CA, FIG. 2, in the environment of PSpice on models of integrated transistors of OJSC NPP Pulsar.

In FIG. 6 shows the logarithmic amplitude-frequency response of the transmission coefficient of the DS, FIG. 5, at different values of the capacitance of the correction capacitor C _to (10). From the analysis of these graphs it follows that the range of operating frequencies of the CA, FIG. 5, expands more than 5 times.

In FIG. 7 is a diagram of a CA, FIG. 2, in the environment of PSpice on models of integrated transistors for the case when the output circuit has an additional parasitic load capacitance C ₃ = 1pF.

In FIG. 8 shows a logarithmic amplitude-frequency response of a transmission coefficient of a DS, FIG. 7, at different values of the capacitance of the correction capacitor C _to (10). From the analysis of these graphs it follows that the operating frequency range of the CA, FIG. 7, expands 7 times.

The broadband static level bias circuit in the transistor amplification and signal conversion stages, FIG. 2, contains an input transistor 1, the base of which is connected to the input signal source 2, the collector is connected to the first 3 power bus, and the emitter is connected via the terminating resistor 4 to the output of device 5, the auxiliary transistor 6, whose collector is connected to the output of device 5, the emitter the current-stabilizing two-terminal 7 is connected to the second 8 bus of the power source, and the base is connected to a bias voltage source 9, a correction capacitor 10, a non-inverting voltage amplifier 11, the input of which is connected to the output of the device and 5. The noninverting output of the voltage amplifier 11 is connected to the emitter of the auxiliary transistor 6 via a compensation capacitor 10. The capacitor 12 in the circuit of FIG. 2, simulates the effect on the operation of the DS of parasitic capacitances of the circuit associated with the output of the device 5.

Consider the operation of the CA, FIG. 2.

:In the high-frequency region, on the amplitude-frequency response of the digital signal converter, FIG. 2, the capacitor 12 begins to influence in the output circuit 5, through which the current component flows $${\dot{I}}_{12}$$

:

- комплекс тока через конденсатор 12;Where $${\dot{I}}_{12}$$

- complex current through the capacitor 12;

- комплекс выходного напряжения устройства; $${\dot{U}}_{\mathrm{at}sx}$$

- complex output voltage of the device;

- комплексное сопротивление конденсатора 12 на частоте сигнала ω.

- the complex resistance of the capacitor 12 at the frequency of the signal ω.

передается на выход неинвертирующего усилителя напряжения 11:Voltage $${\dot{U}}_{\mathrm{at}sx}$$

transmitted to the output of a non-inverting voltage amplifier 11:

where K _y is the voltage transfer coefficient of the non-inverting voltage amplifier 11.

Therefore, the current complex through the correction capacitor 10 is equal to:

- комплекс сопротивления корректирующего конденсатора 10.Where $${\dot{Z}}_{10}=\frac{\mathrm{one}}{j\omega C_{10}}$$

- resistance complex correction capacitor 10.

The current increment through the capacitor 10 is transmitted to the emitter, and then to the collector of the transistor 6. As a result, in the output circuit of the device 5 when the condition

и $${\dot{I}}_{к6}={\alpha }_6{\dot{I}}_{10}$$

, где α₆≈1 - коэффициент усиления по току эмиттера транзистора 6.mutual compensation of two currents is provided $${\dot{I}}_{12}$$

and $${\dot{I}}_{\mathrm{to}6}={\alpha }_6{\dot{I}}_{10}$$

where α ₆ ≈1 is the current gain of the emitter of transistor 6.

Ultimately, this extends the operating frequency range of the DS, FIG. 2, 5-7 times. This conclusion is confirmed by computer simulation of the CA (Fig. 4, Fig. 6, Fig. 8).

Thus, the claimed circuit design solution of the CA is characterized by a wider range of operating frequencies.

Information sources

1. Patent US 5.929.710

2. US Pat. No. 6,297,685 fig. 5, 6

3. Patent US 4.185.212

4. Patent US 4.767.946

5. Patent US 3.985.954

6. Patent US 4.142.110

7. Patent US 7.646.233

8. Patent US 4.080.539

9. Patent US 5.039.887

10. Patent US 4.743.862

11. Patent WO 96/31948

12. US Patent 6,882,294 fig. 3

13. The elemental base of radiation-resistant information-measuring systems: monograph / N.N. Prokopenko, O.V. Dvornikov, S.G. Krutchinsky; Total ed. Doctor of Technical Sciences prof. N.N. Prokopenko; FSBEI HPE “South-Ros. state un-t economics and service. " - Mines: FSBEI HPE "URGUES", 2011. - 208 p.

Claims (1)

A broadband static level bias circuit in transistor amplification and signal conversion stages, containing an input transistor (1), the base of which is connected to an input signal source (2), the collector is connected to the first (3) power bus, and the emitter is connected through a terminating resistor (4) with the output of the device (5), an auxiliary transistor (6), the collector of which is connected to the output of the device (5), the emitter is connected via a current-stabilizing two-terminal device (7) to the second (8) bus of the power source, and the base is connected to the voltage source with (9), correction capacitor (10), non-inverting voltage amplifier (11), the input of which is connected to the output of the device (5), characterized in that the output of the non-inverting voltage amplifier (11) is connected to the emitter of the auxiliary transistor (6) through the correction capacitor (10).

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