RU2421897C1 - Controlled complementary differential amplifier - Google Patents

Abstract

FIELD: electricity. ^ SUBSTANCE: controlled amplifier is the base node of modern receiving and processing systems of HF and microwave signals, analogue computing and measuring equipment. Controlled complementary differential amplifier includes the first (1) and the second (2) input transistors the collectors of which are connected to the first (3) power source, the first (4) and the second (5) output tripoles the base inputs of which are connected to each other, collector output of the first (4) output tripole is connected to the first (6) input of load circuit (7), which is matched with the second (8) power source, collector output of the second (5) output tripole is connected to the second (9) input of load circuit; emitter of the first (1) input transistor is connected to emitter input of the first (4) output tripole; emitter of the second (2) input transistor is connected to emitter input of the second (5) output tripole; at that, control input (10) of controlled pedestal current source (11) is connected to control voltage source (12). To the diagram there introduced is the first (13) and the second (14) additional transistors and additional pedestal current source (15) connected between combined base inputs of the first (4) and the second (5) output tripoles and the second (8) power source; at that, controlled pedestal current source (11) is connected between the first (3) power source and combined emitters of the first (13) and the second (14) additional transistors; base of the first (13) additional transistor is connected to emitter of the first (1) input transistor; base of the second (14) additional transistor is connected to emitter of the second (2) input transistor; collector of the first (13) additional transistor is connected to collector output of the first (4) output tripole; collector of the second (14) additional transistor is connected to collector output of the second (5) output tripole. ^ EFFECT: enlarging functional capabilities of controlled amplifier; creating the conditions at which its output voltage can under influence of control signal uy change not only its amplitude, but also phase; the possibility of performing ux and uy signal analogue multiplier on the basis of the proposed device. ^ 6 cl, 9 dwg

Description

The present invention relates to the field of radio engineering and communication and can be used in automatic gain control devices, phase detectors and modulators, in systems of phase-locked loop and frequency multiplication, or as an amplifier, the voltage transfer coefficient of which depends on the level of the control signal. The controlled amplifier is the base unit of modern systems for receiving and processing signals of the high and microwave ranges, analog computing and measuring equipment.

Currently, in analog microcircuitry as a part of electronic control systems for amplifying, mixing or multiplying signals, circuits of controlled amplifiers based on differential stages with variable static mode are widely used. Such a structure has become the basis for the construction of almost all currently known precision controlled amplifiers and analog signal multipliers. In this regard, the task of improving the parameters of this functional unit for the next-generation electronic equipment is one of the rather urgent tasks of modern microelectronics.

There are several basic differential cascade (DK) architectures. One of them (figure 1), which relates to the classical architecture, was first used in the operational amplifier µA741. Due to the high popularity of such a recreation center, more than 30 patents from different countries were issued for its modification, for example [1-30].

The closest prototype (figure 1) of the claimed device is a controlled complementary amplifier described in US patent No. 4.059.808 fig.1, containing the first 1 and second 2 input transistors, the collectors of which are connected to the first 3 power source, the first 4 and second 5 output three-terminal, the basic inputs of which are connected to each other, the collector output of the first 4 output three-terminal is connected to the first 6 input of the load circuit 7, coordinated with the second 8 power source, the collector output of the second 5 output three-terminal The input 9 of the load circuit, the emitter of the first 1 input transistor is connected to the emitter input of the first 4 output three-terminal, the emitter of the second 2 input transistor is connected to the emitter input of the second 5 output three-terminal, and the control input 10 of the controlled reference current source 11 is connected to the control voltage source 12.

The first significant drawback of the known controlled amplifier is that in the operating frequency range the phase of its output voltage does not change depending on the magnitude of the control voltage u _y . This does not allow the known device to perform the functions of a quadrant multiplier of the signals u _x and u _y .

The second significant drawback of the known device is that the control input 10 of its controlled reference current source 11, which provides electronic control of the voltage gain, is not “tied” to the common bus of power supplies 3 and 8. This significantly narrows the scope of its use.

The main objective of the invention is to expand the functionality of a controlled amplifier - creating conditions under which its output voltage can change not only its amplitude, but also its phase under the action of a control signal u _y . This will allow you to perform on the basis of the claimed device an analog multiplier of the signals u _x and u _y .

The second objective of the invention is to create conditions for electronic control of the voltage gain, at which the control voltage u _y delivers relative to the common bus power sources. The implementation of this goal allows you to perform on the basis of the claimed device not only broadband RF and microwave amplifiers with adjustable parameters, but to create more complex functional units based on it, for example, analog signal multipliers.

The third additional goal is the creation of the architecture of a controlled amplifier with a low supply voltage and electronic control of its voltage gain, as well as the possibility of practical implementation of the device using SiGe SG25H2 technology (operating voltage for n-pn transistors U _p = 1.9 V; for pnp transistors U _p = 2.8 V).

The goals are achieved by the fact that in the controlled complementary amplifier of figure 1, containing the first 1 and second 2 input transistors, the collectors of which are connected to the first 3 power supply, the first 4 and second 5 output three-terminal, the basic inputs of which are connected to each other, collector output the first 4 output three-terminal is connected to the first 6 input of the load circuit 7, coordinated with the second 8 power supply, the collector output of the second 5 output three-terminal is connected to the second 9 input of the load circuit, the emitter of the first 1 input of the second transistor is connected to the emitter input of the first 4 output three-terminal, the emitter of the second 2 input transistor is connected to the emitter input of the second 5 output three-terminal, and the control input 10 of the controlled reference current source 11 is connected to the control voltage source 12, new elements and communications are provided - the circuit is introduced the first 13 and second 14 additional transistors and an additional reference current source 15 connected between the combined base inputs of the first 4 and second 5 output three-terminal and second A power source 8, and a controlled reference current source 11 is connected between the first 3 power sources and the combined emitters of the first 13 and second 14 additional transistors, the base of the first 13 additional transistor is connected to the emitter of the first 1 input transistor, the base of the second 14 additional transistor is connected to the emitter of the second 2 input transistors, the collector of the first 13 additional transistor is connected to the collector output of the first 4 output three-terminal, the collector of the second 14 additional tra ican connected to the collector output of the second three-point 5 of the output.

The amplifier circuit of the prototype in its two modifications is presented in figure 1 and figure 2. Figure 3 shows the inventive device in accordance with claim 1, claim 2 and claim 3 of the claims.

Figure 4 shows a diagram of a controlled amplifier corresponding to claim 4, claim 5 and claim 6 of the claims.

Figure 5 shows a diagram of the inventive device in accordance with claim 1 in the computer simulation environment of Cadence on models of integrated transistors of FSUE NPP Pulsar.

In Fig.6 - Fig.9 shows the results of computer simulation of the circuit of Fig.5:

- the dependence of the gain modulus K _u on the control voltage u _y in the frequency range (Fig.6);

- the dependence of the output differential voltage of the controlled amplifier on the voltages u _x and u _y (Fig.7).

- the time dependence of the output voltage with the simultaneous exposure to two input sinusoidal voltages u _x and u _y ;

- the spectrum of the output signals of a controlled amplifier in the mixer mode u _x and u _y at f _x = 10 GHz and f _y = 1 GHz.

The controlled complementary differential amplifier of figure 2 contains the first 1 and second 2 input transistors, the collectors of which are connected to the first 3 power supply, the first 4 and second 5 output three-terminal, the basic inputs of which are connected to each other, the collector output of the first 4 output three-terminal is connected to the first 6 by the input of the load circuit 7, coordinated with the second 8 power supply, the collector output of the second 5 output three-terminal network is connected to the second 9 input of the load circuit, the emitter of the first 1 input transistor is connected with the emitter input of the first 4 output three-terminal, the emitter of the second 2 input transistor is connected to the emitter input of the second 5 output three-terminal, and the control input 10 of the controlled reference current source 11 is connected to the control voltage source 12. The first 13 and second 14 additional transistors and additional a reference current source 15 connected between the combined base inputs of the first 4 and second 5 output triples and a second 8 power source, wherein the controlled reference voltage OKA 11 is connected between the first 3 power supply and the combined emitters of the first 13 and second 14 additional transistors, the base of the first 13 additional transistor is connected to the emitter of the first 1 input transistor, the base of the second 14 additional transistor is connected to the emitter of the second 2 input transistor, the collector of the first 13 additional transistor connected to the collector output of the first 4 output three-terminal, the collector of the second 14 additional transistor connected to the collector output of the second 5 output tre hpole.

In Fig.2, in accordance with claim 2 of the claims, the controlled reference current source 11 comprises a first 16 current-stabilizing two-terminal device connected between the first 3 power source and the combined emitters of the first 13 and second 14 additional transistors, as well as a scaling resistor 17 connected between the control input 10 of the controlled current source 11 and the combined emitters of the first 13 and second 14 additional transistors.

In Fig. 3, in accordance with claim 3 of the claims, the first 4 output tri-terminal contains the first 18 auxiliary transistor, the emitter of which is connected to the emitter of the first 1 input transistor and is the emitter input of the first 4 output three-terminal, and the collector is connected to the first 6 input of the circuit load 7 and is the collector output of the first 4 output three-terminal, the first auxiliary pn junction 19 connected between the emitter and the base of the first auxiliary transistor 18, the base of which is the base input of the first 4 the output three-terminal, the second 5 output three-terminal contains a second 20 auxiliary transistor, the emitter of which is connected to the emitter of the second 2 input transistor and is the emitter input of the second 5 output three-terminal, and the collector is connected to the second 9 input of the load circuit 7 and is the collector output of the second 5 output three-terminal, the second auxiliary pn junction 21 connected between the emitter and the base of the second 20 auxiliary transistor, the base of which is the base input of the second 5 output three-terminal but.

In Fig. 4, in accordance with claim 4, the collectors of the first 1 and second 2 input transistors are connected to the first 3 power source through the third 22 auxiliary pn junction and, in addition, are connected to the base of the third 23 auxiliary transistor, emitter which is connected to the first 3 power source, and the collector is connected to the combined base inputs of the first 4 and second 5 output three-terminal devices.

In addition, in Fig. 4, in accordance with claim 5, the load circuit 7 comprises first 24 and second 25 LC load cells included respectively between the first 6 input of the load circuit and the second 8 power source, and also between the second 9 the input of the load circuit 7 and the second 8 power source.

In addition, in Fig. 4, in accordance with claim 6, the first 4 output three-terminal contains a fourth 26 auxiliary transistor, the emitter of which is the emitter input of the first 4 output three-terminal, the base is its basic input, and the collector is the collector output of the first 4 output three-terminal, the second 5 output three-terminal contains a fifth 27 auxiliary transistor, the emitter of which is the emitter input of the second 5 output three-terminal, the base is its basic input, and the collector is the collector output of the second 5 output three-terminal.

Consider the operation of the claimed device in the mode of a controlled voltage amplifier u _x (figure 3).

In static mode, at zero control voltage (u _y = 0), the currents through the scaling resistor 17 are close to zero.

Each of the alternating currents of the first 6 and second 9 inputs of the load circuit 7 is composed of two antiphase components:

where i _k18 , i _k13 , i _k20 , i _k14 are the collector currents of transistors 18, 13, 20 and 14 with a positive increment u _x at input Vx.1.

By selecting the static currents of the two-terminal circuits 11 and 15, which determine the ac amplification of the differential stages on transistors 1, 2, 13-14 and the differential stage on transistors 1, 2, 18, 20, it is possible to obtain a zero value of the output differential voltage of the controlled amplifier of FIG. 3

where R ₂₄ = R ₂₅ - the resistance of the two-terminal networks 24 and 25 of the load circuit 7 (in the particular case of resistors).

If the control voltage u _y (12) is incremented u _y> 0, this causes an increase in the sum current common emitter circuit of transistors 13 and 14 by an amount i _y and, consequently, an increase in voltage gain of the differential stage transistors 1, 2 , 13, 14, inverting the phase u _x to the output of Output 1. Therefore, in formulas (1) and (2), the currents i _k13 and i _k14 begin to exceed the corresponding value of the currents i _k18 and i _k20 , which are independent of u _y , and the output differential voltage of the controlled amplifier will have the phase φ _Σ = φ _x +180 °, where φ _x is the phase of the input voltage u _x . The amplitude of the output differential voltage in this case with u _x = const will also increase in proportion to u _y (Fig.6).

If the voltage u _{y is} negative, then the total current of the common emitter circuit of the transistors 13 and 14 decreases. In the circuit of FIG. 3, in this case, the currents i _k18 and i _k20 begin to prevail, and the output differential voltage of the amplifier will have the same phase as the output voltage u _x at input Vx.1.

Thus, the output voltage in the inventive device varies depending on u _y not only in amplitude but also in phase, which is one of the conditions for implementing on its basis not only a controlled amplifier, but a multiplier of two signals u _x and u _y (Fig. 7, Fig. 8) or their mixer (Fig. 9).

Similarly, the circuit of Fig. 4 works, in which the load circuit 7 contains LC-oscillatory circuits that select the necessary spectral components after mixing the signals u _x and u _y (Fig. 9).

A remarkable feature of the circuits of Fig. 3, Fig. 4 is the suppression of the transmission of the control signal u _y to the differential output of a controlled amplifier, which is very important for constructing a mixer and / or multiplier of signals u _x and u _y .

The suppression coefficient of the control signal can have especially high values during the special construction of a controlled reference current source 10, in which changes in the current i _y are transmitted through the resistor 17 via a parallel (independent of u _x ) channel to the load circuit 7 and compensate for the current increments i _y / 2 in the collector circuits of transistors 13-14.

Thus, the claimed complementary differential amplifier has electronic gain control, the phase of which varies depending on the value of u _y (Fig.6). Moreover, the control signal u _y , as well as the input signal u _x are applied to the corresponding inputs relative to the common bus (without isolation capacitors).

As follows from the consideration of the graphs of Fig.7, Fig.8, Fig.9, the claimed device performs the functions of an analog multiplier of small signals u _x and u _y .

The range of multiplication on the channel "X" can be expanded in the traditional way - the use of input logarithmic diodes.

BIBLIOGRAPHIC LIST

1. US Patent No. 3,786.362

2. US patent No. 4.030.044

3. US patent No. 4.059.808, figure 5

4. US Patent No. 4,286.227

5. Auth. testimonial. USSR No. 375754, H03f 3/38

6. Auth. testimonial. USSR No. 843164, H03f 3/30

7. US Patent No. 3,660.773

8. US Patent No. 4,560.948

9. RF patent No. 2930041, H03f 1/32

10. Japan Patent No. 57-5364, H03f 3/343

11. Patent of Czechoslovakia No. 134845, cl. 21a ² 18/08

12. Patent of Czechoslovakia No. 134849, cl. 21a ² 18/08

13. Czechoslovak Patent No. 135326, cl. 21a ² 18/08

14. US Patent No. 4,389.579

15. England patent No. 1543361, H3T

16. US patent No. 5.521.552 (figa)

17. US Patent No. 4.059.808

18. US Patent No. 5,789.949

19. US Patent No. 4,453.134

20. US Patent No. 4,760.286

21. Auth. testimonial. USSR No. 1283946

22. RF patent No. 2019019

23. US Patent No. 4.3 89.579

24. US Patent No. 4,453.092

25. US Patent No. 3,566.289

26. US patent No. 4.059.808 (figure 2)

27. US Patent No. 3,649,926

28. US patent No. 4.714.894 (figure 1)

29. Matavkin V.V. High-speed operational amplifiers. - M.: Radio and Communications, 1989.

30. Herpy M. Analog Integrated Circuits. - M.: Radio and Communications, 1983, p. 174, Fig. 5.52.

Claims (6)

1. A controlled complementary differential amplifier containing the first (1) and second (2) input transistors, the collectors of which are connected to the first (3) power source, the first (4) and second (5) output three-terminal, the basic inputs of which are connected to each other , the collector output of the first (4) output three-terminal is connected to the first (6) input of the load circuit (7), matched with the second (8) power supply, the collector output of the second (5) output three-terminal is connected to the second (9) input of the load circuit, emitter first (1) input transistor the ora is connected to the emitter input of the first (4) output three-terminal network, the emitter of the second (2) input transistor is connected to the emitter input of the second (5) output three-terminal network, and the control input (10) of the controlled reference current source (11) is connected to the control voltage source (12 ), characterized in that the first (13) and second (14) additional transistors and an additional reference current source (15) are connected between the combined base inputs of the first (4) and second (5) output three-terminal and the second (8) the source power, and a controlled reference current source (11) is connected between the first (3) power source and the combined emitters of the first (13) and second (14) additional transistors, the base of the first (13) additional transistor is connected to the emitter of the first (1) input transistor, the base of the second (14) additional transistor is connected to the emitter of the second (2) input transistor, the collector of the first (13) additional transistor is connected to the collector output of the first (4) output three-terminal, the collector of the second (14) additional transistor the ora is connected to the collector output of the second (5) output three-terminal network. 2. A controlled complementary differential amplifier according to claim 1, characterized in that the controlled reference current source (11) comprises a first (16) current-stabilizing two-terminal device connected between the first (3) power source and the combined emitters of the first (13) and second (14) additional transistors, as well as a scaling resistor (17), connected between the control input (10) of the controlled current source (11) and the combined emitters of the first (13) and second (14) additional transistors. 3. The controlled complementary differential amplifier according to claim 1, characterized in that the first (4) output three-terminal contains a first (18) auxiliary transistor, the emitter of which is connected to the emitter of the first (1) input transistor and is the emitter input of the first (4) output three-terminal and the collector is connected to the first (6) input of the load circuit (7) and is the collector output of the first (4) output three-terminal network, the first auxiliary pn junction (19) connected between the emitter and the base of the first auxiliary transistor (18), which is the basic input of the first (4) output three-terminal, the second (5) output three-terminal contains a second (20) auxiliary transistor, the emitter of which is connected to the emitter of the second (2) input transistor and is the emitter input of the second (5) output three-terminal, and the collector connected to the second (9) input of the load circuit (7) and is the collector output of the second (5) output three-terminal network, the second auxiliary pn junction (21) connected between the emitter and the base of the second (20) auxiliary transistor, the base of which o is the basic input of the second (5) output three-terminal network. 4. The controlled complementary differential amplifier according to claim 1, characterized in that the collectors of the first (1) and second (2) input transistors are connected to the first (3) power source through the third (22) auxiliary pn junction and, in addition, connected to the base of the third (23) auxiliary transistor, the emitter of which is connected to the first (3) power source, and the collector is connected to the combined base inputs of the first (4) and second (5) output three-terminal devices. 5. The controlled complementary differential amplifier according to claim 1, characterized in that the load circuit (7) contains the first (24) and second (25) LC load elements connected respectively between the first (6) input of the load circuit and the second (8) power source, as well as between the second (9) input of the load circuit (7) and the second (8) power source. 6. The controlled complementary differential amplifier according to claim 4, characterized in that the first (4) output three-terminal contains a fourth (26) auxiliary transistor, the emitter of which is the emitter input of the first (4) output three-terminal, the base is its basic input, and the collector is the collector output of the first (4) output three-terminal, the second (5) output three-terminal contains a fifth (27) auxiliary transistor, the emitter of which is the emitter input of the second (5) output three-terminal, the base is its basic input, and the collector - the collector output of the second (5) output three-point.

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