RU2439694C1 - Analogue voltage multiplier - Google Patents

Abstract

FIELD: electricity. ^ SUBSTANCE: analogue voltage multiplier contains multiplying Gilbert cell, balanced load circuit, voltage-current convertor, the first and second front-end transistors, the first and second p-n junctions in logarithmic form, potential matching circuit, zoom resistors, the first and second reference voltage sources, the first and second groups of auxiliary transistors. ^ EFFECT: extension of operating frequency range for analogue voltage multiplier. ^ 8 dwg

Description

The present invention relates to the field of radio engineering and communication and can be used in automatic gain control devices, phase detectors and modulators, as well as in phase locked loop and frequency multiplication systems or as an amplifier, the voltage transfer coefficient of which depends on the level of the control signal. The analog multiplier (APN) is the basic unit of modern systems for the reception and processing of high-frequency and microwave-frequency signals, analogue computing and measuring equipment, which makes it possible to solve the problems of distinguishing difference frequencies and attenuating signals. APN is an integral part of quadrature modulators and demodulators, as well as synchronous filters. High-linear broadband APN can serve as the base cell of non-linear SF blocks of “systems on a chip”.

The analog voltage multiplier (APN) of modern communication and telecommunication systems is implemented mainly on the basis of the Gilbert cell multiplier, which has been improved in more than 50 patents of leading microelectronic companies (see, for example, [1-36]). The alleged invention relates to this class of devices.

On the basis of the Gilbert cell, not only voltage multipliers are realized, but also controlled amplifiers and mixers (mixers) of the RF and microwave ranges. In this sense, the APN is the basic functional unit of modern microelectronics, which determines the quality indicators of many communication systems.

The closest prototype of the claimed device is an analog voltage multiplier (APN), (Fig. 1), considered in the monograph by E.I. Starchenko “Analog voltage multipliers” - Mines: Publishing House of YURGUES, 2006. - 57 s, p. 12, Fig. 2.2 . In addition, this structure of the APN is presented in the textbook for universities VN Nogin "Analog electronic devices." - M.: Radio and Communications, 1992. - 304 s, p. 260, Fig. 16.11, as well as in US Pat. Known APN contains a multiplier cell of Gilbert 1, the antiphase current outputs of which 2 and 3 are connected to the first 4 bus of the power source through a symmetrical load circuit 5, the first 6 and second 7 current inputs of channel "Y" of the multiplier cell of Gilbert 1, connected to the corresponding current outputs of the converter “Voltage-current” of channel “Y” 8, the first 9 and second 10 potential inputs of channel “X” of the Gilbert cell 1, connected to the collectors of the corresponding first 11 and second 12 input transistors, the first 13 and second 14 arithmetic pn junctions, the first conclusions of which are combined and connected through the potential matching circuit 15 to the bus of the first 4 power supply, the second output of the first 13 logarithmic pn junction connected to the collector of the first 11 input transistor, and the second output of the second 14 logarithmic pn junction connected to the collector of the second 12 input transistor, a scaling resistor 16 connected between the emitters of the first 11 and second 12 input transistors, the first 17 reference current source connected between the emitter of the first 11 input the first transistor and the second power supply bus 18, the second reference current source 19 connected between the emitter of the second input transistor 12 and a second 18 power source bus.

A significant drawback of the known voltage multiplier (APN) is that it has a relatively low operating frequency range, which is limited by the parasitic capacitances of the transistors used (collector-base capacitance and substrate capacitance).

The main objective of the invention is to expand the range of operating frequencies (bandwidth) APN.

This goal is achieved by the fact that in the APN containing the Gilbert multiplying cell 1, the antiphase current outputs of which 2 and 3 are connected to the first 4 bus of the power supply through a symmetrical load circuit 5, the first 6 and second 7 current inputs of channel “Y” of the Gilbert multiplying cell 1 connected to the corresponding current outputs of the voltage-current converter of channel “Y” 8, the first 9 and second 10 potential inputs of channel “X” of the Gilbert cell 1, connected to the collectors of the corresponding first 11 and second 12 input tr nzistors, the first 13 and second 14 logarithmic pn junctions, the first conclusions of which are combined and connected through the potential matching circuit 15 to the bus of the first 4 power supply, the second output of the first 13 logarithmic pn junction connected to the collector of the first 11 input transistor, and the second output of the second 14 logarithmic pn junction connected to the collector of the second 12 input transistor, a scaling resistor 16 connected between the emitters of the first 11 and second 12 input transistors, the first 17 reference current source included between the emitter of the first 11 input transistor and the second 18 bus of the power source, the second 19 reference current source connected between the emitter of the second 12 input transistor and the second 18 bus of the power source, new elements and connections are provided - the first 20 and second 21 groups of auxiliary transistors are introduced into the circuit moreover, the collectors n> 2 of parallel connected auxiliary transistors of the first 20 group are connected to the emitter of the first 11 input transistor, the collectors n> 2 of parallel connected auxiliary transistors of the second 2 1 groups are connected to the emitter of the second 12 input transistor, emitters and bases of all auxiliary transistors of the first 20 and second 21 groups are combined and connected to the second 18 bus of the power source.

The drawing of figure 1 shows a diagram of the APN prototype.

The drawing of figure 2 presents a diagram of a classical multiplying cell Gilbert (1), which is implemented on transistors 33 ÷ 36.

The drawing of figure 3 shows a diagram of the claimed APN in accordance with the claims.

The drawing of Fig. 4 shows a diagram of the analog multiplier of Fig. 2 in a Cadence environment on SiGe models of integrated transistors with frequency range extension circuits implemented on the basis of the first 20 and second 21 groups of auxiliary transistors.

The drawing of Fig.5 shows the dependence of the gain of the APN of Fig.4 on the frequency using the first 20 and second 21 groups of auxiliary transistors with different areas of emitter junctions with a resistance of the scaling resistor 16 equal to R16 = 200 Ohms and the control voltage along the channel "Y" equal to Vу = 100 mV.

The drawing of Fig.6 shows the dependence of the gain of the APN of Fig.4 on the frequency with the resistance of the scaling resistor 16 R16 = 200 Ohms and another control voltage on the channel "Y" equal to Vу = 200 mV.

The drawing of Fig.7 illustrates the dependence of the gain of the APN on the frequency when connecting the first 20 and second 21 groups of auxiliary transistors with different areas of emitter junctions with a resistance of the scaling resistor 16 R16 = 1 kOhm and a control voltage along the channel "Y" equal to Vу = 100 mV.

The drawing of Fig. 8 shows the dependence of the gain of the APN on the frequency when connecting the first 20 and second 21 groups of auxiliary transistors with different areas of emitter junctions with a resistance of the scaling resistor 16 R16 = 1 kOhm and other control voltage along the channel "Y" equal to Vу = 200 mV

The inventive APN of Fig. 3 contains a classical Gilbert multiplying cell 1 (Fig. 2), the antiphase current outputs of which 2 and 3 are connected to the first 4 bus of the power supply through a symmetrical load circuit 5, the first 6 and second 7 current inputs of the channel “Y” of the multiplying cell Gilbert 1, connected to the corresponding current outputs of the voltage-current converter of channel “Y” 8, the first 9 and second 10 potential inputs of channel “X” of the Gilbert 1 multiplying cell, connected to the collectors of the corresponding first 11 and second 12 input transistors s, the first 13 and second 14 logarithmic pn junctions, the first conclusions of which are combined and connected through the potential matching circuit 15 to the bus of the first 4 power supply, the second output of the first 13 logarithmic pn junction connected to the collector of the first 11 input transistor, and the second output of the second 14 the logarithmic pn junction is connected to the collector of the second 12 input transistor, a scaling resistor 16 connected between the emitters of the first 11 and second 12 input transistors, the first 17 is a reference current source connected between Mitter first 11 and second input transistor 18, the power supply bus, the second reference current source 19 connected between the emitter of the second input transistor 12 and a second 18 power source bus. The first 20 and second 21 groups of auxiliary transistors are introduced into the circuit, with collectors n> 2 of parallel connected auxiliary transistors of the first 20 group connected to the emitter of the first 11 input transistor, collectors n> 2 of parallel connected auxiliary transistors of the second 21 group connected to the emitter of the second 12 input transistor , emitters and bases of all auxiliary transistors of the first 20 and second 21 groups are combined and connected to the second 18 bus power supply.

In the particular case of FIG. 3, the first 17 and second 19 sources of the reference current are made on transistors 22 and 23. However, in some cases, the authors recommend using relatively high-resistance resistors as these elements.

In the circuit of FIG. 3, a symmetrical load circuit 5 is implemented on the basis of collector resistors 24 and 25. In other switching circuits, these may be inductors or oscillatory circuits.

Capacitors 26 and 27 in the drawing of figure 3 characterize the output capacitance of transistors 22 and 23.

The voltage-current Converter channel "Y" (figure 3) is made according to the traditional scheme on transistors 28 and 29, a resistor 30, current-stabilizing two-terminal networks 31 and 32.

In the drawing of figure 2, the Gilbert cell multiplier 1 is made according to the classical architecture and contains transistors 33 ÷ 36. As a potential matching circuit 15, zener diodes, resistors, or diodes can be used.

Consider the operation of the APN of Fig.3.

и управление этими токами величиной коэффициента усиления по напряжению дифференциальных каскадов на транзисторах 33, 36 и 34, 35 (фиг.2). В схеме фиг.3 при увеличении тока первого 6 токового входа на величину

и уменьшении тока второго 7 токового входа на величину

коэффициент усиления по напряжению каскада на транзисторах 35, 36 (фиг.2) увеличивается, а каскада на транзисторах 37, 38 (фиг.2) уменьшается. Поэтому, переменное выходное напряжение АПН пропорционально произведению напряжений u_х и u_у:To implement the function of multiplying two voltages u _x and u _y in the circuit of figure 3, it is necessary to convert the control voltage u _y with slope S into two antiphase currents using the voltage-current converter of channel "Y" 8

and controlling these currents with the magnitude of the voltage gain of the differential stages on transistors 33, 36 and 34, 35 (FIG. 2). In the circuit of figure 3 with increasing current of the first 6 current input by

and decreasing the current of the second 7 current input by

the voltage gain of the cascade on transistors 35, 36 (FIG. 2) increases, and the cascade on transistors 37, 38 (FIG. 2) decreases. Therefore, the AC output voltage is proportional to the product of the voltage u _x and u _y :

where R _{H. ECV} is the equivalent resistance of the symmetrical load circuit 5;

φ _t ≈ 26 mV - temperature potential.

A remarkable feature in the APN of Fig. 3 is that it provides mutual compensation for the influence on the amplitude-frequency characteristic of the collector junction capacitance of the transistor 11 (12) and auxiliary transistors of the first 20 (second 21) group, as well as the Gilbert cell transistors (1) , which reduces the error in the multiplication of u _x and u _y in the high frequency range (f> 10 GHz). Moreover, due to the high identity of the transistors and their stray capacitances, the conditions of mutual compensation are not violated in the operating temperature ranges. In practical schemes, the number of elementary transistors included in the first 20 and second 21 groups of auxiliary transistors lies in the range n = 2 ÷ 6 and depends on the selected area of the emitter junctions and the geometry of the elementary transistors.

Indeed, the analysis of the graphs of FIGS. 5 to 8 shows that the gain in the upper cutoff frequency of the gain (in the -3dB level), which provides the introduction of the first 20 and second 21 groups of auxiliary transistors, lies in the range from 8 GHz to 12 GHz ( depending on a given level of non-uniformity of the amplitude-frequency characteristic). This allows, due to the optimal choice of the number n of elementary transistors included in the first 20 and second 21 groups of auxiliary transistors and the areas of their emitter junctions, to adjust the amplitude-frequency characteristic of the arrester in the high frequency region and to provide the upper cutoff frequency of 16 ÷ 24 GHz for SiGe technologies SGB25VD , instead of 9 ÷ 10 GHz.

Thus, the proposed technical solution is characterized by higher quality parameters in the frequency range.

BIBLIOGRAPHIC LIST

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Claims (1)

An analog voltage multiplier containing a Gilbert multiplier cell (1), the antiphase current outputs of which (2) and (3) are connected to the first (4) bus of the power supply through a symmetrical load circuit (5), the first 6 and second (7) channel current inputs Gilbert's “Y” multiplying cell (1) connected to the corresponding current outputs of the voltage-current converter of channel “Y” (8), the first (9) and second (10) potential inputs of channel “X” of the Gilbert multiplying cell (1) associated with the collectors of the corresponding first (11) and second (12) inputs transistors, the first (13) and second (14) logarithmic pn junctions, the first conclusions of which are combined and connected through the potential matching circuit (15) to the bus of the first (4) power supply, the second output of the first (13) logarithmic pn junction connected to the collector of the first (11) input transistor, and the second output of the second (14) logarithmic pn junction is connected to the collector of the second (12) input transistor, a scaling resistor (16) connected between the emitters of the first (11) and second (12) input transistors, the first (17) source of supports current connected between the emitter of the first (11) input transistor and the second (18) power supply bus, the second (19) reference current source connected between the emitter of the second (12) input transistor and the second (18) power supply bus, characterized in that the first (20) and second (21) groups of auxiliary transistors are introduced into the circuit, and the collectors n> 2 of the auxiliary transistors connected in parallel to the first (20) group are connected to the emitter of the first (11) input transistor, the collectors n> 2 of the auxiliary transistors connected in parallel Hur second (21) of the group connected to the emitter of the second (12) input transistor, the emitters and bases of the first auxiliary transistor (20) and second (21) groups are joined and bound to the second (18) power supply bus.

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