RU2394358C1 - Low-voltage analogue voltage multiplier - Google Patents

Abstract

FIELD: radio engineering. ^ SUBSTANCE: low-voltage analogue voltage multiplier includes first (1) differential stage (DS), second (7) DS differential stage; first (2) and second (3) current outputs of first (1) DS are connected to second (9) and first (8) current outputs respectively of second (7) DS; second (5) potential input of first (1) DS is connected to first (10) potential input of second (7) DS and connected to first (13) input of "X" multiplication channel; first (4) potential input of first (1) DS is connected to second (11) potential input of second (7) DS and connected to second (14) input of "X" multiplication channel; current input (6) of first (1) DS and current input (12) of second (7) DS are connected to first (15) power supply (PS) respectively through first (16) and second (17) current-stabilising bipoles; first (2) and second (3) current outputs of first (1) DS are connected to load circuit (19); at that, analogue multiplier has also first (20) input of "Y" multiplication channel, second (21) input of "Y" multiplication channel. To the scheme there introduced is first (22), second (23), third (24) and fourth (25) auxiliary resistors (R); first (26) and second (27) directly offset p-n junctions, first input 20 of "Y" multiplication channel is connected to current input (6) in common emitter circuit of first (1) DS through in-series connected third R and first (26) directly offset p-n junction; second input (21) of "Y" multiplication channel is connected to current input (12) in common emitter circuit of second (7) DS through in-series connected fourth (25) R and second (27) directly offset p-n junction; at that, first (28) common assembly of third (24) R and first (26) directly offset p-n junction is connected through first (22) R to second (18) PS, and second (29) common assembly of the fourth R and second (27) directly offset p-n junction is connected through second (23) R to second (18) PS. ^ EFFECT: reduction of supply voltage to less than 1,5 V. ^ 4 dwg

Description

The present invention relates to the field of radio engineering and communication and can be used in automatic gain control devices, phase detectors and modulators, as well as in phase locked loop and frequency multiplication systems or as an amplifier, the voltage transfer coefficient of which depends on the level of the control signal. The analog multiplier (APN) is the basic unit of modern systems for the reception and processing of signals of the high and microwave ranges, analog computing and measuring equipment, it allows us to solve the problems of allocating the difference frequency, attenuation of signals. APN is an integral part of quadrature modulators and demodulators, as well as synchronous filters. High-linear broadband APN can serve as a base cell of nonlinear SF blocks of systems on a chip.

The analog voltage multiplier is implemented mainly on the basis of the Gilbert cell multiplier, which has been improved in more than 30 patents of leading microelectronic companies (see, for example, [1-36]). The present invention relates to this class of devices.

The closest prototype of the claimed device is an analog voltage multiplier (Fig. 1), discussed in US patent application No. 2006/0232334, fig. 1, comprising a first 1 differential stage having first 2 and second 3 current outputs, first 4 and second 5 potential inputs and current input 6 in the common emitter circuit of the first 1 differential stage, the second 7 differential stage having first 8 and second 9 current outputs, the first 10 and second 11 potential inputs and current input 12 in the common emitter circuit of the second 7 differential stage, moreover, the first 2 current output of the first 1 differential stage is connected to the second 9 current output of the second 7 differential stage, and the second 3 current output of the first 1 differential stage is connected to the first 8 current output of the second 7 differential stage, the second 5 potential input of the first 1 differential stage is connected to the first 10 potential input of the second 7 differential cascade and is connected to the first 13 input of the multiplication channel "X", the first 4 potential input of the first 1 differential cascade is connected to the second 11 potential input of the second 7 differential cascade and connected to the second 14 input of the multiplication channel "X", the current input 6 of the first 1 differential cascade is connected to the first 15 power source through the first 16 current-stabilizing two-terminal, the current input 12 of the second 7 differential cascade is connected to the first 15 source power supply through the second 17 current-stabilizing two-terminal, the first 2 and second 3 current outputs of the first 1 differential stage are connected to the load circuit 19, and the analog multiplier also has the first 20 course of the channel multiplication «Y», multiplying the second input 21 «Y» channel.

A significant drawback of the known multiplier is that it is not operable with low-voltage power, for example, E _p = ± 1.5 V. This is due to its architecture, which requires a supply voltage E _p ≥ ± (3U _eB ) ≈ 2.1 V, where U _eb = 0.7 ÷ 0.8 V is the emitter-base voltage of a bipolar transistor.

The main objective of the invention is to ensure the operation of the APN at supply voltages less than 1.5 V (performing, for example, the APN on low-voltage SiGe transistors of the SGB25VD process technology).

This goal is achieved by the fact that in the APN containing the first 1 differential stage having the first 2 and second 3 current outputs, the first 4 and second 5 potential inputs and current input 6 in the common emitter circuit of the first 1 differential stage, the second 7 differential stage having the first 8 and second 9 current outputs, the first 10 and second 11 potential inputs and current input 12 in the common emitter circuit of the second 7 differential stage, the first 2 current output of the first 1 differential stage connected to the second 9 current output of the second 7th differential stage, and the second 3 current output of the first 1 differential stage is connected to the first 8 current output of the second 7 differential stage, the second 5 potential input of the first 1 differential stage is connected to the first 10 potential input of the second 7 differential stage and connected to the first 13 channel input multiplication "X", the first 4 potential input of the first 1 differential stage is connected to the second 11 potential input of the second 7 differential stage and connected to the second 14 channel input X, the current input 6 of the first 1 differential stage is connected to the first 15 power supply through the first 16 current-stabilizing two-terminal device, the current input 12 of the second 7 differential stage is connected to the first 15 power source through the second 17 current-stabilizing two-terminal device, the first 2 and second 3 current outputs the first 1 differential stage is connected to the load circuit 19, and the analog multiplier also has the first 20 input of the multiplication channel "Y", the second 21 input of the multiplication channel "Y", new elements and communications are provided - the first 22, second 23, third 24 and fourth 25 auxiliary resistors are introduced into the circuit, the first 26 and second 27 are directly biased pn junctions, the first input 20 of the multiplication channel “Y” is connected to current input 6 in the common emitter circuit of the first 1 differential stage through connected the third 24 auxiliary resistor and the first 26 directly biased pn junction, the second input 21 of the multiplication channel "Y" is connected to the current input 12 in the common emitter circuit of the second 7 differential stage through a fourth fourth 25 auxiliary connected in series the resistor and the second 27 directly biased pn junction, the first 28 common node of the third 24 auxiliary resistor and the first 26 directly biased pn junction connected through the first 22 auxiliary resistor to the second 18 power supply, and the second 29 common node of the fourth 25 auxiliary resistor and second 27 a directly biased pn junction is connected through a second 23 auxiliary resistor to a second 18 power supply.

The drawing of figure 1 shows a diagram of the APN prototype, and in the drawing of figure 2 is a diagram of the claimed APS in accordance with the claims.

The drawing of Fig. 3 shows the circuit of the APN of Fig. 2 in the computer simulation environment PSpice on the models of integrated transistors of the Federal State Unitary Enterprise NPP "Pulsar", and Fig. 4 shows the dependence of its output voltage on the voltage at the inputs of the channels "X" and "Y". This mode characterizes the multiplying properties of the APN. These graphs show that the claimed APN is a four-quadrant multiplier. Moreover, the error in the multiplication of γ can be quite small (γ≤0.2%).

The inventive APN of FIG. 2 comprises a first 1 differential stage having first 2 and second 3 current outputs, first 4 and second 5 potential inputs and current input 6 in a common emitter circuit of the first 1 differential stage, second 7 differential stage having first 8 and second 9 current outputs, the first 10 and second 11 potential inputs and current input 12 in the common emitter circuit of the second 7 differential stage, and the first 2 current output of the first 1 differential stage is connected to the second 9 current output of the second 7 differential stage kada, and the second 3 current output of the first 1 differential stage is connected to the first 8 current output of the second 7 differential stage, the second 5 potential input of the first 1 differential stage is connected to the first 10 potential input of the second 7 differential stage and connected to the first 13 input of the multiplication channel "X ", The first 4 potential input of the first 1 differential stage is connected to the second 11 potential input of the second 7 differential stage and connected to the second 14 input of the multiplication channel" X ", the current input 6 is first about 1 differential cascade is connected to the first 15 power supply through the first 16 current-stabilizing two-terminal device, the current input 12 of the second 7 differential cascade is connected to the first 15 power supply through the second 17 current-stabilizing two-terminal device, the first 2 and second 3 current outputs of the first 1 differential stage are connected to the load circuit 19, wherein the analog multiplier also has a first 20 input of the multiplication channel “Y”, a second 21 input of the multiplication channel “Y”. The first 22, second 23, third 24 and fourth 25 auxiliary resistors are introduced into the circuit, the first 26 and second 27 are directly biased pn junctions, the first input 20 of the multiplication channel “Y” is connected to current input 6 in the common emitter circuit of the first 1 differential stage through in series connected the third 24 auxiliary resistor and the first 26 directly biased pn junction, the second input 21 of the multiplication channel "Y" is connected to the current input 12 in the common emitter circuit of the second 7 differential cascade through a fourth fourth 25 auxiliary connected in series the resistive resistor and the second 27 directly biased pn junction, the first 28 common node of the third 24 auxiliary resistor and the first 26 directly biased pn junction connected through the first 22 auxiliary resistor to the second 18 power supply, and the second 29 common node of the fourth 25 auxiliary resistor and second 27 a directly biased pn junction is connected through a second 23 auxiliary resistor to a second 18 power supply.

Consider the operation of the APN of figure 2.

In the static mode (u _x = 0, u _y = 0), the emitter currents of the transistors of the first 1 and second 7 differential stages are set by two-terminal circuits 16 and 22, 17 and 23. In this case, the input currents of channel “Y” (currents through resistors 24 and 25) are close to zero.

канала «Y». В заявляемой схеме АПН этот эффект реализуется следующим образом.To perform the operation of multiplying two voltages u _x and u _y in the APN of figure 2, it is necessary to provide an antiphase change in currents in the common emitter circuits 6 and 12 of the differential stages under the action of voltages u _y and

channel "Y". In the claimed circuit APN, this effect is implemented as follows.

получают приращение, а u_x≈0, то ток

через резистор 24 и ток

через резистор 25 изменяются пропорционально u_у:If u _y and

get increment, and u _x ≈0, then the current

through resistor 24 and current

through the resistor 25 vary in proportion to u _y :

where R ₂₄ , R ₂₅ - resistance of the resistors 24, 25 (R ₂₄ = R ₂₅ >> r _e )

- крутизна преобразования напряжения u_у в токи

,

;

- the steepness of the conversion of voltage u _y into currents

,

;

r _ei is the differential resistance pn of the transitions of the circuit.

Therefore, the voltage gain K _{u1 of} cascade 1 decreases, and cascade 7 (K _u2 ) increases:

where I ₁ = I ₇ is the total static current of the emitters of the transistors of the first 1 and second 7 differential stages;

φ _T ≈25 mV - temperature potential;

R _n.Eq - equivalent load resistance 19 _ALP in node 9.

Therefore, the AC output voltage is proportional to the product of u _x and u _y :

идентичны, что расширяет полосу пропускания АПН особенно при малых величинах u_у, u_x.It should be noted that in the circuit of figure 2, the voltage transmission channels u _x from signal sources u _x and

identical, which extends the passband of the APN especially with small values of u _y , u _x .

The circuit of figure 2 has small values of parasitic capacitance in nodes 6 and 12, which improves its multiplying properties in the high frequency region on the channel "X".

в эмиттерах транзисторов первого 1 дифференциального каскада их коллекторные токи изменяются пропорционально u_у. Однако противофазно изменяются и коллекторные токи транзисторов второго 7 каскада, что стабилизирует статическое напряжение на резисторах цепи нагрузки 19.A remarkable feature of the circuit of figure 2 is the suppression of the transmission of the signal u _y to the outputs Vykh.1 and Vykh.2. Indeed, when the current changes

in the emitters of the transistors of the first 1 differential stage, their collector currents vary in proportion to u _y . However, the collector currents of the transistors of the second 7 cascade also change in phase, which stabilizes the static voltage across the resistors of the load circuit 19.

Thus, the proposed technical solution is an alternative to the widespread APN with classical architecture [1-36] and is characterized by higher quality parameters.

As for the range of linear operation of the APN of figure 2 along the channel "X", then it, as well as in the APN prototype, is quite small (10-50 mV). This allows you to use the APN of figure 2 as a low-voltage mixer of two signals u _x and u _y . To increase the range of multiplication on the channel "X", you should use the traditional circuitry technique - turning on the input "X" of the logarithmic diodes.

Presented on the drawing of figure 4, the dependencies confirm that the inventive device performs the functions of a voltage multiplier. However, unlike the APN prototype, the proposed circuit is operable with a supply voltage E _p ≥ ± (1 ÷ 1.2) V, which allows us to recommend it for microcircuits with topological norms of less than 0.18 μm.

BIBLIOGRAPHIC LIST

1. Patent GB 2.318.470, H03F 3/45.

2. Patent EP 1.369.992.

3. US Patent No. 5,874,857.

4. US patent No. 6.456.142, Fig.8.

5. US Patent No. 3,931.583, Fig.9.

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Claims (1)

A low-voltage analog voltage multiplier comprising a first (1) differential stage having first (2) and second (3) current outputs, first (4) and second (5) potential inputs and current input (6) in the common emitter circuit of the first (1 ) a differential stage, a second (7) differential stage, having first (8) and second (9) current outputs, first (10) and second (11) potential inputs and current input (12) in the common emitter circuit of the second (7) differential cascade, and the first (2) current output of the first (1) differential cascade is connected to (9) the current output of the second (7) differential stage, and the second (3) current output of the first (1) differential stage is connected to the first (8) current output of the second (7) differential stage, the second (5) potential input of the first (1) ) the differential stage is connected to the first (10) potential input of the second (7) differential stage and connected to the first (13) input of the multiplication channel “X”, the first (4) potential input of the first (1) differential stage is connected to the second (11) potential the input of the second (7) differential stage and with connected to the second (14) input of the multiplication channel “X”, the current input (6) of the first (1) differential stage is connected to the first (15) power source through the first (16) current-stabilizing two-terminal device, the current input (12) of the second (7) differential the cascade is connected to the first (15) power source through the second (17) current-stabilizing two-terminal device, the first (2) and second (3) current outputs of the first (1) differential stage are connected to the load circuit (19), and the analog multiplier also has the first (20) ) input of the multiplication channel “Y”, second (21) input of the channel multiplication la "Y", characterized in that the first (22), second (23), third (24) and fourth (25) auxiliary resistors are introduced into the circuit, the first (26) and second (27) directly biased pn junctions, the first the input (20) of the multiplication channel “Y” is connected to the current input (6) in the common emitter circuit of the first (1) differential stage through the third (24) auxiliary resistor and the first (26) directly biased pn junction, the second input (21) connected in series the multiplication channel "Y" is connected to the current input (12) in the common emitter circuit of the second (7) differential helmet and through the fourth (25) auxiliary resistor and the second (27) directly biased pn junction connected in series, the first (28) common node of the third (24) auxiliary resistor and the first (26) directly biased pn junction is connected through the first (22) auxiliary resistor with the second (18) power source, and the second (29) common node of the fourth (25) auxiliary resistor and the second (27) directly biased pn junction is connected through the second (23) auxiliary resistor to the second (18) power source.

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