RU2560967C1 - Method of correction of large-scale integrated circuit topology - Google Patents

Abstract

FIELD: radio engineering, communication.

SUBSTANCE: in the method of correction of large-scale integrated circuit topology the formation of new links between elements or nodes of the circuit for execution of correction of crystal topology is performed using indium partitions. The formation of indium partitions between the selected metallised buses is performed in mechanical way using electrodes with flat bases.

EFFECT: decrease of cost of execution of operation of correction of topology at minimization of time for its execution.

2 cl, 8 dwg

Description

The invention relates to the design of circuitry and topology of integrated circuits and can be used to correct the topology of the LSI.

Despite the application of modern design methods and the use of high-quality technology, new crystals may be inoperative or their measured parameters may differ from expected ones.

A known method of topology correction, which consists in measuring the parameters of the crystal after its manufacture, detecting the presence of a defect, the location of its localization and determining the proposed ways to correct it. Based on the results obtained, computer development of the second version of the LSI topology is carried out, a new set of photomasks is designed and a full cycle of technological operations is performed for the manufacture of a batch of plates. If the results of measuring the parameters of a new LSI chip suit the developers, the design of the topology is considered to be completed successfully, if the result is negative, it is necessary to change the design again, develop a third version of the topology and / or scheme, re-create a set of photo templates and repeat the entire technological cycle. And this can happen several times, since errors made when designing the circuit diagram and topology in this way are detected only after the manufacturing of the LSI [Rapid prototyping of submicron ICs using FIB. David Perrin, Wayland Seifert. Solid State Technology, October, 1994].

Obviously, the disadvantage of the considered correction method is the unpredictably long time required for the development and manufacture of workable LSIs.

Closest to the proposed one is a correction method, in which after finding the cause of the defect, the location of its location and determining the possible ways to correct it, a mechanical change of the LSI crystal circuit is performed in real time, when the old (defective) are quickly eliminated and new connections between the elements are created or circuit nodes. New connections between the selected points of the circuit are formed using temporarily created conductive jumpers with subsequent measurement of the parameters of the modified crystal circuit. Jumpers are created on the surface of the crystal using the Focused Ion Beam (FIB) technology, such as a Quanta 3D or similar [FIB / FE SEM System Tracks Down Killer Defects. Eugene Delenia, Bryan Tracy, Homi Fatemi. EE-Evaluation Engineering, October, 1995], [Electron-probe methods of induced current and potential contrast in the analysis of failures of specialized integrated circuits for reading and processing signals from matrix IR photodetectors. Akimov V.M., Dremova N.N., Yakunin S.N. Applied Physics, 2008, No. 2, 94-99].

The use of thin FIB ion-beam technology for the reconstruction of LSI elements allows the implementation of technological operations such as etching of materials, deposition of dielectrics, and deposition of conductive elements (Pt, W) in the local region of the crystal.

Correction of the topology of the crystal continues until a circuit is obtained in which the detected defect is eliminated. With a positive result of the work performed, a new topology is being designed.

The indicated methodology for topology correction has a significant drawback associated with the high cost of installations using FIB technology and the need for highly qualified specialists. In this regard, this method has not found wide application.

The objective of the invention is to reduce the cost of performing the operation of topology correction while minimizing the time for its implementation.

The technical result - reducing the cost of topology correction - is achieved by the fact that the LSI topology correction method includes measuring the crystal circuit parameters after its manufacture, investigating the reasons for the deviation of the measured parameters from the expected ones, detecting the location of the defect, eliminating the defective connection between the circuit elements, creating a new connection in the circuit instead of a defective one using a temporarily created conductive jumper, moreover, the conductive jumper is created using an indium layer by pressing this layer to a metallized tire for cold welding of the indium layer and tire material.

The essence of the invention is as follows:

- according to the results of the study of the fabricated crystal, a way to correct the defect is outlined;

- eliminate the defective connection between the circuit elements intended for removal;

- determine the necessary location of the indium jumper instead of the defective;

- make the removal of the dielectric from the metal bus at the place of future contact of the jumper with the metal by any known method;

- apply a film of indium on the windows to the metallized tires and the route of the future location of the bridge with a needle (probe) of the probe installation;

- carry out the preliminary formation of the indium bridge; while the indium film is pressed with a needle with a flat base in the windows to the metal busbars and to the crystal surface along the jumper location path;

- form the final pattern of the indium bridge both in width and in height;

- make the electrical molding of the contact obtained by passing an electric current through it during the deformation of indium and after creating the contact to reduce the contact resistance of the metal-indium-metal;

- they measure the parameters of the modified crystal circuit; if the result is negative, the cycle of operations to correct the defect is repeated; if the result is positive, the second version of the topology is being designed.

When applying the considered method for correcting the LSI topology, the use of sophisticated technological equipment is not required; it is enough to have an analytical probe installation, a set of needles (probes) and a small amount of consumable material - metallic indium. The work on correcting the topology is carried out by one employee - a specialist in electroprobe measurements. Usually, the correction of one topology element takes several minutes.

The sequence of technological operations for creating indium jumpers by the proposed method is illustrated in FIG. 1-8, where:

1 - crystal LSI,

2 - metallization tires,

3 - a layer of protective dielectric,

4 - indium film,

5 - electrode for clamping indium,

6 - jumper from india,

7 - electrodes for electrical contact molding.

Creating indium jumpers is carried out in the following sequence:

- determine the location of the indium bridge (Fig. 1A is a plan view of the crystal and Fig. 1b is the cross section of the crystal at the point of creation of the indium bridge);

- remove the dielectric from the metal bus at the place of future contact of the jumper with the metal by any known method (Fig. 2);

- apply a film of plastic indium metal on the windows to the metallized tires with the needle of the probe installation (Fig. 3);

- form the electrical contact of the indium jumper to the metallized tires; for this, the indium film is pressed against the tire metal with a needle with a flat base, thereby making cold welding between the contact metals (Fig. 4);

- create the final picture of the indium bridge both in width and in height (Fig. 5 - top view of the crystal);

- produce the electrical molding of the obtained contact by passing electric current through it to reduce the contact resistance of the metal - indium - metal (Fig. 6 and 7);

- conduct electrical control of the resistance of the indium jumper (Fig).

The use of indium for the operational change of the crystal scheme is determined by its properties. Indium is the most ductile metal in a wide temperature range - from room temperature to helium temperature. Its hardness on the Mohs scale is slightly more than 1 (only talc is softer). Indium is 20 times softer than pure gold, and its tensile strength is 6 times less than that of lead. It is stable in air at room temperature, and oxidizes when heated.

The melting point of indium is 156.78 ° C, and it is this temperature that basically determines the current limit for using the indium jumper. By its main operational parameters, indium is close to tire metals, which makes it possible to create reliable electrical, mechanical and thermal indium-metal contact in a wide temperature range.

For example, an indium-metal contact is widely used in the creation of indium microcontacts for hybridization of crystals by the “inverted crystal” method for the creation of infrared photodetectors [Methods for creating a metallization system with indium microcontacts for silicon matrix MOS multiplexers. Akimov V.M., Vasilieva L.A., Kogan N.B., Klimanov E.A., Kurbet I.Yu., Liseikin V.P., Mikertumyants A.R., Sednev M.V., Seregina N .N., Schukin S.V. Applied Physics, No. 1, 2008, p. 71-74].

A set of tests of indium jumpers made by the proposed method was carried out, including mechanical loads, multiple thermal cycling and control of temporary stability.

The electrical resistance of the contact metallized conductor - indium layer is usually units - tens of ohms, depending on the contact area. An indium jumper passes a current of several hundred milliamps, which is quite enough for most cases. Metals: aluminum, molybdenum, vanadium and semiconductor materials: polysilicon and doped silicon have been successfully used as a conducting material for contact with the indium layer. This method is applicable for the correction of LSI topology, hybrid thin- and thick-film microcircuits, as well as combined GIS.

The method can also be used to eliminate breaks in metallized tires and create conductors and contact pads for measuring test structures.

Claims (2)

1. A method for correcting the LSI topology, including measuring the parameters of the crystal circuit after its manufacture, investigating the reasons for the deviation of the measured parameters from the expected ones, detecting the location of the defect, eliminating the defective connection between the circuit elements, forming a new connection in the circuit with the help of the defective, using a temporarily created conducting jumper, characterized in that in order to reduce the cost of topology correction, a conductive jumper is created using an indium layer by pressing this layer to the metal lined tire for cold welding of indium layer and tire material. 2. The method according to p. 1, characterized in that electric current is passed through the metallization buses and the conductive jumper.

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