CN102347255B - Alignment detection method for thin film transistor - Google Patents
Alignment detection method for thin film transistor Download PDFInfo
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- CN102347255B CN102347255B CN 201010239799 CN201010239799A CN102347255B CN 102347255 B CN102347255 B CN 102347255B CN 201010239799 CN201010239799 CN 201010239799 CN 201010239799 A CN201010239799 A CN 201010239799A CN 102347255 B CN102347255 B CN 102347255B
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Abstract
The invention provides an alignment detection method for a thin film transistor, which comprises the following steps: providing a substrate on which an element area and a test area are defined; forming a first conducting layer on the substrate; carrying out first patterning processing on the first conducting layer to form a gate electrode of the thin film transistor and a first end and a second end of a test element; forming a first insulating layer on the substrate; forming a pair of first contact holes which correspond to the first end and the second end in the first insulating layer; forming a pixel electrode and a connecting electrode of the test element in the element area; and performing a close circuit/open circuit test on the test element. When the test element has a close circuit, the alignment of the film layer of the thin film transistor is judged to be accurate, and when the test element has an open circuit, the alignment of the film layer of the thin film transistor is judged to be inaccurate.
Description
Technical field
The invention relates to a kind of rete to position detecting method, refer to that especially a kind of rete of the thin-film transistor that can integrate with electric test method is to position detecting method.
Background technology
In the manufacturing process of LCD, numerous small thin-film transistors are formed on the same substrate, so the contraposition precision of each rete of thin-film transistor (alignment accuracy) can be described as one of key factor of the yield that influences thin-film transistor technology.
The thin-film transistor of available liquid crystal display and the technology of pixel electrode can be summarized as follows: a substrate at first is provided, and forms a metal level on substrate.Next utilize one first Patternized technique patterned metal layer and form a gate electrode, on gate electrode, form an insulating barrier subsequently.After forming insulating barrier, on insulating barrier, form semi-conductor layer and a doping semiconductor layer in regular turn; Pass through one second Patternized technique patterned semiconductor layer and doping semiconductor layer again, and form semiconductor structure.Afterwards, on substrate, form a metal level again, and form source by one the 3rd Patternized technique patterned metal layer.Form after the source/drain, form an insulating barrier again, and in insulating barrier, form a contact hole (contact hole) by one the 4th Patternized technique.At last, on substrate, form a transparency conducting layer, and by one the 5th Patternized technique patterned transparent conductive layer, and form a pixel electrode by contact hole electric connection source/drain, finish the making of thin-film transistor and pixel electrode.
As shown in the above description, rete patterns such as gate electrode, semiconductor structure, source/drain, contact hole and pixel electrode all are to utilize little shadow technology that one mask pattern is transferred on the photoresistance, the recycling etch process with the design transfer on the photoresistance to the target rete, therefore each mask pattern all must have relative position very accurately, otherwise this layer pattern may link up with preceding layer pattern, so cause desire the circuit malfunction of construction.Therefore, be to utilize the optical profile type measurement to check the overlay precision of mask pattern in the prior art, it is coherent to guarantee that the rete pattern that forms behind the Patternized technique can overlap with preceding layer pattern.
Yet the sampling observation rate that existing optical profile type is measured is about 1～5%, and its measurement time reaches 10～20 minutes especially.It is extremely low that optical profile type that hence one can see that is measured not only sampling observation rate, also extremely time-consuming because of its measurement time, and cause optical profile type to measure the sampling observation rate that can't improve that always faces, and perhaps must set up the predicament of increase costs such as measurement platform for improving the sampling observation rate.
Summary of the invention
Therefore, the invention provides a kind of rete of existing optical profile type measurement that replaces to position detecting method, in order to check the contraposition precision of rete.
The invention provides a kind of thin-film transistor to position detecting method, this method at first provides a substrate, and definition has an element region and a test section on this substrate.Next form one first conductive layer at this substrate, and this first conductive layer carried out one first Patternized technique, in this element region, to form a gate electrode of a thin-film transistor, and one first end and one second end that in this test section, form a testing element, wherein this first end electrically separates with this second end.Afterwards, form one first insulating barrier at this substrate, and this first insulating barrier covers this first end and this second end of this gate electrode and this testing element.After this first insulating barrier to be formed, in this first insulating barrier, form one first contact hole, and this first contact hole is to this first end and this second end that should testing element; In this element region, form a pixel electrode subsequently, and form a connection electrode of this testing element in this first contact hole in this test section.This first end, this connection electrode and this second end to this testing element carries out one path/out of circuit test afterwards.When this first end, this connection electrode and this second end of this testing element have a path, the contraposition of rete of judging this thin-film transistor is accurate, and have when opening circuit when this first end, this connection electrode and this second end of this testing element, judge that the contraposition of rete of this thin-film transistor is inaccurate.
According to thin-film transistor provided by the present invention to position detecting method, this first contact hole can be respectively in order to form the semiconductor structure of thin-film transistor, source/drain, pixel electrode, and form in order to electrically connect in pixel electrode contacts elements such as hole with second of source/drain the Patternized technique, when this first contact hole causes being formed at this connection electrode of this testing element in it and this first because contraposition is inaccurate, second end can judge that Patternized technique and the formed rete generation contraposition thereof in order to form this first contact hole is inaccurate when opening circuit.And because thin-film transistor provided by the present invention is to utilize general path/out of circuit test to position detecting method, whether the contraposition of rete that can judge thin-film transistor according to circuit pathways or the result that opens circuit is accurate, so can significantly reduce the testing time to position detecting method of thin-film transistor, also can promote the sampling observation rate to position detecting method of thin-film transistor.
Description of drawings
Fig. 1 to Fig. 4 b is the schematic diagram to first preferred embodiment of position detecting method of thin-film transistor provided by the present invention, and wherein Fig. 4 a and Fig. 4 b are the part schematic diagram of testing element provided by the present invention.
Fig. 5 to Fig. 8 is the intention to second preferred embodiment of position detecting method of thin-film transistor provided by the present invention, and wherein Fig. 8 is the part schematic diagram of testing element provided by the present invention.
Fig. 9 to Figure 11 is the schematic diagram to the 3rd preferred embodiment of position detecting method of thin-film transistor provided by the present invention, and wherein Figure 11 is the part schematic diagram of testing element provided by the present invention.
Figure 12 is the 4th preferred embodiment to position detecting method of thin-film transistor provided by the present invention, and is the part schematic diagram of testing element provided by the present invention.
Figure 13 a is the schematic diagram to a preferred embodiment of position detecting method of thin-film transistor provided by the present invention.
Figure 13 b is the schematic diagram to another preferred embodiment of position detecting method of thin-film transistor provided by the present invention.
Embodiment
In order to make purpose of the present invention, technical scheme and beneficial effect clearer, below in conjunction with drawings and Examples, the present invention is further elaborated.Should be appreciated that specific embodiment described herein only in order to explaining the present invention, and be not used in restriction the present invention.
See also Fig. 1 to Fig. 4 b, Fig. 1 to Fig. 4 b is the schematic diagram to first preferred embodiment of position detecting method of thin-film transistor provided by the present invention, and wherein Fig. 4 a and Fig. 4 b are the part schematic diagram of testing element provided by the present invention.As shown in Figure 1, at first provide a substrate 100, and definition there are an element region 102 and a test section 104 on the substrate 100.Next, form one first conductive layer (not shown) at substrate 100, and first conductive layer carried out one first Patternized technique, in element region 102, to form a gate electrode 202 of a thin-film transistor, and one first end 302 and one second end 304 that form a testing element in test section 104, and first end 302 and second end 304 are for electrically separating.Because technology such as little shadow that first Patternized technique comprises and etching are for haveing the knack of the personage institute well known of this skill, does not give unnecessary details in this Therefore, omited.
Subsequently, form one first insulating barrier 106 at substrate 100, and first insulating barrier 106 is first end 302 and second end 304 of cover gate electrode 202 and testing element as shown in Figure 1.Next, semi-conductor layer 110 on substrate 100, and semiconductor layer 110 from bottom to top can comprise not doping semiconductor layer 112, for example an amorphous silicon layer or a polysilicon layer in regular turn, and doping semiconductor layer 114, for example a doped amorphous silicon layer or a doped polysilicon layer.
Next see also Fig. 2.Subsequently, carry out one second Patternized technique, patterned semiconductor layer 110 is to form semiconductor structure 204 at least corresponding to first insulating barrier 106 above the gate electrode 202 in element region 102.Not doping semiconductor layer 112 in this semiconductor structure 204 is used as the channel layer of thin-film transistor; Doping semiconductor layer 114 is then as ohmic contact layer, in order to the contact impedance between the metal material that reduces not doping semiconductor layer 112 and follow-up formation.It should be noted that, in the present embodiment, second Patternized technique forms in the semiconductor structure 204 in element region 102, semiconductor layer in the patterning test section 104 110 and first insulating barrier 106 that is positioned at semiconductor layer 110 belows in the lump contact hole 306 with formation one first in first insulating barrier 106 of test section 104 and semiconductor layer 110.The first contact hole 306 is substantially corresponding to first end 302 and second end 304 of testing element, also the i.e. first contact hole 306 at least part of first end 302 and second end 304 of exposing also between first end 302 and second end 304 substantially.Since the required little shadow technology of second Patternized technique with in order to the etching technique that removes first insulating barrier 106 and semiconductor layer 110 etc. also for known to the personage who has the knack of this skill, so also repeat no more in this.
Please continue to consult Fig. 2.After finishing semiconductor structure 204 and first contact the making in hole 306, on substrate 100, form one second conductive layer (not shown) again, and by one the 3rd Patternized technique patterning, second conductive layer, remove second conductive layer in the test section 104, and the 204 formation source 206 of the semiconductor structure in element region 102, finish the making of thin-film transistor 200.Behind the source/drain 206 that forms thin-film transistor 200, form one second insulating barrier 108 at substrate 100 again, and utilize one the 4th Patternized technique patterning, second insulating barrier 108, with second insulating barrier 108 in the removal test section 104, and form one second contact hole 208 in second insulating barrier 108 in element region 102.
See also Fig. 3.Afterwards, form a transparency conducting layer (not shown) at substrate 100, pass through one the 5th this transparency conducting layer of Patternized technique patterning again, and form a pixel electrode 210 in element region 102, wherein pixel electrode 210 is by the second contact hole 208 and source/drain 206 electric connections.In addition, the transparency conducting layer of patterning also forms a connection electrode 308 of testing element in the first contact hole 306 in test section 104 simultaneously, and finishes the making of testing element 300.It should be noted that testing element provided by the present invention 300 is for can be integrated in the thin-film transistor technology of general need five road Patternized techniques, so need not increase the technology number.
Next, first end 302, connection electrode 308 and second end 304 to testing element 300 carries out one path/out of circuit test.In detail, the practice of path/out of circuit test is first end 302 and second end 304 of electric connection testing element 300, and feeds a test signal at first end 302.When test signal by first end 302, connect electrode 308, and can detect this test signal at second end 304 of testing element 300 time, namely represent testing element 300 first end 302, connect electrode 308 and second end 304 has a path.It should be noted that, if the second Patternized technique contraposition is accurate, then the first contact hole 306 can expose part first end 302 and part second end 304 of testing element 300 simultaneously, can electrically connect first end 302 and second end 304 so connect electrode 308, and form above-mentioned path.Therefore, this path testing result can illustrate that first contact hole 306 contrapositions of testing element 300 are accurate, can judge simultaneously the rete of thin-film transistor 300, and for example contact semiconductor structure 204 contrapositions that hole 306 forms simultaneously with first accurate.
See also Fig. 4 a and Fig. 4 b in addition.Otherwise, when test signal not when second end 304 of testing element 300 is detected, namely represent testing element 300 first end 302, connect electrode 308 and second end 304 and have and open circuit.This explanation of opening circuit: the inaccurate situation of little shadow technology generation contraposition in second Patternized technique, and this a pair of biased difference causes semiconductor structure 204 and first contact the situation that the contraposition skew also takes place thereupon in hole 306 with it forms simultaneously.When this skew to the left or to the right surpasses the coincidence tolerance, then the first contact hole 306 is shown in Fig. 4 a and Fig. 4 b, can't expose first end 302 or second end 304 of testing element 300, therefore connecting electrode 308 can't electrically connect first end 302 or second end 304, opens circuit and form one.Therefore, this out of circuit test result can illustrate that first contact hole 306 contrapositions of testing element 300 are inaccurate, can judge simultaneously the rete of thin-film transistor 300, and for example contact semiconductor structure 204 contrapositions that hole 306 forms simultaneously with first inaccurate.
See also Fig. 5 to Fig. 8, Fig. 5 to Fig. 8 is the schematic diagram to second preferred embodiment of position detecting method of thin-film transistor provided by the present invention, and wherein Fig. 8 is the part schematic diagram of testing element provided by the present invention.It should be noted that in addition in second preferred embodiment with the first preferred embodiment components identical to the components identical symbol description.As shown in Figure 5, this second preferred embodiment also provides definition that the substrate 100 of element region 102 and test section 104 is arranged, be to utilize the described film-forming process of first preferred embodiment and first Patternized technique in element region 102, to form the gate electrode 202 of thin-film transistor 200 on it, simultaneously one first end 312 and one second end 314 of formation one testing element test section 104 in, and first end 312 and second end 314 are for electrically separating.
Subsequently, form one first insulating barrier 106 at substrate 100, and first insulating barrier 106 is first end 312 and second end 314 of cover gate electrode 202 and testing element as shown in Figure 5.Next, form the semi-conductor layer (not shown) at substrate 100, semiconductor layer from bottom to top comprises not doping semiconductor layer 112 and a doping semiconductor layer 114 in regular turn.Carry out subsequently as described second patterning step of first preferred embodiment, at first insulating barrier, the 106 formation semiconductor structures 204 of corresponding gate electrode 202 parts.Please continue to consult Fig. 5.After treating in element region 102, to form semiconductor structure 204, form one second conductive layer 206a at substrate 100 again.
See also Fig. 6.Next for utilizing as described the 3rd Patternized technique patterning of the first preferred embodiment second conductive layer 206a, in element region 102, to form the source/drain 206 of thin-film transistor 200 corresponding to semiconductor structure 204 parts, finish the making of thin-film transistor 200.It should be noted that in the present embodiment, in element region 102, form in the source/drain 206 that the 3rd Patternized technique is the second conductive layer 206a in the patterning test section 104 in the lump, and forms a patterning second conductive layer 206b.Afterwards, and utilize the patterning second conductive layer 206b as first insulating barrier 106 in the etch shield etching test section 104, forming one first contact hole 316 in first insulating barrier 106 of test section 104, and the first contact hole 316 is substantially corresponding to first end 312 and second end 314 of testing element.
See also Fig. 7.After finishing source/drain 206 and first contact the making in hole 316, form one second insulating barrier 108 at substrate 100, and utilize one the 4th Patternized technique patterning, second insulating barrier 108, remove second insulating barrier 108 in the test section 104, and in second insulating barrier 108 of element region 102, form one second contact hole 208.Afterwards, form a transparency conducting layer (not shown) at substrate 100, by form pixel electrode 210 in element region 102 as described the 5th this transparency conducting layer of Patternized technique patterning of first preferred embodiment, pixel electrode 210 is by the second contact hole 208 and source/drain 206 electric connections again.Simultaneously, form one of testing element in the first contact hole 316 in test section 104 and connect electrode 318, and finish the making of testing element 310.As previously mentioned, testing element 310 is for can be integrated in the thin-film transistor technology of general need five road Patternized techniques, so need not increase the technology number.
Next, first end 312, connection electrode 318 and second end 314 to testing element 310 carries out one path/out of circuit test.In detail, path/out of circuit test is first end 312 and second end 314 that electrically connects testing element 310, and feeds a test signal in first end 312.When test signal by first end 312, connect electrode 318, and can detect this test signal at second end 314 of testing element 310 time, namely represent testing element 310 first end 312, connect electrode 318 and second end 314 has a path.As previously mentioned, if the 3rd Patternized technique contraposition is accurate, then the first contact hole 316 can expose part first end 312 and part second end 314 of testing element 310 simultaneously, can electrically connect first end 312 and second end 314 so connect electrode 318, and form above-mentioned path.Therefore, this path testing result can illustrate that first contact hole 316 contrapositions of testing element 310 are accurate, can judge simultaneously the rete of thin-film transistor 200, and for example contact source/drain 206 contrapositions that hole 316 forms simultaneously with first accurate.
See also Fig. 8 in addition.Yet, when test signal not when second end 314 of testing element 310 detects, namely represent testing element 310 first end 312, connect electrode 318 and second end 314 and have and open circuit.This little shadow technology generation contraposition inaccurate situation of explanation in the 3rd Patternized technique that open circuit causes source/drain 206 and first contact hole 316 situation that contraposition is offset also takes place thereupon with it forms simultaneously.When this skew to the left or to the right surpasses the coincidence tolerance, the first contact hole 316 is for as shown in Figure 8, can't expose first end 312 or second end 314 of testing element 310, connect electrode 318 and can't electrically connect first end 312 or second end 314 then, open circuit and form one.First contact hole 316 contrapositions that testing element 310 can be described according to this out of circuit test result are inaccurate, can judge simultaneously the rete of thin-film transistor 200, and for example contact source/drain 206 contrapositions that hole 316 forms simultaneously with first inaccurate.
See also Fig. 9 to Figure 11, Fig. 9 to Figure 11 is the schematic diagram to the 3rd preferred embodiment of position detecting method of thin-film transistor provided by the present invention, and wherein Figure 11 is the part schematic diagram of testing element provided by the present invention.It should be noted that in addition in the 3rd preferred embodiment with the first preferred embodiment components identical also with the components identical symbol description.As shown in Figure 9, this the 3rd preferred embodiment also provides definition that the substrate 100 of element region 102 and test section 104 is arranged, on it for to utilize the described film-forming process of first preferred embodiment and first Patternized technique in element region 102, to form the gate electrode 202 of thin-film transistor 200, simultaneously one first end 322 and one second end 324 of formation one testing element test section 104 in, and first end 322 and second end 324 are for electrically separating.
Subsequently, form one first insulating barrier 106 at substrate 100, and first end 322 of first insulating barrier, 106 cover gate electrodes 202 and testing element and second end 324.Next, form the semi-conductor layer (not shown) at substrate 100, semiconductor layer from bottom to top comprises not doping semiconductor layer 112 and doping semiconductor layer 114 in regular turn.Carry out subsequently as described second patterning step of first preferred embodiment, and form semiconductor structure 204 at first insulating barrier 106 of corresponding gate electrode 202 parts.After forming semiconductor structure 204, then form one second conductive layer (not shown) at substrate 100.
Please continue to consult Fig. 9.Next for utilizing as described the 3rd Patternized technique patterning of first preferred embodiment second conductive layer, in element region 102, to form the source/drain 206 of thin-film transistor 200 corresponding to semiconductor structure 204 places, finish the making of thin-film transistor 200.And after the making of finishing source/drain 206, form one second insulating barrier 108 at substrate 100.Subsequently, utilize just like described the 4th Patternized technique patterning of first preferred embodiment second insulating barrier 108, to form the second contact hole 208 in second insulating barrier 108 in element region 102.It should be noted that, in second insulating barrier 108 of element region 102, form in the second contact hole 208, the 4th Patternized technique is second insulating barrier 108 and first insulating barrier 106 of patterning test section 104 in the lump, contact hole 326 in first insulating barrier 106 of test section 104 and second insulating barrier 108, to form one first, and first contacts hole 326 substantially corresponding to first end 322 and second end 324 of testing element.
See also Figure 10.Afterwards, form a transparency conducting layer (not shown) at substrate 100, pass through again as described the 5th this transparency conducting layer of Patternized technique patterning of first preferred embodiment, and in element region 102, forming pixel electrode 210, pixel electrode 210 electrically connects by the second contact hole 208 and source/drain 206.In addition, when utilizing the 5th Patternized technique to form pixel electrode 210, also form one of testing element in the first contact hole 326 of while in test section 104 and connect electrode 328, and finish the making of testing element 320.
Next, first end 322, connection electrode 328 and second end 324 to testing element 320 carries out one path/out of circuit test.As previously mentioned, electrically connect first end 322 and second end 324 of testing element 320, and feed a test signal at first end 322.When test signal by first end 322, connect electrode 328, and can detect this test signal at second end 324 of testing element 320 time, namely represent testing element 320 first end 322, connect electrode 328 and second end 324 has a path.If the 4th Patternized technique contraposition is accurate, then the first contact hole 326 can expose part first end 322 and part second end 324 of testing element 320 simultaneously, can electrically connect first end 322 and second end 324 so connect electrode 328, and form above-mentioned path.Therefore, this path testing result can illustrate that first contact hole 326 contrapositions of testing element 320 are accurate, can judge simultaneously the rete of thin-film transistor 200, for example contact with first that hole 326 forms simultaneously second to contact hole 208 contrapositions accurate.
See also Figure 11 in addition.When test signal not when second end 324 of testing element 320 is detected, namely represent testing element 320 first end 322, connect electrode 328 and second end 324 and have and open circuit.This little shadow technology generation contraposition inaccurate situation of explanation in the 4th Patternized technique that open circuit causes the second contact hole 208 and first contact hole 326 situation that contraposition is offset takes place thereupon with it forms simultaneously.When this skew to the left or to the right surpassed the coincidence tolerance, then the first contact hole 326 can't expose first end 322 or second end 324 of testing element 320 for as shown in figure 11, therefore connected electrode 328 and formed one and open circuit with first end 322, second end 324.First contact hole 326 contrapositions that can infer testing element 320 according to this out of circuit test result are inaccurate, can infer simultaneously the rete pattern of thin-film transistor 200, for example contact with first that hole 326 forms simultaneously second to contact hole 208 contrapositions inaccurate.
According to the explanation of first to the 3rd preferred embodiment, thin-film transistor provided by the present invention is to utilize five essential in general thin-film transistor technology road Patternized techniques to make testing element 300/310/320 in test section 104 to position detecting method as can be known.Testing element 30,0/3,10/,320 first end 302/312/322 that utilization and gate electrode 202 form simultaneously and second end 304/314/324 are as the input point and detecting point of test signal, and utilize the last bridge that is connected electrode 308/318/328 conduct electric connection that forms simultaneously with pixel electrode 210, be path or open circuit to judge whether corresponding rete contraposition is accurate according to testing element 300/310/320.
See also Figure 12, Figure 12 is the schematic diagram of testing element provided by the present invention.Yet, the situation of contraposition skew may take place in the personage Ying Zhi that has the knack of this skill except above-mentioned rete, when carrying out the 5th road Patternized technique patterned transparent conductive layer with making pixel electrode 210 and being connected electrode 308/318/328, skew situation as shown in figure 12 also might take place in the 5th road Patternized technique.Namely the inaccurate situation of little shadow technology generation contraposition in the 5th Patternized technique causes the situation that the contraposition skew takes place electrode 328 that connects.When this skew to the left or to the right surpasses the coincidence tolerance, then connect first end 322 and second end 324 that electrode 328 can't electrically be connected to testing element 320, therefore connect electrode 328 and form one and open circuit with first end 322, second end 324.
If the final connection electrode that forms 308/318/328 itself above-mentioned skew situation takes place, also might cause the operator to judge by accident, or whether cause the operator can't determine the contraposition of other rete accurate.In view of this, thin-film transistor provided by the present invention also can be when making thin-film transistor to position detecting method, the testing element 300/310/320 that first to the 3rd preferred embodiment is provided is made in respectively in the test section 104 simultaneously.When only having testing element 300 to open circuit in three testing elements 300/310/320, can judge that the second Patternized technique contraposition of making the first contact hole 306 and semiconductor structure 204 is inaccurate; When only having testing element 310 to open circuit, can judge that the 3rd Patternized technique contraposition of making the first contact hole 316 and source/drain 206 is inaccurate; And when only having testing element 320 to open circuit, can infer that to make the second contact hole 208 contacts hole 326 with first the 4th Patternized technique contraposition inaccurate.Yet, when testing element 300, testing element 310 open circuit simultaneously with testing element 320 threes, can infer that the 5th Patternized technique of making connection electrode 308/318/328 and pixel electrode 210 is inaccurate, cause all testing elements all to obtain the result that opens circuit, and can be determined by other method.
See also Figure 13 a, Figure 13 a is the schematic diagram to a preferred embodiment of position detecting method of thin-film transistor provided by the present invention.Even more noteworthy, since thin-film transistor provided by the present invention to position detecting method for utilizing electrical signals as testing tool, therefore thin-film transistor provided by the present invention also can (test element group TEG) 400 integrates with the testing element group of existing electrical characteristic in order to the testing film transistor array to position detecting method.Shown in Figure 13 a, for testing element 300/310/320 can being electrically connected with series system with testing element group 400 respectively, and the probe 500 of testing electrical property board that directly utilizes testing element group 400 is finished contraposition and is detected when carrying out testing electrical property.In other words, thin-film transistor provided by the present invention to position detecting method for can give the testing electrical property board one rete contraposition audit function, it is being carried out outside the existing electrical characteristic audit function, also can carry out other function simultaneously: when testing element 300/310/320 and testing element group 400 have path, the contraposition of rete of namely representing thin-film transistor is accurate, and can carry out the testing electrical property of testing element group 400 simultaneously; When testing element 300/310/320 and testing element group 400 have when opening circuit, then judge it is testing element group 400 problems or testing element 300/310/320 and the inaccurate problem of thin-film transistor contraposition by the engineer again.Importantly, because testing electrical property itself is a necessary inspection engineering, and therefore testing electrical property and can finish simultaneously bit test can significantly promote sampling observation rate to 25% with the testing element 300/310/320 that testing element group 400 is integrated under the prerequisite that does not increase the testing time.
See also Figure 13 b in addition, Figure 13 b is the schematic diagram to another preferred embodiment of position detecting method of thin-film transistor provided by the present invention.As previously mentioned, thin-film transistor provided by the present invention is to integrate with a testing element group 402 to position detecting method.Shown in Figure 13 b, testing element 300/310/320 can be electrically connected with parallel way with testing element group 402 respectively, and the probe 502 of testing electrical property board that directly utilizes testing element group 402 is when carrying out testing electrical property, have contraposition simultaneously and detect this function: when 300/310/320 pair of testing element group of testing element 402 forms a short circuit, be that the contraposition of expression thin-film transistor is accurate; Open circuit and testing element group 402 when forming paths when testing element 300/310/320 forms one, then can directly carry out the testing electrical property of testing element group 400.As previously mentioned, because testing electrical property itself is a necessary inspection engineering, and therefore testing electrical property and can finish simultaneously bit test can significantly promote sampling observation rate to 25% with the testing element 300/310/320 that testing element group 402 is integrated under the prerequisite that does not increase the testing time.
In sum, according to thin-film transistor provided by the present invention to position detecting method, this first contact hole can be respectively at forming in order to the semiconductor structure that forms thin-film transistor, source/drain, pixel electrode and in order to electrically connect in pixel electrode contacts elements such as hole with second of source/drain the Patternized technique, when the first contact hole causes being formed at this connection electrode of this testing element in it and this first, second end when opening circuit because contraposition is inaccurate, can judge that certain road Patternized technique and formed rete generation contraposition thereof are inaccurate.And because thin-film transistor provided by the present invention is to utilize general path/out of circuit test to position detecting method, whether the contraposition of rete that can judge thin-film transistor according to circuit pathways or the result that opens circuit is accurate, so can significantly reduce the testing time to position detecting method of thin-film transistor, also can promote the sampling observation rate to position detecting method of thin-film transistor.
The above only is preferred embodiment of the present invention, not in order to limiting the present invention, all any modifications of doing within the spirit and principles in the present invention, is equal to and replaces and improvement etc., all should be included within protection scope of the present invention.
Claims (10)
- A thin-film transistor to position detecting method, it is characterized in that, said method comprising the steps of:One substrate is provided, and definition has an element region and a test section on the described substrate;Form one first conductive layer at described substrate, and described first conductive layer carried out one first Patternized technique, in described element region, to form a gate electrode of a thin-film transistor, and one first end and one second end that in described test section, form a testing element, described first end electrically separates with described second end;Form one first insulating barrier at described substrate, described first insulating barrier covers first end and second end of described gate electrode and described testing element;In described first insulating barrier, form one first contact hole, first end and second end of the corresponding described testing element in the described first contact hole;In described element region, form a pixel electrode, and form a connection electrode of described testing element in the first contact hole in described test section; AndFirst end, connection electrode and second end to described testing element carry out one path/out of circuit test, when described first end of described testing element, described connection electrode and described second end have a path, the contraposition of rete of judging described thin-film transistor is accurate, and have when opening circuit when described first end of described testing element, described connection electrode and described second end, judge that the contraposition of rete of described thin-film transistor is inaccurate.
- Thin-film transistor as claimed in claim 1 to position detecting method, it is characterized in that described method is further comprising the steps of:Form semi-conductor layer at described substrate; AndCarry out one second Patternized technique, the described semiconductor layer of patterning is to form semiconductor structure at least corresponding to first insulating barrier above the described gate electrode in described element region.
- 3. thin-film transistor as claimed in claim 2 to position detecting method, it is characterized in that, in described element region, form in the described semiconductor structure, described second Patternized technique also is positioned at described first insulating barrier of described semiconductor layer below in the described test section of patterning in the lump, to form the described first contact hole in described first insulating barrier of described test section.
- Thin-film transistor as claimed in claim 2 to position detecting method, it is characterized in that described method is further comprising the steps of:Form one second conductive layer at described substrate; AndCarry out one the 3rd Patternized technique, described second conductive layer of patterning is to form the source of described thin-film transistor in described element region.
- 5. thin-film transistor as claimed in claim 4 to position detecting method, it is characterized in that, in described element region, form in the described source/drain, described the 3rd Patternized technique and described first insulating barrier in the described test section of patterning in the lump contact the hole to form described first in described first insulating barrier of described test section.
- Thin-film transistor as claimed in claim 4 to position detecting method, it is characterized in that described method is further comprising the steps of:Form one second insulating barrier at described substrate; AndCarry out one the 4th Patternized technique, described second insulating barrier of patterning is to form one second contact hole in described second insulating barrier of described element region.
- 7. thin-film transistor as claimed in claim 6 to position detecting method, it is characterized in that, form in described second insulating barrier of described element region in the described second contact hole, described the 4th Patternized technique also forms the described first contact hole in the lump in described first insulating barrier of described test section.
- Thin-film transistor as claimed in claim 6 to position detecting method, it is characterized in that described method is further comprising the steps of:Form a transparency conducting layer at described substrate; AndCarry out one the 5th Patternized technique, the described transparency conducting layer of patterning is with the described connection electrode that forms described pixel electrode at described element region and form described testing element in described test section.
- Thin-film transistor as claimed in claim 8 to position detecting method, it is characterized in that the described first contact hole is carried out before described the 5th Patternized technique for being formed at.
- Thin-film transistor as claimed in claim 1 to position detecting method, it is characterized in that described testing element is for electrically connecting a testing element group.
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| CN 201010239799 CN102347255B (en) | 2010-07-28 | 2010-07-28 | Alignment detection method for thin film transistor |
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| US6440816B1 (en) * | 2001-01-30 | 2002-08-27 | Agere Systems Guardian Corp. | Alignment mark fabrication process to limit accumulation of errors in level to level overlay |
| CN101393388A (en) * | 2007-09-18 | 2009-03-25 | 上海广电Nec液晶显示器有限公司 | Method for manufacturing thin film transistor LCD array substrate |
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| US6440816B1 (en) * | 2001-01-30 | 2002-08-27 | Agere Systems Guardian Corp. | Alignment mark fabrication process to limit accumulation of errors in level to level overlay |
| CN101393388A (en) * | 2007-09-18 | 2009-03-25 | 上海广电Nec液晶显示器有限公司 | Method for manufacturing thin film transistor LCD array substrate |
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