RU2393526C2 - Comparator of binary numbers - Google Patents

Abstract

FIELD: information technologies.

SUBSTANCE: invention may be used to build means of automatics, functional units of control systems. Device comprises two delay elements, two AND elements, four OR elements, two NOT elements.

EFFECT: reduced instrument costs.

1 dwg, 1 tbl

Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

подаются на упомянутые компараторы в j-й момент времени, а сигналы x_i(n-1) и x_i0

Comparators of binary numbers are known (see, for example, Fig. 6-19a on page 286 in the book Pospelov D.A. Logical methods of analysis and synthesis of circuits. M .: Energy, 1974), which perform the recognition of relations x ₁ = x ₂ , x ₁ ≠ x ₂ , where x ₁ = x _{1 (n-1)} ... x ₁₀ , x ₂ = x _{2 (n-1)} ... x ₂₀ are n-bit binary numbers given by binary signals x _{10, ...,} x _{1 (n-1)} , x ₂₀ , ..., x _{2 (n-1)} ∈ {0,1}, and the signals x _{1 (nj)} , x _{2 {nj)}

fed to the above-mentioned comparators at the j-th moment of time, and the signals x _{i (n-1)} and x _i0

determine the values of the highest and lowest digits of the number x _i, respectively.

The reason that impedes the achievement of the technical result indicated below when using known binary number comparators includes limited functionality, due to the fact that the recognition of the relations x _l > x ₂ , x ₁ <x _{2 is} not performed.

подаются на соответствующие входы прототипа в j-й момент времени, а сигналы x_i(n-1) и x_i0

определяют значения соответственно старшего и младшего разрядов числа x_i.The closest device of the same purpose to the claimed invention in terms of features is the binary number comparator adopted for the prototype (Fig. 6-20 on page 288 in the book of D. Pospelov. Logical methods of analysis and synthesis of circuits. M .: Energy, 1974) , which contains NOT elements, AND elements, OR elements, delay elements, and performs recognition of the relations x ₁ = x ₂ , x ₁ > x ₂ , x ₁ <x ₂ . where x ₁ = x _{1 (n-1)} ... x ₁₀ , x ₂ = x _{2 (n-1)} ... x ₂₀ are n-bit binary numbers given by binary signals x _{10, ...,} x _{1 (n-1) ,} x ₂₀ , ..., x _{2 (n-1)} ∈ {0,1}, and the signals x _{1 (nj)} , x _{2 (nj)}

fed to the corresponding inputs of the prototype at the j-th moment of time, and the signals x _{i (n-1)} and x _i0

determine the values of the highest and lowest digits of the number x _i, respectively.

The reason that impedes the achievement of the following technical result when using the prototype, include high hardware costs.

The technical result of the invention is to reduce hardware costs while maintaining the functionality of the prototype.

элемента ИЛИ соединены соответственно с выходом i-го элемента И, первым входом (i+2)-го элемента ИЛИ и входом i-го элемента задержки, подключенного выходом к первому входу (i+2)-го элемента ИЛИ, второй вход и выход которого соединены соответственно с первым входом i-го элемента И и входом i-го элемента НЕ, подключенного выходом к второму входу (3-i)-го элемента И, первый вход которого соединен с (3-i)-м входом компаратора двоичных чисел, подключенного i-м выходом к выходу i-го элемента ИЛИ.The specified technical result in the implementation of the invention is achieved by the fact that in the comparator of binary numbers containing two elements NOT, two AND elements, two OR elements and two delay elements, the peculiarity lies in the fact that two OR elements are additionally introduced into it, the first, second inputs and outputs of the i-th

OR elements are connected respectively to the output of the i-th AND element, the first input of the (i + 2) th OR element and the input of the i-th delay element connected to the first input of the (i + 2) OR element, the second input and output which are connected respectively to the first input of the i-th element AND and the input of the i-th element NOT connected to the second input of the (3-i) -th element And, the first input of which is connected to the (3-i) -th input of the binary number comparator connected by the i-th output to the output of the i-th OR element.

The drawing shows a diagram of the proposed comparator of binary numbers.

соединены соответственно с выходом элемента 2_i, первым входом элемента 3_i+2 и входом элемента 1_i подключенного выходом к первому входу элемента 3_i+2, второй вход и выход которого соединены соответственно с первым входом элемента 2_i и входом элемента 4_i, подключенного выходом к второму входу элемента 2_3-i, первый вход которого соединен с (3-i)-м входом компаратора двоичных чисел, подключенного i-м выходом к выходу элемента 3_i.The binary number comparator contains two delay elements 1 ₁ , 1 ₂ , two elements AND 2 ₁ , 2 ₂ , four elements OR 3 ₁ , 3 ₂ , 3 ₃ , 3 ₄ , two elements NOT 4 ₁ , 4 ₂ , the first and second inputs and output of element 3 _i

connected respectively to the output of element 2 _i , the first input of element 3 _{i + 2} and the input of element 1 _i connected by the output to the first input of element 3 _{i + 2} , the second input and output of which are connected respectively to the first input of element 2 _i and the input of element 4 _i , connected by the output to the second input of the element 2 _3-i , the first input of which is connected to the (3-i) -th input of the binary number comparator, connected by the i-th output to the output of the element 3 _i .

момент времени подаются соответственно двоичные сигналы x_1(n-j)∈{0,1} и x_2(n-j)∈{0,1}, которые задают значения (n-j)-х разрядов подлежащих сравнению n-разрядных двоичных чисел х₁=x_1(n-1)…x_10, и x₂=x_2(n-1)…x₂₀. Здесь сигналы x_i(n-l) и x_i0

определяют значения соответственно старшего и младшего разрядов числа x_i. Сигнал на выходе элемента задержки 1_i в j-й момент времени равен сигналу, который действовал на его входе в (j-1)-й момент времени, а у_i0=0 (в качестве элемента задержки может быть использован D-триггер). Тогда сигналы на первом, втором выходах предлагаемого компаратора будут определяться выражениямиThe work of the proposed comparator of binary numbers is as follows. At his first and second entrances to the jth

moment of time, binary signals x _{1 (nj)} ∈ {0,1} and x _{2 (nj)} ∈ {0,1} are given, which specify the values of the (nj) -th digits of the n-bit binary numbers x ₁ = x to be compared _{1 (n-1)} ... x _10, and x ₂ = x _{2 (n-1)} ... x ₂₀ . Here, the signals x _{i (nl)} and x _i0

determine the values of the highest and lowest digits of the number x _i, respectively. The signal at the output of the delay element 1 _i at the jth moment of time is equal to the signal that acted at its input at the (j-1) th moment of time, and at _i0 = 0 (a D trigger can be used as a delay element). Then the signals at the first, second outputs of the proposed comparator will be determined by the expressions

where y ₁₀ = y ₂₀ = 0. The table below shows the values of the functions realized by expressions (1) on all possible sets of values of their arguments.

at _{l (jl)} y _{2 (jl)} x _{l (nj)} x ₂ (nj) at _lj At _2j 0 0 0 0 0 0 0 0 0 one 0 one 0 0 one 0 one 0 0 0 one one 0 0 0 one 0 0 0 one 0 one 0 one 0 one 0 one one 0 0 one 0 one one one 0 one one 0 0 0 one 0 one 0 0 one one 0 one 0 one 0 one 0 one 0 one one one 0

An analysis of the data given in the table allows us to conclude that: 1) if _{l (jl)} = y _{2 (j-1)} = 0 and x _{1 (nj)} = x _{2 (nj)} , then _lj = y _2j = 0; 2) if y _{l (jl)} = y _{2 (j-1)} = 0 and x _{l (nj)} > x _{2 (nj)} ( _{1 (jl)} = y _{2 (jl)} = 0 and x _{l (nj)} <x _{2 (nj)} ) _, then _lj = 1 and _2j = 0 ( _lj = 0 and _2j = 1); 3) if y _{1 (jl)} = 1 and y _{2 (jl)} = 0 (y _{1 (jl)} = 0 and y _{2 (jl)} = 1), then y _1j = 1 and y _2j = 0 (y _1j = 0 and y _2j = 1) Thus, when x ₁ = x ₂ or x ₁ > x ₂ or x ₁ <x _2, respectively, we have _1n = y _2n = 0 or y _1n = 1, y _2n = 0 or y _1n = 0, for _2n = 1. Moreover, the proposed comparator contains ten elements. Note that the prototype includes twelve elements.

подаются на соответствующие входы предлагаемого компаратора в j-й момент времени, а сигналы x_i(n-1) и x_i0

определяют значения соответственно старшего и младшего разрядов числа x_i.The above information allows us to conclude that the proposed binary number comparator has lower hardware costs compared to the prototype and performs the recognition of the relations x ₁ = x ₂ , x ₁ > x ₂ , x ₁ <x ₂ , where x ₁ = x _{1 (n- 1)} ... x ₁₀ , x ₂ = x _{2 (n-1)} ... x ₂₀ - n-bit binary numbers given by the binary signals x ₁₀ , _... , x _{1 (n-1)} , x ₂₀ , ..., x _{2 ( n-1)} ∈ {0,1}, and the signals x _{1 (nj)} , x _{2 (nj)}

fed to the corresponding inputs of the proposed comparator at the j-th moment of time, and the signals x _{i (n-1)} and x _i0

determine the values of the highest and lowest digits of the number x _i, respectively.

Claims (1)

A binary number comparator containing two NOT elements, two AND elements, two OR elements and two delay elements, characterized in that two OR elements are additionally introduced into it, with the first, second inputs and output of the ith

OR elements are connected respectively to the output of the i-th AND element, the first input of the (i + 2) th OR element and the input of the i-th delay element connected to the first input of the (i + 2) OR element, the second input and output which are connected respectively to the first input of the i-th element AND and the input of the i-th element NOT connected to the second input of the (3-i) -th element And, the first input of which is connected to the (3-i) -th input of the binary number comparator connected by the i-th output to the output of the i-th OR element.