RU189024U1 - BINARY COMPARATOR - Google Patents

Abstract

The invention relates to electronics and is intended for use in counting and control devices. Its technical result, which consists in simplifying the device and improving performance, is achieved through the use of logical elements of only one type - 2IL-NOT and combining them into a tree-like chain, whose critical paths from inputs to outputs contain no more than 2K + 3 stages, where K equal to the rounded to the nearest larger integer value of the logarithm on the base two from the bit width of the compared numbers N, that is, in each input block 1-0, ... 1-6 comparison of bits entered the third logic element 5 2 OR-NOT. The device diagram also denotes blocks 2-0, ... 2-5 combining the results of partial comparisons and the remaining logic elements 3, 4 and 6, ... 10 2OR-NOT. The device generates signals of three signs comparing two numbers A and B with the digits a, a, ... a and b, b, ... b according to the following logical formulas: 1il.

Description

The utility model relates to electronics and is intended for use in counting and control devices made on logic elements 2ИЛИ-НЕ, in particular, from the composition of serial microcircuits of a small degree of integration.

Known comparators of binary numbers of a certain width. See, for example, US Patent No. 3,310,1035 NPC 340-146.2, published May 10, 1966 [1]. Such devices have limited capabilities for processing multi-digit numbers.

This disadvantage is eliminated in the device described in the patent of the Russian Federation No. 2300132 IPC G06F 7/02 and G05B 1/03, published on May 27, 2007 [2]. According to its technical essence, it is the closest to the claimed utility model.

This device contains input blocks that perform comparisons of pairs of digits of numbers of the same order, blocks combining the results of partial comparisons, and a signal generator of the sign of equality of numbers. The device performs the function of comparing two binary numbers A and B of arbitrary width N: F _{A> B} , F _{A <B} and F _{A = B} , whose logical expressions are the following formulas.

where a _i and b _i are the i-th order bits of the compared numbers A and B, and the inequality bracketed represent logical variables that take true and false values, respectively, when executing and not performing the inequalities enclosed in brackets.

The device sequentially attaches the result of comparing the next pair of digits of the numbers of the next in descending order to the result of comparing fragments of numbers containing previous digits. This reduces the speed, since the critical distribution circuit of signals from the inputs a _N-1 and b _N-1 most significant digits of the numbers to the outputs consists of all serially connected functional blocks of the device.

которые сложно реализуются в КМОП и ТТЛ схемотехнических базисах, а элементы ЗАПРЕТ представлены не во всех сериях логических микросхем.The disadvantage of a binary number comparator is also the complexity of its implementation on CMOS and TTL types of microcircuits and on elements of microcircuits of a small degree of integration. It uses logical elements 2ILI and BAN

which are difficult to implement in CMOS and TTL circuitry bases, and the elements of the prohibition are not presented in all series of logic circuits.

The technical result of the utility model is to simplify the device by reducing the number of types of logic elements used to one and improving performance by reducing the number of stages of logic elements in the circuits of propagation of signals from the inputs to the outputs of the device.

целого значению логарифма по основанию два от N, то есть

у блоков объединения результатов частичных сравнений, составляющих первый каскад, первые, вторые и третьи, четвертые входы соответственно подключены к первым, вторым выходам блоков сравнения разрядов четных и нечетных номеров, следующих в порядке возрастания от 0 до N-1, если N - четно, или до N-2, если N - нечетно, в каждом следующем каскаде первые, вторые и третьи, четвертые входы блоков объединения результатов частичных сравнений подключены к первым, вторым выходам аналогичных блоков предыдущего каскада в порядке возрастания номеров соответствующих им разрядов сравниваемых чисел, если в предыдущих каскадах отсутствуют связи выходов блока сравнения разрядов и блока объединения результатов частичных сравнений или двух блоков объединения результатов частичных сравнений, первые, вторые выходы этих блоков в порядке возрастания номеров соответствующих разрядов сравниваемых чисел подключены к первому, второму и третьему, четвертому входам последнего по порядку блока объединения частичных результатов сравнения данного каскада, первый и второй выходы блока объединения результатов частичных сравнений последнего К-го каскада соответственно являются выходами устройства для сигналов превышения первого числа вторым - А<В и второго числа первым - А>В, а также подключены ко входам логического элемента 2ИЛИ-НЕ формирователя сигнала признака равенства чисел.The technical result is achieved by the fact that in a binary number comparator containing blocks of comparison of bits in an amount equal to the digit capacity of N numbers, and each block of comparison of digits consists of the first and second elements, the first inputs and outputs of which are respectively the first and second inputs and outputs of the block, the first and second inputs of the bit comparison blocks are connected to pairs of inputs of bits a _i and b _{i of the} first and second numbers A and B of order i = 0, 1, ... N-1, blocks combining the results of partial comparisons, each of which consists of the first second and second elements, the first inputs of which, respectively, are the first and second inputs of the unit, and the second inputs are its third and fourth inputs, the third and fourth elements, the first inputs of which are respectively connected to the outputs of the first and second elements, the second to the fourth and third inputs block, and the outputs, respectively, are its first and second outputs, the signal generator of the sign of equality of numbers on the logical element 2OR-NOT, the output of which is the output of the device for the equality signal of the compared numbers - A = B, all elements of the device are logical elements 2, OR-NOT, and in each input block of comparison of discharges a third logical element 2 OR-NO is additionally entered, whose inputs are connected to the inputs of the block, and the output is connected to the second inputs of the first and second elements, the number of blocks combining the results of partial comparisons is N-1, they form a tree chain consisting of several cascades, the number of which is K, is equal to rounded to the nearest

integer to the logarithm of base two from N, that is,

in units of combining the results of partial comparisons constituting the first cascade, the first, second and third, fourth inputs are respectively connected to the first, second outputs of the block of comparison of even digits and odd numbers, following in ascending order from 0 to N-1, if N is even, or up to N-2, if N is odd, in each next stage the first, second and third, fourth inputs of the combination combining results block of partial comparisons are connected to the first, second outputs of the similar blocks of the previous cascade in ascending order of numbers correspondingly compared digits, if in previous cascades there are no links between the outputs of the bits comparison block and the combining block of partial comparison results, or two blocks of combining partial comparison results, the first, second outputs of these blocks are connected to the first, second, and second numbers in increasing order of the corresponding digits of the compared numbers. the third and fourth inputs of the last in order block for combining partial results of a comparison of a given cascade; the first and second outputs of the combining block are The tatts of partial comparisons of the last K-th stage, respectively, are the device outputs for signals exceeding the first number, the second —A <B, and the second number — the first —A> B, and are also connected to the inputs of the logical element 2IL-NOT of the signal generator of the equality of numbers.

The specified implementation of the device allows you to use it only logical elements of type 2 OR-NOT and reduce their number in the critical circuits of the signals from the inputs to the outputs to 2K + 3, where

Distinctive features of the utility model are the type and presence of additional elements, electrical connections of the elements and units of the device.

The utility model is illustrated by a drawing of the electric circuit of a comparator of two 7-bit binary numbers.

The binary number comparator contains blocks 1-0, ... 1-6 comparison of bits in an amount equal to the digit capacity of the numbers N = 7 and blocks 2-0, ... 2-5 combining the results of partial comparisons in the number N-1 = 6. Each block 1-0, ... 1-6 comparison of bits consists of the first, second and third logic elements 3, 4 and 5 2, OR-NOT. The first, second inputs and outputs of elements 3 and 4, respectively, are the first, second inputs X, Y and outputs X <Y, X> Y of the block, at element 5 the inputs are connected to the inputs of the block X and Y, and the output is connected to the second inputs of elements 3 and 4. The first and second inputs X, Y of the bit comparison blocks are connected to the pairs of inputs a _i and b _{i of the} bits of the first and second numbers A and B in ascending order of numbers i = 0, 1, ... 6. Each block 2-0, ... 2-5 combining the results of partial comparisons consists of the first and second logical elements 6 and 7 2, OR-NOT, the first inputs of which, respectively, I lyayutsya first and second inputs of X ₀ and Y ₀ block and second inputs - with third and fourth inputs X ₁ and Y _1, the third and fourth AND gates 8 and 9 2or NOR first inputs of which are respectively connected to the outputs of the elements 6 and 7 , the second - with the fourth and third inputs Y ₁ and X _{1 of the} block, and the outputs respectively are its first and second outputs X ₁ X ₀ <Y ₁ Y ₀ and X ₁ X ₀ > Y ₁ Y ₀ . Blocks 2-0, ... 2-5 combining the results of partial comparisons form a three-cascade tree-like chain; in blocks 2-0, 2-1 and 2-2, which constitute the first cascade, the first, second and third, fourth inputs X ₀ , Y ₀ and X ₁ , Y ₁ respectively connected to the first, second outputs X <Y, X> Y blocks 1-0 and 1-1, 1-2 and 1-3, 1-4 and 1-5 comparison of digits of even and odd numbers ( a ₀ , b ₀ and a ₁ , b ₁ (a ₂ , b ₂ and a ₃ , b ₃ ), (a ₄ , b ₄ and a ₅ , b ₅ ). In the second cascade, the first, second and third, fourth inputs X ₀ , Y ₀ and X ₁ Y ₁ blocks 2-3 are connected to the first, second outputs X ₁ X ₀ <Y ₁ Y ₀ , X ₁ X ₀ > Y ₁ Y ₀ blocks 2-0, 2-1, and inputs X _0, Y ₀ and X _1, Y ₁ b 2-4, respectively, are connected to the first, second outputs of block 2-2 and to the first, second outputs of block 1-6, since for N = 7 the numbers of 1-0, ... 1-6 comparison of bits and blocks 2 are odd 0, ... 2-2 combining the results of partial comparisons in the first cascade. In the third cascade of block 2-5, the first, second and third, fourth inputs X ₀ , Y ₀ and X ₁ , Y _{1 are} respectively connected with the first, second outputs X ₁ X ₀ <Y ₁ Y ₀ , X ₁ X ₀ > Y ₁ Y ₀ blocks 2-3 and 2-4, and its first and second outputs, respectively, are outputs of the device for the signals of the first number exceeding the second - A <B and the second number is first - A> B, and also connected to the inputs of the logic element 10 2IL-NOT of a signal generator of the sign of equality of numbers, the output of which is the device output for the equality signal of the compared numbers - A = B.

The device works as follows.

Comparison of pairs of digits a _i and b _{i of the} same order of i of numbers A and B is explained in the following table.

The table shows that for any combination of signals a _i and b _i, only one of all the signs corresponds to a single logical signal and it suffices to form only signals that identify inequalities by which an equality signal can be obtained.

The system of logical functions that responds to the table is

The signals of the functions F _{ia <b} and F _{ia> b of} system (1) form blocks 1-0, ... 1-6 comparison of bits on their first and second outputs X <Y and X> Y, using signals a _i and b _i , arriving on their first and second inputs X and Y.

The results of the comparison of single-bit parts of the compared numbers then go to the inputs X ₀ , Y ₀ and X ₁ , Y _{1 of} blocks 2-0, ... 2-2 combining the results of partial comparisons that make up the first stage, which form from them the signals of the signs of comparison of three pairs 2- bit parts composed of digits of the compared numbers of the 0th and 1st, 2nd and 3rd, 4th and 5th orders.

младший разряд a_i. Аналогичным образом определяется превосходство второго числа из разрядов b_i+1b_i.Part of the first number of digits a _{i + 1} a _{i is} greater than the similar part of the second - b _{i + 1} b _i , if the most significant digit of a _{i + 1 is} greater than b _{i + 1} , and in the case of equality of these digits, if the first number has

low order a _i . Similarly, the superiority of the second number of bits b _{i + 1} b _{i is} determined.

и склеить с ними содержащиеся там члены по логическим формулам

Formulas (2) and (3) can be simplified if the excess conjunctions are entered in the brackets

and glue the members there with them using logical formulas

In the final form, formulas (4), (5) are applicable for combining any partial comparison results if the terms F _{i + 1 a> b} , F _{i + 1 a <b} and F _{i a> b} , F _{i a <b} in them be considered as signs of comparison of parts made up of higher and lower order ones, respectively. Inversions of the signs F _{i + 1 a <b} and F _{i + 1 a> b} in them are presented as a condition for considering the correlation of the lower parts at the same time and the equality of the older parts, and the superiority of one of them, which has already entered as signs F _{i + 1 a> b} and F _{i + 1 a <b} , i.e.

, соответствующую признаку Х₁Х₀<Y₁Y₀ и функцию

для признака X₁X₀>Y₁Y₀. С учетом формул (6), применяя логический закон поглощения для конъюнкции -х(у+х)=х, замена условных переменных Х₀, Y₀ и Х₁, Y₁ на соответствующие признаки сравнения в выражениях функций блоков объединения результатов частичных сравнений приводит эти выражения к виду, эквивалентному формулам (4) и (5):The signals Fi _{i a <b} and Fi _{i a> b} signs of comparing parts of the low-order bits come to the inputs X ₀ and Y ₀ , and F _{i + 1 a <b} and F _{i + 1 a> b} for the parts of the following by seniority - to the inputs X ₁ and Y ₁ . Each of blocks 2-0, ... 2-5 performs the function

corresponding to the attribute X ₁ X ₀ <Y ₁ Y ₀ and the function

for the sign X ₁ X ₀ > Y ₁ Y ₀ . Taking into account formulas (6), applying the logical law of absorption for the conjunction x (y + x) = x, replacing the conditional variables X ₀ , Y ₀ and X ₁ , Y ₁ with the corresponding comparison signs in the expressions of functions of the combining blocks of partial comparisons results these expressions to a form equivalent to formulas (4) and (5):

In the second stage, blocks 2-3 and 2-4 from the results of the comparisons a ₁ a ₀ with b ₁ b ₀ , and ₃ a ₂ with b ₃ b ₂ and a ₅ a ₄ with b ₅ b ₄ , and ₆ with b ₆ respectively form the signs of comparing parts of the four low and three high digits: a ₃ a ₂ a ₁ a ₀ , b ₃ b ₂ b ₁ b ₀ and a ₆ a ₅ a ₄ , b ₆ b ₅ b ₄ . They are then combined by block 2-5 of the third, in this case, the last stage, the outputs of which serve as outputs of the signals of signs of inequalities A <B and A> B.

, формирует элемент 10 2ИЛИ-НЕ.Equality of numbers A and B is achieved in the case of equality of pairs of constituent digits of the same order, but it also corresponds to the conjunction of inversions of signs of inequalities, since only at A = B both statements about superiority of A over B and B over A will be false. Signal signal A = B, corresponding to conjunction

, forms the element 10 2ILE-NOT.

From the description of the operation of the device, it should be seen that each block combining the results of partial comparisons of two pairs of comparison signs of two successive pairs of parts of compared numbers forms one pair of signs for fragments of numbers composed of these parts. On each cascade of these blocks, the number of compared parts, of which pairs can be made, and their corresponding signs, are halved. If for one part there is no pair, it is transmitted to the nearest of the subsequent cascades, where it can unite with one remaining there without a pair of parts. This happens before the complete unification of all parts.

The maximum number N of digits of numbers, signs of which can combine a tree-like chain of blocks consisting of K cascades, is 2 ^K. And if the number of digits exceeds 2 ^K , but less than 2⋅2 ^K remains, K + 1 cascade will be needed. Consequently, the number of cascades K is equal to the degree to which the number 2 should be erected in order to obtain the nearest integer exceeding N, which expresses the formula

The expression for the number of units combining the results of partial comparisons is easy to obtain for the case of equality of the digit capacity of N to 2, to some extent, that is, N = 2 ^K. Since in the first cascade the number of blocks is N / 2 and is halved on each next cascade, their total number will correspond to the sum of K terms of the geometric progression with the denominator q = 0.5. According to the well-known expression of the sum S _K through q, the first and last members of the progression p ₁ = 2 ^K-1 and p _K = 1

This number will remain equal to N-1 for any N because each increase in N by one digit will require adding one block.

последовательных элементов.Thus, the comparator of two N-bit binary numbers performs its functions, having in its composition 7N-3 logic element 2IL-NOT connected to a tree-like chain in which the propagation paths of signals from inputs to outputs contain no more than

consecutive elements.

Claims (1)

A binary number comparator containing blocks of comparison of bits in an amount equal to the digit capacity of N numbers, each block of bits comparison consists of the first and second elements, the first inputs and outputs of which are respectively the first and second inputs and outputs of the block, the first and second inputs of the bits comparison blocks are connected to the pairs of inputs of digits a _i and b _i of the first and second numbers A and b of the order of i = 0, 1, ... N-1 blocks of the partial combining results of comparisons, each of which consists of first and second elements, first inputs of which with responsibly are the first and second inputs of the block, and the second inputs are its third and fourth inputs, the third and fourth elements, the first inputs of which are respectively connected to the outputs of the first and second elements, the second to the fourth and third inputs of the block, and the outputs respectively are its first and the second outputs, the signal conditioner of the sign of equality of numbers on the logical element 2OR-NOT, the output of which is the output of the device for the equality signal of the compared numbers - A = B, characterized in that all elements of the device a are logical elements 2ILI — NOT; a third logic element 2ILI-NOT is added to each input block of comparison of discharges, whose inputs are connected to the inputs of the block, and the output is connected to the second inputs of the first and second elements, the number of units combining the partial comparison results is N- 1, they form a tree chain consisting of several cascades, the number of which K is equal to rounded to the nearest

the integer value of the logarithm of base two from N, i.e.

in units of combining the results of partial comparisons constituting the first cascade, the first, second and third, fourth inputs are respectively connected to the first, second outputs of the block of comparison of even digits and odd numbers, following in ascending order from 0 to N-1, if N is even, or up to N-2, if N is odd, in each next stage the first, second and third, fourth inputs of the combination combining results block of partial comparisons are connected to the first, second outputs of the similar blocks of the previous cascade in ascending order of numbers correspondingly compared digits, if in previous cascades there are no links between the outputs of the bits comparison block and the combining block of partial comparison results, or two blocks of combining partial comparison results, the first, second outputs of these blocks are connected to the first, second, and second numbers in increasing order of the corresponding digits of the compared numbers. the third and fourth inputs of the last in order block for combining partial results of a comparison of a given cascade; the first and second outputs of the combining block are The tatts of partial comparisons of the last K-th stage, respectively, are the device outputs for signals exceeding the first number, the second —A <B, and the second number — the first —A> B, and are also connected to the inputs of the logical element 2IL-NOT of the signal generator of the equality of numbers.

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