RU2762061C1 - Binary number comparator - Google Patents

Abstract

FIELD: electronics.

SUBSTANCE: invention relates to electronics and is intended for use in integrated circuits of counting and control devices on complementary field-effect transistors of the metal-oxide-semiconductor (CMOS) structure. The device contains units for comparing digits containing an inverter, element 2AND-NOT and element 2OR-NOT, blocks for combining the results of partial comparisons forming a tree-like chain and implementing functions

,

, and a signal generator for the sign of equality of numbers made on element 2OR-NOT.

EFFECT: increase in performance.

3 cl, 12 dwg, 1 tbl

Description

The invention relates to electronics and is intended for use in integrated microcircuits of counting and control devices on complementary field-effect transistors of the metal-oxide-semiconductor (CMOS) structure.

Known comparators of binary numbers of arbitrary width. See, for example, RF patent No. 2300132 IPC G06F 7/02 and G05B 1/03, published on May 27, 2007 [1]. Such devices sequentially combine the results of comparing pairs of digits of numbers following in a certain order of powers, which reduces performance.

This drawback is eliminated in the device described in the RF patent for utility model No. 189024 IPC G06F 7/02, H03K 5/22, G05B 1/03, published on May 06, 2019 [2]. In its technical essence, it is the closest to the claimed invention.

The closest analogue contains blocks for comparing digits and blocks for combining the results of partial comparisons, forming a tree-like chain, consisting of several cascades, the number of which K is equal to the rounded down to the nearest larger integer value of the logarithm to base two of the digit capacity of the compared numbers N, that is

The outputs of the unit for combining the results of partial comparisons of the last stage are the outputs of the device for signals of exceeding the first number by the second and second numbers first, and are also connected to the inputs of the logic element 2OR-NOT of the signal generator of the sign of equality of numbers.

Comparison units of the digits and units for combining the results of partial comparisons are also made on logical elements 2OR-NOT, which are combined into two-stage serial circuits, which reduces the speed of the units and the device as a whole.

у блоков объединения результатов частичных сравнений, составляющих первый каскад, первые, вторые и третьи, четвертые входы соответственно подключены к первым, вторым выходам блоков сравнения разрядов четных и нечетных номеров, следующих в порядке возрастания от 0 до N - 1, если N - четно, или до N - 2, если N - нечетно, в каждом следующем каскаде первые, вторые и третьи, четвертые входы блоков объединения результатов частичных сравнений подключены к первым, вторым выходам аналогичных блоков предыдущего каскада в порядке возрастания номеров соответствующих им разрядов сравниваемых чисел, если в предыдущих каскадах отсутствуют связи выходов блока сравнения разрядов и блока объединения результатов частичных сравнений или двух блоков объединения результатов частичных сравнений, первые, вторые выходы этих блоков в порядке возрастания номеров соответствующих разрядов сравниваемых чисел подключены к первому, второму и третьему, четвертому входам последнего по порядку блока объединения результатов частичных сравнений данного каскада, второй выход блока объединения результатов частичных сравнений последнего К-го каскада является выходом устройства для сигнала превышения второго числа первым - А>В и подключен ко второму входу элемента 2ИЛИ-НЕ формирователя сигнала признака равенства чисел, внесены следующие отличия.The technical result of the invention, which consists in eliminating this drawback, is achieved by the fact that in a binary number comparator containing bit comparison blocks in an amount equal to the digit capacity of numbers N, each bit comparison block consists of a first element and a second, third element, the first inputs of which are connected to the output of the first element, and the outputs, respectively, are the first, second outputs of the block, the input of the first element and the second input of the second element, respectively, are the first and second inputs of the block, the third element is a logical element 2 OR-NOT, blocks for combining the results of partial comparisons, each of which has the first to the fourth inputs and consists of the first and second elements, the outputs of which are respectively the second and first outputs of the block, the generator of the signal of the sign of equality of numbers on the logical element 2OR-NOT, the output of which is the output of the device for the signal of equality of the compared numbers - A = B, the number combining units i results of partial comparisons are equal to N - 1, they form a tree-like chain, consisting of several cascades, the number of which K is equal to the rounded up to the nearest larger integer value of the logarithm base two from N, that is

in the blocks for combining the results of partial comparisons that make up the first stage, the first, second and third, fourth inputs are respectively connected to the first, second outputs of the blocks for comparing the digits of even and odd numbers, following in ascending order from 0 to N - 1, if N is even, or up to N - 2, if N is odd, in each next cascade the first, second and third, fourth inputs of the blocks for combining the results of partial comparisons are connected to the first, second outputs of similar blocks of the previous cascade in ascending order of the numbers of the corresponding digits of the compared numbers, if in previous stages there are no connections between the outputs of the digit comparison unit and the unit for combining the results of partial comparisons or two blocks for combining the results of partial comparisons, the first and second outputs of these blocks in ascending order of the numbers of the corresponding digits of the compared numbers are connected to the first, second and third, fourth inputs of the last block in order combining the results At the partial comparisons of this cascade, the second output of the unit for combining the results of partial comparisons of the last K-th cascade is the output of the device for the signal when the second number is exceeded first - A> B and is connected to the second input of the 2OR-NOT element of the signal generator of the sign of equality of numbers, the following differences are introduced.

The first and second elements of each unit for comparing the device bits are respectively an inverter and a 2NOR logic element, the second input of which is connected to the second input of a 2ORNO logic element.

а нулевые значения -

входы переменных Y первого и второго элементов

соответственно являются первым и вторым входами блока, входы переменных Z и X - соответственно соединены и являются третьим и четвертым входами блока.In each block for combining the results of partial comparisons, both elements perform a logical function of three variables X, Y, Z, the unit values of which correspond to the expression

and zero values -

inputs of Y variables of the first and second elements

respectively, they are the first and second inputs of the block, the inputs of the variables Z and X are respectively connected and are the third and fourth inputs of the block.

The generator of the signal of the sign of equality of numbers additionally contains an inverter, the input of which is connected to the first output of the unit for combining the results of partial comparisons of the last K-th stage, and the output to the first input of the element 2 OR-NOT and is the output of the device for the signal when the first number is exceeded by the second - A <B ...

The inputs of each block for comparing the digits are connected to a pair of inputs of digits a, and b, the compared numbers A and B of the corresponding order i = 0, 1, ... N - 1, moreover, if an even number of sequential connected blocks combining the results of partial comparisons, the first and second inputs of the block are respectively connected to the inputs a _i and b _i , and if odd, then to the inputs b _i and a _i .

The discharge comparison units have two variants of execution, in each of them the unit contains from the first to the fifth MOS transistors of the enriched type with induced p-type channels and from the first to the fifth MOS transistors of the enriched type with induced n-type channels, the sources from the first to the fourth p-MOS transistors are connected to the positive supply voltage bus, and the sources of the first and third to fifth n-MOS transistors are connected to the zero potential bus, the gates of the first p- and n-MOS transistors are connected and are the first input of the block, the drain the fourth p-MOS transistor is connected to the source of the fifth p-MOS transistor, and the source of the second n-MOS transistor is connected to the drain of the third n-MOS transistor, the drains of the second, third p-MOS and second n-MOS transistors are connected with the first output of the block, the drains of the fifth p-MOS- and fourth, fifth n-MOS transistors are connected to the second output of the block.

In the first embodiment of the block for comparing the discharges, the gates of the second, fourth p-MOS and third, fourth n-MOS transistors are connected and are the second input of the unit, and the gates of the third, fifth p-MOS and second, fifth n-MOS transistors are connected and connected to the drains of the first p- and n-MOS transistors.

In the second version of the discharge comparison unit, the gates of the second, fourth p-MOS- and third, fourth n-MOS transistors are connected and connected to the drains of the first p- and n-MOS transistors, and the gates of the third, fifth p-MOS and second , the fifth n-MOS transistors are connected and are the second input of the block,

а нулевые значения - выражению

содержит первые, вторые и третьи МОП-транзисторы обогащенного типа с индуцированными каналами р- и n-типов проводимости, затворы которых попарно соединены и соответственно являются входами сигналов X, Y и Z, истоки первых и третьих р- и n-МОП-транзисторов соответственно подключены к шинам положительного напряжения питания и нулевого потенциала, стоки первого р-МОП- и третьего n-МОП-транзисторов соответственно соединены с истоками вторых р- и n-МОП-транзисторов, стоки которых и стоки третьего р-МОП- и первого n-МОП-транзисторов соединены с выходом элемента.Each element that performs a function whose single values correspond to the expression

and zero values - to the expression

contains the first, second and third enriched-type MOS transistors with induced channels of p- and n-types of conductivity, the gates of which are connected in pairs and, respectively, are the inputs of signals X, Y and Z, the sources of the first and third p- and n-MOS transistors, respectively connected to the buses of positive supply voltage and zero potential, the drains of the first p-MOS- and third n-MOS transistors, respectively, are connected to the sources of the second p- and n-MOS transistors, the drains of which and the drains of the third p-MOS- and the first n- MOS transistors are connected to the output of the element.

Each block for comparison of the discharges of both variants is structurally made in the form of the first and second regions of the p-type MOS structures adjacent to the longitudinal sides and the adjacent longitudinal sides of the also adjacent first and second regions of the n-type MOS structures, across the first regions of the p- and n- The first strip of gates passes through the MOS structures, connected to the first input of the block, across all four regions, the second strip of gates runs, connected to the p- and n-source-drain regions of the first p- and n-MOS- structures, and the third strip of gates, connected to the second input of the block, in the parts of the first regions of p- and n-MOS structures separated by the first strip of gates and in the second regions of p- and n-MOS structures, the second and third strips of gates each separate three regions sources and sinks of the corresponding types.

In the first embodiment of the discharge comparison unit, the first regions of the p- and n-MOS structures are located at the edges of the block, and the second regions of the p- and n-MOS structures are adjacent to each other, the p-region of the sources-drains between the first and second strips of gates of the first region of p-MOS structures and the outermost p-regions of the sources-drains of both regions of the r-MOS structures from the side of the third strip of gates are connected to the bus of positive supply voltage, the n-region of sources-drains between the first and second strips of gates of the first region n- MOS structures and the n-region of the sources-drains of both regions of the n-MOS structures from the side of the third strip of gates are connected to the zero potential bus, the p-region of the sources-drains of the first region of the p-MOS structures between the second and third strips of gates and the extreme from the side of the second strip of gates, the n-region of the source-drain of the second region of n-MOS structures are connected to the first output of the block, the n-region of the sources-drains of the first region of n-MOS structures between the second and third strips of gates and the extreme from the side of the second strip of gates, the p-area of the source-drain of the second area of the p-MOS structures are connected to the second output of the block.

In the second version of the discharge comparison unit, the first regions of the p- and n-MOS structures are adjacent to each other, and the second regions of the p- and n-MOS structures are located at the edges of the block, the p-source-drain region between the first and second strips of gates the first region of p-MOS structures and the extreme p-regions of the sources-drains of the second region of p-MOS structures are connected to the bus of positive supply voltage, the n-region of the sources-drains between the first and second strips of gates of the first region of n-MOS structures and the extreme The n-region of the sources-drains of the second region of n-MOS structures are connected to the zero potential bus, the p-region of the sources-drains of the second region of the r-MOS structures between the second and third strips of gates and the n-region of the source, which is extreme from the side of the third strip of gates. drain of the first region of n-MOS structures are connected to the first output of the block, the n-region of sources-drains of the second region of n-MOS structures between the second and third strips of gates and the p-region of the source-drain of the first region ST p-MOS structures are connected to the second output of the block.

The numbers of comparison units of digits, made according to the first and second options, differ by no more than one.

а нулевые значения - выражению

конструктивно выполнен в виде двух смежных продольными сторонами областей МОП-структур р- и n-типов проводимости, пересеченных поперек тремя общими полосками затворов, разделяющими МОП-структуры на области истоков-стоков соответствующих типов проводимости, первая-третья полоски затворов по порядку соединены со входами сигналов X, Y и Z, крайние р- и n-области истоков-стоков соответственно подключены к шинам положительного напряжения питания и нулевого потенциала, а области истоков-стоков р-типа между второй и третьей полосками затворов и n-типа между первой и второй полосками затворов соединены с выходом элемента.Each element that performs a function whose single values correspond to the expression

and zero values - to the expression

Structurally made in the form of two adjacent longitudinal sides of the regions of MOS structures of p- and n-types of conductivity, crossed across by three common strips of gates, dividing the MOS structures into regions of sources-drains of the corresponding types of conductivity, the first-third strips of gates are connected in order to the inputs signals X, Y and Z, the extreme p- and n-areas of the sources-drains are respectively connected to the buses of the positive supply voltage and zero potential, and the areas of the sources-drains of the p-type between the second and third strips of gates and n-type between the first and second strips of gates are connected to the outlet of the element.

The specified implementation of the comparator of binary numbers allows you to reduce the number of elements in the units for comparing the digits and in the units for combining the results of partial comparisons, and due to this, to reduce the number of sequentially connected stages of logic elements in the signal propagation circuits from the inputs of the device to the outputs, the proposed circuit implementation of the elements of the device on complementary MOS -transistors makes it possible to use certain design solutions of elements that provide a high packing density of the comparator of binary numbers in an integral design and a decrease in parasitic capacitances.

Distinctive features of the invention are circuitry, structural implementation of functional units of the device and their connections.

а нулевые значения -

примененного в блоках объединения результатов частичных сравнений, на фиг. 7, 8 и 10 - схемы конструктивного выполнения этих блоков и элемента, фиг. 11 и 12 демонстрируют возможности объединения р- и n-МОП-структур элементов

и блоков сравнения разрядов устройства.The invention is illustrated by drawings, Fig. 1, 2, 3 and 4 represent the functional electrical diagrams of the comparators of binary numbers with a width of 4, 5, 6 and 7, respectively, in FIG. 5, 6 and 9 show the schematic electrical diagrams, respectively, of the units for comparing the digits of the first, second versions and an element performing a function, the unit values of which correspond to the expression

and zero values -

applied in the units for combining the results of partial comparisons, in FIG. 7, 8 and 10 are diagrams of constructive execution of these blocks and element, FIG. 11 and 12 demonstrate the possibilities of combining p- and n-MOS structures of elements

and units for comparing the device discharges.

К=2 при N=4, а при N=5, 6 и 7 К=3.The comparator of binary numbers contains blocks 1-0, ... 1-6 for comparing digits in an amount equal to the number of digits N, in the examples given, taking values 4, 5, 6 and 7. Blocks 2-0, 2-1, 2-2, 3 -0, 3-1, and 4, combining the results of partial comparisons, the number of which is equal to N - 1, form a tree-like chain of several cascades, the number of which K is equal to the rounded up to the nearest higher integer value of the logarithm base two from N, that is,

K = 2 at N = 4, and at N = 5, 6 and 7 K = 3.

и

от входных переменных.Each block 1-0, ... 1-7 of the comparison of the digits consists of the first element 5 - the inverter, the second and third elements 6 and 7 with logical functions 2I-NOT and 2OR-NOT, respectively. Inverter input 5 is the first block input for variable and. The first inputs of elements 6 and 7 are connected to the output of element 5, the second inputs are connected and are the second input of the block for the variable v, and the outputs are the first and second outputs of the bit comparison unit corresponding to logical functions

and

from input variables.

а нулевые значения - выражению

входы переменных Y элементов 8 и 9 соответственно являются первым и вторым входами u₀ и v₀ блока, входы переменных Z и X обоих элементов 8 и 9 соответственно соединены и являются третьим и четвертым входами u₁ и v₁ блока, выходы элементов 8 и 9 соответственно являются вторым и первым выходами блока, выходные сигналы которых соответствуют инверсиям функций u₁⋅u₀+v₁ и u₁⋅v₀+v₁.Each block for combining the results of partial comparisons has the first, second and third, fourth inputs u ₀ , v ₀ and u ₁ , v ₁ , it consists of the first and second elements 8 and 9, performing the logical function of three variables X, Y, Z, unit whose values correspond to the expression

and zero values - to the expression

inputs of variables Y of elements 8 and 9, respectively, are the first and second inputs of u ₀ and v _{0 of the} block, inputs of variables Z and X of both elements 8 and 9, respectively, are connected and are the third and fourth inputs of u ₁ and v _{1 of the} block, outputs of elements 8 and 9 respectively, they are the second and first outputs of the block, the output signals of which correspond to the inversions of the functions u ₁ ⋅u ₀ + v ₁ and u ₁ ⋅v ₀ + v ₁ .

In the circuits of the comparators of 4-, 5-, 6- and 7-bit binary numbers in Figs. 1, 2, 3 and 4, the blocks 2-0, 2-1 and 2-2 of combining the results of partial comparisons constituting the first stages, the first and the second inputs u ₀ and v _{0 are} respectively connected to the first and second outputs of blocks 1-0, 1-2, 1-4, 1-6, comparing the digits a ₀ and b ₀ , a ₂ and b ₂ , a ₄ and b ₄ , a ₆ and b ₆ with even numbers, and the third and fourth inputs u ₁ and v ₁ - to the first and second outputs of blocks 1-1, 1-3, 1-5, comparing the digits a ₁ and b ₁ , a ₃ and b ₃ , a ₅ and b ₅ with odd numbers.

In the second stages, the first and second inputs u ₀ and v _{0 of} blocks 3-0 and 3-1 of combining the results of partial comparisons are connected to the first and second outputs of blocks 2-0 and 2-2 of the first stage, the third and fourth inputs u ₁ and v ₁ block 3-0 in each circuit are connected to the first and second outputs of block 2-1, and block 3-1 in FIG. 4 - with the first and second outputs of the block 1-6, which does not have a pair and. therefore, it is not associated with the blocks of combining the results of partial comparisons of the first stage. Block 1-4 in FIG. 2, only the outputs of block 3-0, which constitutes the second stage of combining the results of partial comparisons, could form a pair with its outputs.

The last stages of combining the results of partial comparisons in the circuit in FIG. 1 forms a block 3-0, and in FIGS. 2, 3 and 4 -blocks 4. The second outputs of block 3-0 in FIG. 1 and blocks 4 in FIGS. 2, 3 and 4 are the outputs of devices for signals when the second number is exceeded first - A> B.

The generator of the signal of the sign of equality of numbers consists of an inverter 10 and a logic element 11 with a 2OR-NOT function. The input of the inverter 10 is connected to the first output of block 3-0 in the circuit of FIG. 1 or block 4 in the diagrams of FIG. 2, 3 and 4. The output of the inverter 10 is connected to the first input of the element 11 and is the output of each device for the signal when the first number is exceeded by the second - A <B. The second input of element 11 is connected to the second output of block 3-0 or 4, and the output is the output of the device for the signal of equality of the compared numbers - A = B in all the examples given.

The inputs of each block 1-0, ... 1-6 of the comparison of digits are connected to a pair of inputs of digits a _i and b _{i of the} first and second numbers A and B of the corresponding order i = 0, 1, ... block 1-0, ... 1-6 before the outputs of the device contains an even number of serially connected blocks 2-0, 2-1, 2-2, 3-0, 3-1, 4 combining the results of partial comparisons, the first and second inputs of this block 1-0, ... 1-6 comparison of the digits are respectively connected to the inputs a _i and b _i , and if odd - then to the inputs b _i and a _i .

So, in the scheme of Fig. 1, the output signals of all blocks 1-0, ... 1-3 pass to the outputs along the circuits from two series-connected blocks 2-0 - 3-0 or 2-1 - 3-0 and for all blocks 1- 0, ... 1-3, the first and second inputs u and v are respectively connected to the inputs of the digits a ₀ and b ₀ , a ₁ and b ₁ , a ₂ and b ₂ , and ₃ and b _{3 of the} first and second numbers A and B.

In the diagrams of Figs. 2 and 3 and 4, the output signals of blocks 1-0, ... 1-3 pass through three stages of blocks 2-0 - 3-0 - 4 or 2-1 - 3-0 - 4, inputs u and v of blocks 1-0, ... 1-3 are respectively connected to the inputs of the digits b ₀ and a ₀ , b ₁ and a ₁ , b ₂ and a ₂ , b ₃ and a _{3 of the} second and first numbers B and A.

In block 1-4 in Fig. 2, the inputs u and v are respectively connected to the inputs of bits b ₄ and a ₄ , since the output signals of block 1-4 are directly fed to the inputs u ₁ and v _{1 of} block 4, which constitutes the last stage of combining the results of partial comparisons.

Similarly, to the inputs b ₄ and a ₄ , b ₅ and a ₅ , the inputs u and v of blocks 1-4,1-5 in FIG. 4, the output signals of which pass sequential circuits from three stages of blocks 2-2 - 3-1 - 4.

Blocks 1-4, 1-5 in Fig. 3 and 1-6 in FIG. 4 are connected to the outputs of the device by circuits from an even number of cascades of units for combining the results of partial comparisons. FIG. 3 they consist of blocks 2-2 and 4, and in FIG. 4 - from blocks 3-1 and 4. Therefore, the inputs u and v of blocks 1-4, 1-5 in FIG. 3 and block 1-6 in FIG. 4 are respectively connected to the inputs of digits a ₄ and b ₄ , a ₅ and b ₅ , and ₆ and b _{6 of the} first and second numbers A and B.

The device works as follows.

Comparison of pairs of digits a _i and b _{i of the} same order i of numbers A and B is made according to the following truth table.

The interconnection of the logical expressions corresponding to the comparison criteria allows to form only simpler signals identifying the inequalities of the digits, according to which an equality signal can be obtained. One pair of signals is sufficient, except for two pairs related by the mutual inversion ratio, corresponding to the expressions from columns 3 and 4, 5 and 6.

и

сигналы, соответствующие парам признаков из таблицы 1, занимающих колонки 3 и 6 или 4 и 5.Blocks 1-0, ... 1-6, depending on the connection of inputs u and v, form at their first and second outputs

and

signals corresponding to pairs of attributes from Table 1, occupying columns 3 and 6 or 4 and 5.

The results of the comparison of one-digit parts of the compared numbers then go to the inputs u ₀ , v ₀ and u ₁ , v _{1 of} blocks 2-0, ... 2-2 combining the results of partial comparisons that make up the first cascade, which form from them the results of comparing parts containing two the category of the compared numbers of the 0th and 1st, 2nd and 3rd, 4th and 5th orders.

The part of the first number of two digits a _{i + 1} a _{i is} greater than the analogous part of the second - b _{i + 1} b _i , if the most significant bit a _{i + 1 is} greater than b _{i + 1} , and if these digits are equal, if the least significant bit a _{i of the} first number exceeds the least significant bit b _{i of the} second. Similarly, the superiority of a part of the second number from the digits b _{i + 1} b _{i is} determined.

Parts of the numbers A and B, consisting of the digits of sequentially decreasing orders from i to j, in the following text and on the diagrams are designated as A _ij and B _ij , respectively, and the logical expressions of the signs of their comparison - as F (A _ii > B _ij ), F (A _ii <B _ij ), F (A _ii > B _ij ), F (A _ii <B _ij ). Similarly designated expression discharges comparing _{attributes: F (a i> b i} ), F (a i <b i), F (a i ≥b i), F (a i ≤b i).

,

и склеить с ними содержащиеся там члены по логическим формулам

Formulas (1) and (2) can be simplified by introducing redundant conjunctions in parentheses

,

and glue the terms contained there with them by logical formulas

Inverting formulas (3) and (4) allows you to obtain simple logical expressions for the remaining signs of inequality.

Actions corresponding to formulas (3) - (6) are performed by blocks 2-0, 2-1 and 2-2 of combining the results of partial comparisons.

принимают на входы X, Y, Z сигналы признаков a_i+1>b_i+1, a_i≥b_i, a_i+1≥b_i+1 и a_i+1>b_i+1, a_i>b_i, a_i+1≥b_i+1, i=0, 2, 4, из которых элемент 8 формирует сигналContained in each block 2-0 and 2-1 in the circuit of FIG. 1 and block 2-2 in FIG. 3 elements 8 and 9 with function

_{accept signals of signs a i + 1} > b _{i + 1} , a _i ≥b _i , a _{i + 1} ≥b _{i + 1} and a _{i + 1} > b _{i + 1} , a _i > b at inputs X, Y, Z _i , a _{i + 1} ≥b _{i + 1} , i = 0, 2, 4, of which element 8 forms the signal

which obviously corresponds to formula (4), and element 9 is the signal

corresponding to formula (5).

в блоках 2-0 и 2-1 в схемах Фиг. 2, 3 и 4 и в блоке 2-2 на фиг. 4 имеют на входах X, Y, Z сигналы признаков a_i+1<b_i+1, a_i≤b_i, a_i+1≤b_i+1 и a_i+1<b_i+1, a_i<b_i, a_i+1≤b_i+1, i=0, 2, 4. Их выходные сигналыElements 8 and 9 with function

in blocks 2-0 and 2-1 in the diagrams of FIG. 2, 3 and 4 and in block 2-2 of FIG. 4 have at the inputs X, Y, Z feature signals a _{i + 1} <b _{i + 1} , a _i ≤b _i , a _{i + 1} ≤b _{i + 1} and a _{i + 1} <b _{i + 1} , a _i < b _i , a _{i + 1} ≤b _{i + 1} , i = 0, 2, 4. Their output signals

and

correspond to formulas (3) and (6).

Formulas (3) - (6) are applicable for combining the results of comparing any parts, if the signs of comparison of digits are replaced by signs of comparison of parts from groups of digits.

In general, for i1> j1, i2 = j1 - 1> j2 the formulas will look like this:

Combining the results of comparing the two-digit parts according to these formulas is performed by blocks 3-0 and 3-1.

In the circuit of FIG. 1 block 3-0 generates signals according to the formulas

and in the diagrams of FIG. 2,3,4- by formulas

Block 3-1 in the circuit of FIG. 4 combines the results of comparing parts of different bit depth, it works according to the formulas

FIG. 1 block 3-0 makes up the last stage of combining the results of partial comparisons, the signal from its first output, corresponding to formula (7), through the inverter 10 enters the output of the device for signals of exceeding the first number by the second - A <B, and the second output in accordance with the formula (8) is directly the output of the A> B signals.

In the remaining examples of the binary number comparator in FIG. 2, 3 and 4, the last cascade of combining the results of partial comparisons is made up of blocks 4, they form the final expressions of signs for comparing numbers according to the following formulas.

FIG. 2

FIG. 3

Figure 4

Signals of the sign A = B in this device are formed by element 11 2OR-NOT as a conjunction of inversions of signals of signs of superiority A over B and B over A, since both of these signs can be simultaneously false only if the numbers A and B.

From the description of the operation of the device, it should be seen that each block for combining the results of partial comparisons of two pairs of comparison features of two successive pairs of parts of the compared numbers forms one pair of features for the number fragments composed of these parts. At each cascade of these blocks, the number of parts to be compared, from which pairs can be made, and the corresponding comparison signs, are halved. If there is no pair for one part, it is transmitted to the nearest of the subsequent cascades, where it can combine with one part left there without a pair. This happens until all parts are completely unified.

The maximum number of N digits of numbers, the signs of which can be combined by a tree-like chain of blocks, consisting of K cascades, is 2 ^K. And if the number of discharges exceeds 2 ^K , but remains less than 2⋅2 ^K , K + 1 cascade will be needed. Therefore, the number of cascades K is equal to the power to which the number 2 should be raised in order to obtain the nearest integer greater than N or equal to it, which expresses the formula

The expression for the number of blocks for combining the results of partial comparisons is easy to obtain for the case of equality of the bit width N to 2, to some integer power, that is, N = 2 ^K , since in the first stage the number of blocks is equal to N / 2 and is halved at each subsequent stage , their total number will correspond to the sum S _K of K members of a geometric progression with the denominator q = 0.5. Substituting this value q, the values of the first and last members of the progression p ₁ = 2 ^K-1 and p _K = 1 into the well-known formula, we obtain the following expression for the sum S _K.

The number of blocks for combining the results of partial comparisons will remain equal to N - 1 for any N, because each increment of N by one bit requires adding one block.

The elements of the device are proposed to be made on complementary field-effect transistors of MOS structures and structurally implemented in the form of regions of MOS structures of p- and n-types of conductivity adjacent to the longitudinal sides, crossed across by gate strips dividing MOS structures into regions of source-sinks of the corresponding types.

блоков первого и второго вариантов выполнения, а стоки МОП-транзисторов 16, 20, 21 и 26, 30, 31 - с их вторыми выходами

Units 1-0, ... 1-6 for comparison of digits have two variants of circuitry and design, shown in Figs. 5, 6 and 7, 8 respectively. In each embodiment, the block comprises first to fifth MOS transistors 12-16 in FIG. 5 and 22-26 in FIG. 6 are enriched type with p-type induced channels and first through fifth MOS transistors 17-21 and 27-31 of enriched type with induced n-type channels, respectively. The sources of the p-MOS transistors 12 - 15 and 22 - 25 are connected to the + U _P bus of the positive supply voltage, and the sources of the n-MOS transistors 17, 19-21 and 27, 29 - 31 are connected to the zero potential bus. The gates of the pairs of MOS transistors 12 and 17, 22 and 27 are connected and are the first inputs and blocks of both options, the drains of the p-MOS transistors 15 and 25, respectively, are connected to the sources of the p-MOS transistors 16 and 26, and the sources of the n-MOS transistors 18 and 28 - with drains of n-MOS transistors 19 and 29. Drains of MOS transistors 13, 14, 18 and 23, 24, 28 are respectively connected to the first outputs

blocks of the first and second embodiments, and the drains of the MOS transistors 16, 20, 21 and 26, 30, 31 - with their second outputs

In the first embodiment of the bit comparison unit, see FIG. 5, the gates of the MOS transistors 13, 15, 19 and 20 are connected and are the second input v of the block, and the gates of the MOS transistors 14, 16, 18 and 21 are connected to the drains of the MOS transistors 12 and 17.

In the second embodiment of the bit comparison unit, see FIG. 6, the gates of the MOS transistors 23, 25, 29 and 30 are connected to the drains of the MOS transistors 22 and 27, and the gates of the MOS transistors 24, 26, 28 and 31 are connected and are the second input v of the block.

CMOS elements form units of logical functions performed by connecting the outputs to the positive supply voltage bus using the channels of p-type MOS transistors that arise in them when there is a low voltage on the gates, and zeros by connecting the outputs to the zero potential bus through open channels n- MOS transistors in the presence of high voltage levels on their gates. The conductivity functions of series and parallel connections of MOS transistors correspond to the conjunctions and disjunctions of the conductivity functions of transistors, which for p-channel are expressed by inversion, and for n-channel - by repeating logic levels at the gates.

In the first embodiment of the unit for comparing the discharges, MOS transistors 12 and 17 form inverter 5, MOS transistors 13, 14 and 18, 19 - element 6 2I-NOT, and MOS transistors 15, 16 and 20, 21 - element 7 2 OR- NOT.

In the second embodiment of the unit for comparing the discharges, the inverter 5 is made up of MOS transistors 22 and 27, element 6 2I-NOT MOS transistors 23, 24 and 28, 29, and element 7 2 OR-NOT - MOS transistors 25, 26 and 30, 31.

блока. N-область истоков-стоков в первой области 39 n-МОП-структур между полосками 43, 44 затворов и крайняя со стороны полоски 43 затворов р-область истока-стока в области 40 р-МОП-структур соединены со вторым выходом u v блока.In the design of the first embodiment of the unit for comparing the digits (Fig. 7), the first regions 38 and 39 of the p- and n-MOS structures are located at the edges of the unit, and the second regions 40 and 41 are adjacent to each other. P-region of sources-drains between the first and second strips 42 and 43 gates in the region of 38 p-MOS structures and the outermost gates from the side of the third strip 44 gates of the p-region and drains-drains of regions 38 and 40 of p-MOS structures are connected to the bus + U _P positive supply voltage. The N-region of the source-drain between the strips 42 and 43 of the gates in the region 39 of the n-MOS structures and the outermost from the side of the strip 44 of the gates of the n-region of the sources-drains in the regions 39 and 41 of the n-MOS structures are connected to the zero potential line. The source-drain P-region in the region 38 of the p-MOS structures between the gate strips 43, 44 and the n-source-drain region on the side of the gate strip 43 in the region 41 of the n-MOS structures are connected to the first output

block. The N-region of the sources-drain in the first region 39 of the n-MOS structures between the strips 43, 44 of the gates and the p-region of the source-drain in the region 40 of the p-MOS structures, which is extreme from the side of the strip 43 of the gates, are connected to the second output of the uv block.

At the intersections of the strips 42, 43 and 44 of the gates of the regions 38 and 39 of the p- and n-MOS structures, respectively, there are the channel regions of the p-MOS transistors 12, 14, 13 and n-MOS transistors 17, 21, 20, and in the places where the strips 43 and 44 cross the gates of the regions 40 and 41 of the p- and n-MOS structures 40 and 41 - the channel regions of the p-MOS transistors 16, 15 and n-MOS transistors 18, 19.

блока. N-область истоков-стоков в области 48 n-МОП-структур между полосками 50, 51 затворов и крайняя со стороны полоски 51 затворов р-область истока-стока в области 45 р-МОП-структур соединены со вторым выходом

блока.In the construction of the second embodiment of the unit for comparing the digits (Fig. 8), the first regions 45 and 46 of the p- and n-MOS structures are adjacent to each other, and the second regions 47 and 48 of the p and n-MOS structures are located at the edges of the block. P-area of sources-drains between the first and second strips 49 and 50 gates in the area of 45 p-MOS-structures and the extreme p-area of sources-drains in the area of 47 p-MOS structures are connected to the bus + U _P positive supply voltage. The N-region of the source-drain between the strips 49 and 50 of the gates in the region 46 of the n-MOS structures and the extreme n-regions of the sources-drains in the region 48 of the n-MOS structures are connected to the zero potential line. The P-region of the sources-drains in the region 47 of the p-MOS structures between the gate strips 50, 51 and the n-region of the source-drain in the region 46 of the n-MOS structures, which is extreme from the side of the strip 51 of the gates, are connected to the first output

block. The N-region of sources-drains in the region 48 of n-MOS structures between the strips 50, 51 of the gates and the p-region of the source-drain in the region 45 of the p-MOS structures, which is extreme from the side of the strip 51 of the gates, are connected to the second output

block.

The intersection of the gates 45 and 46 by strips 49, 50 and 51 of the p- and n-MOS structures, respectively, form the channel regions of the p-MOS transistors 22, 25, 26 and n-MOS transistors 27, 29, 28, and the intersections by the stripes 50 and 51 gates of the regions 47 and 48 of the p- and n-MOS-structures 45 and 46 - the region of the channels of the p-MOS transistors 23, 24 and n-MOS transistors 30, 31.

The described constructive implementation of the discharge comparison units in two versions makes it possible to increase the density of their placement on the crystal surface when the device is integrated. FIG. 12 shows a fragment of the arrangement of an array of such blocks, which provides for a mirror-symmetric arrangement of pairs of blocks of both embodiments, which makes it possible to minimize the placement step of MOSFET structures due to the two-row arrangement of the regions of the MOS structures, reducing the area of insulating regions and aligning the source regions connected to the power buses MOS structures.

Obviously, the number of bit comparison units made according to the first and second options should be equal for an even digit capacity N of the compared numbers or differ by one for an odd N.

а нулевые значения - выражению

см. фиг. 9 содержит первые, вторые, третьи МОП-транзисторы 32, 33, 34 и 35, 36, 37 обогащенного типа с индуцированными каналами р- и n-типов проводимости, затворы которых попарно соединены и соответственно являются входами сигналов X, Y и Z. Истоки р- и n-МОП-транзисторов 32, 34 и 35, 37 соответственно подключены к шине +U_П положительного напряжения питания и к шине нулевого потенциала. Стоки р- и n-МОП-транзисторов 32 и 37 соответственно соединены с истоками р- и n-МОП-транзисторов 33 и 36, стоки которых и стоки МОП-транзисторов 34 и 35 соединены с выходом элемента.Each element 8 and 9 performing a function whose single values correspond to the expression

and zero values - to the expression

see fig. 9 contains the first, second, third MOS transistors 32, 33, 34 and 35, 36, 37 of the enriched type with induced channels of p- and n-types of conductivity, the gates of which are connected in pairs and, respectively, are the inputs of signals X, Y and Z. Sources p- and n-MOS transistors 32, 34 and 35, 37, respectively, are connected to the + U _P bus of the positive supply voltage and to the zero potential bus. The drains of the p- and n-MOS transistors 32 and 37 are respectively connected to the sources of the p- and n-MOS transistors 33 and 36, the drains of which and the drains of the MOS transistors 34 and 35 are connected to the output of the element.

с неполностью определенной функцией оправдано тем, что у каждого такого элемента в данном устройстве логические функции сигналов, поступающих на входы X и Z связаны отношением включения F_X ⊃ F_Z, то есть F_X включает F_Z, так как все единичные значения функции F_Z на определенном наборе значений переменных соответствуют единичным значениям функции F_X, которая имеем еще и другие единичные значения.Applying elements

with an incompletely defined function is justified by the fact that for each such element in a given device the logical functions of the signals arriving at the inputs X and Z are connected by the inclusion relation F _X ⊃ F _Z , that is, F _X includes F _Z , since all unit values of the function F _Z on a certain set of values of the variables correspond to the unit values of the function F _X , which we also have other unit values.

во всех блоках объединения результатов частичных сравнений на входы X и Z соответственно поступают сигнал признака исключительного превосходства части одного числа над аналогичной частью другого, например, А_1-0>В_1-0 и сигнал признака того же превосходства, дополненного признаком равенства этих же частей, - А_1-0≥В_1-0. Очевидно, что признак вида А_1-0>В_1-0 выполняется только при выполнении признака A_1-0≥В_1-0, все случаи невыполнения которого, совпадают со случаями невыполнения признака А_1-0>B_1-0, а, еще, признак А_1-0≥В_1-0 не может быть ложным, когда истинен признак А_1-0>В_1-0. Это выражается следующими логическими формулами.So, for elements 8 and 9

in all blocks for combining the results of partial comparisons, the inputs X and Z respectively receive a signal of a sign of the exceptional superiority of a part of one number over a similar part of another, for example, A _1-0 > B _1-0 and a signal of a sign of the same superiority supplemented by a sign of equality of the same parts , - А _1-0 ≥В _1-0 . Obviously, a feature of the form A _1-0 > B _1-0 is fulfilled only when the feature A _1-0 ≥B _{1-0 is} fulfilled, all cases of non-fulfillment of which coincide with the cases of non-fulfillment of the feature A _1-0 > B _1-0 , and , yet, the sign A _1-0 ≥B _1-0 cannot be false when the sign A _1-0 > B _1-0 is true. This is expressed by the following logical formulas.

The logical relationship of signals X and Z expressed by formulas (10) and (11) made it possible to simplify the connections of MOS transistors in the circuit of elements 8 and 9, during the synthesis of which the following formulas were converted.

The extreme logical expressions on the left and right in formula (13) describe the connections, respectively, of n- and p-MOS transistors in elements 8 and 9, and formula (12) proves that p- and n-MOS transistors controlled by different signals are directly those connected between the output of the element and the power rails cannot have open channels at the same time. The high signal level X, which turns on the n-MOSFET 35, is never combined with the low turn-on level of the p-MOS transistor 34, the signal level Z.

а нулевые значения - выражению

конструктивно выполнен (Фиг. 10) в виде двух смежных продольными сторонами областей 52 и 53 МОП-структур р- и n-типов проводимости, пересеченных поперек тремя общими полосками 54, 55 и 56 затворов, разделяющими области 52 и 53 на области истоков-стоков соответствующих типов проводимости. Полоски 54, 55, 56 затворов по порядку соединены со входами сигналов X, Y, Z. Крайние р- и n-области истоков-стоков соответственно подключены к шине +U_П положительного напряжения питания и к шине нулевого потенциала, а области истоков-стоков р-типа между полосками 55, 56 затворов и n-типа между полосками 54, 55 затворов соединены с выходом элемента.Each element that performs a function whose single values correspond to the expression

and zero values - to the expression

structurally made (Fig. 10) in the form of two adjacent longitudinal sides of the regions 52 and 53 MOS structures of p- and n-types of conductivity, crossed across by three common strips 54, 55 and 56 of the gates, separating the regions 52 and 53 into the source-drain region corresponding types of conductivity. Strips 54, 55, 56 of the gates are connected in order to the inputs of the signals X, Y, Z. The extreme p- and n-regions of the sources-drains are respectively connected to the + U _P bus of the positive supply voltage and to the zero potential bus, and the regions of the sources-drains p-type between the strips 55, 56 of the gates and n-type between the strips 54, 55 of the gates are connected to the outlet of the element.

позволила выполнить связи стоков и истоков их р- и n-МОП-транзисторов 32, 33 и 37, 36 простым совмещением, не требующим контактов и проводников. Расположение подключенных к шинам питания истоков МОП-транзисторов 32, 34 и 35, 37 по краям позволяет совмещать их у соседних элементов в общей конструкции устройства, как показано на фиг. 11.The intersection of the gate regions 52 and 53 by strips 54, 55, 56 of the p- and n-MOS structures, respectively, form the channel regions of the p-MOS transistors 32, 33, 34 and n-MOS transistors 35, 36, 37. Simplified circuit of elements 8 and 9

made it possible to perform connections of drains and sources of their p- and n-MOS transistors 32, 33 and 37, 36 by simple alignment, which does not require contacts and conductors. The arrangement of the sources of the MOS transistors 32, 34 and 35, 37 connected to the power lines at the edges allows them to be combined at adjacent elements in the overall structure of the device, as shown in FIG. eleven.

последовательных элементов. Устройство формирует сигналы трех признаков сравнения чисел А и В по логическим формулам:Thus, the comparator of two N-bit binary numbers performs its functions, having in its composition logical elements connected in a tree-like chain, the signal propagation paths from inputs to outputs of which contain no more than

consecutive elements. The device generates signals of three signs of comparison of numbers A and B according to logical formulas:

The proposed circuit and design implementation of the device elements will increase the density of its packaging in an integrated design.

Claims (3)

1. Comparator of binary numbers containing blocks of comparison of digits in an amount equal to the number of digits N, each block of comparison of digits consists of the first element and the second, third elements, the first inputs of which are connected to the output of the first element, and the outputs, respectively, are the first, second outputs of the block , the input of the first element and the second input of the second element, respectively, are the first and second inputs of the block, the third element is a logical element 2 OR NOT, blocks for combining the results of partial comparisons, each of which has from the first to the fourth inputs and consists of the first and second elements, outputs which, respectively, are the second and first outputs of the block, the generator of the signal of the sign of equality of numbers on the logical element 2 OR-NOT, the output of which is the output of the device for the signal of equality of the compared numbers - A = B, the number of blocks for combining the results of partial comparisons is equal to N - 1, they form a tree-like chain consisting of several cascades, the number of which K is equal to the rounded to the nearest larger integer value of the logarithm base two from N, that is

, in the blocks for combining the results of partial comparisons that make up the first stage, the first, second and third, fourth inputs are respectively connected to the first, second outputs of the blocks for comparing the digits of even and odd numbers, following in ascending order from 0 to N - 1, if N is even , or up to N - 2, if N is odd, in each next cascade the first, second and third, fourth inputs of the blocks for combining the results of partial comparisons are connected to the first, second outputs of similar blocks of the previous cascade in ascending order of the numbers of the corresponding digits of the compared numbers, if in the previous stages there are no connections between the outputs of the digit comparison unit and the unit for combining the results of partial comparisons or two blocks for combining the results of partial comparisons, the first and second outputs of these blocks in ascending order of the numbers of the corresponding digits of the compared numbers are connected to the first, second and third, fourth inputs of the latter in order results combining unit of partial comparisons of this cascade, the second output of the unit for combining the results of partial comparisons of the last K-th cascade is the output of the device for the signal when the second number is exceeded first - A> B and is connected to the second input of the element 2OR-NOT of the signal generator of the sign of equality of numbers, characterized in that the first and second elements of each block for comparing the digits, respectively, are an inverter and a logical element 2 AND-NOT, the second input of which is connected to the second input of the element 2OR-NOT, in each block for combining the results of partial comparisons, both elements perform the logical function of three variables X, Y, Z, whose single values correspond to the expression

, and zero values -

, inputs of variables Y of the first and second elements

respectively, they are the first and second inputs of the block, the inputs of the variables Z and X of these elements are respectively connected and are the third and fourth inputs of the block, the signal generator of the equality sign additionally contains an inverter, the input of which is connected to the first output of the unit for combining the results of partial comparisons of the last K-th stage , and the output is to the first input of the element 2OR-NOT and is the output of the device for the signal when the first number is exceeded by the second - A <B, the inputs of each bit comparison unit are connected to a pair of bit inputs a _i and b _{i of the} compared numbers A and B of the corresponding order i = 0, 1, ... N - 1, and if the distribution chain of the output signals of this block to the device outputs contains an even number of series-connected blocks for combining the results of partial comparisons, the first and second inputs of the block are respectively connected to the inputs a _i and b _i , and if odd -, then to the inputs b _i and a _i . 2. Comparator of binary numbers according to claim 1, characterized in that the bit comparison blocks have two variants of execution, in each of them the block contains from the first to the fifth MOS transistors of the enriched type with induced p-type channels and from the first to the fifth MOS- enriched type transistors with induced n-type channels, the sources from the first to the fourth p-MOS transistors are connected to the positive supply voltage bus, and the sources of the first and from the third to the fifth n-MOS transistors are connected to the zero potential bus, the gates of the first p- and n-MOS transistors are connected and are the first input of the block, the drain of the fourth p-MOS transistor is connected to the source of the fifth p-MOS transistor, and the source of the second n-MOS transistor is connected to the drain of the third n-MOS transistor, the drains of the second , the third p-MOS and second n-MOS transistors are connected to the first output of the block, the drains of the fifth p-MOS and fourth, fifth n-MOS transistors are connected to the second output of the block, in the first embodiment of the block the gates of the second, fourth p -MOS and third, fourth n-MOS transistors are connected and are the second input of the block, and the gates of the third, fifth p-MOS and second, fifth n-MOS transistors are connected and connected to the drains of the first p- and n-MOS- transistors, in the second embodiment of the block, the gates of the second, fourth p-MOS- and third, fourth n-MOS transistors are connected and connected to the drains of the first p- and n-MOS transistors, and the gates of the third, fifth p-MOS- and second , the fifth n-MOS transistors are connected and are the second input of the block, each element performing a function, the unit values of which correspond to the expression

, and zero values - to the expression

, contains the first, second and third enriched type MOS transistors with induced p- and n-type channels, the gates of which are connected in pairs and, respectively, are the inputs of the X, Y and Z signals, the sources of the first and third p- and n-MOS transistors respectively connected to the buses of the positive supply voltage and zero potential, the drains of the first p-MOS and third n-MOS transistors, respectively, are connected to the sources of the second p- and n-MOS transistors, the drains of which and the drains of the third p-MOS and the first n - MOS transistors are connected to the output of the element. 3. Comparator of binary numbers according to claim 2, characterized in that each block for comparing the digits of both variants is structurally made in the form of the first and second regions of the p-type MOS structures adjacent to the longitudinal sides and the adjacent longitudinal sides of also adjacent first and second regions of the MOS -structures of the n-type, across the first regions of the p- and n-MOS structures passes the first strip of gates, connected to the first input of the block, across all four regions there is a second strip of gates connected to the outermost ones from the side of the first strip of gates p- and n- regions of the sources-drains of the first regions of the p- and n-MOS structures, and the third strip of gates connected to the second input of the block, in the parts of the first regions of the p- and n-MOS structures separated by the first strip of gates and in the second regions of the p- and n -MOS structures, the second and third strips of gates are separated by three regions of the sources-drains of the corresponding types, in the first embodiment of the discharge comparison unit, the first regions of p- and n-MOS structures are located n about the edges of the block, and the second regions of the p- and n-MOS structures are adjacent to each other, the p-region of sources-drains between the first and second strips of gates of the first region of p-MOS structures and the outermost p-region of the sources from the side of the third strip of gates - the drains of both regions of p-MOS structures are connected to the bus of positive supply voltage, the n-source-drain region between the first and second strips of gates of the first region of n-MOS structures and the outermost gates from the side of the third strip of gates of the n-region of the sources-drains of both regions n-MOS structures are connected to the zero potential bus, the p-region of the sources-drains of the first region of the p-MOS structures between the second and third strips of gates and the n-region of the source-drain of the second region of n-MOS structures, extreme from the side of the second strip of gates are connected to the first output of the block, the n-region of the sources-drains of the first region of n-MOS structures between the second and third strips of gates and the p-region of the source-drain of the second region of the p-MOS structures from the side of the second strip of gates are connected to the the second output of the unit, in the second embodiment of the discharge comparison unit, the first regions of the p- and n-MOS structures are adjacent to each other, and the second regions of the p- and n-MOS structures are located at the edges of the block, the p-region of sources-drains between the first and the second strips of gates of the first region of p-MOS structures and the extreme p-regions of sources-drains of the second region of p-MOS structures are connected to the bus of positive supply voltage, the n-region of sources-drains between the first and second strips of gates of the first region of n-MOS structures -structures and the extreme n-regions of the sources-drains of the second region of n-MOS structures are connected to the zero potential bus, the p-region of the sources-drains of the second region of the p-MOS structures between the second and third strips of gates and the extreme from the side of the third strip of gates n - the source-drain area of the first region of n-MOS structures are connected to the first output of the block, the n-source-drain area of the second region of n-MOS structures between the second and third strips of gates and the p-region of source, which is extreme from the side of the third strip of gates oka-drain of the first region of p-MOS structures are connected to the second output of the block, the number of comparison blocks of the digits made according to the first and second options differ by no more than one, each element performing a function, the unit values of which correspond to the expression

, and zero values - to the expression

, structurally made in the form of two adjacent longitudinal sides of the regions of MOS structures of p- and n-types of conductivity, crossed across by three common strips of gates, dividing the MOS structures into regions of sources-drains of the corresponding types of conductivity, the first-third strips of gates are connected in order to signal inputs X, Y and Z, the extreme p- and n-areas and drains-drains are respectively connected to the buses of the positive supply voltage and zero potential, and the areas of the p-type sources-drains between the second and third strips of gates and n-type between the first and the second by strips of closures are connected to the outlet of the element.

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