RU2300131C1 - Binary number comparator - Google Patents

Abstract

FIELD: computer engineering, possible use for building automatic devices, functional units of control systems, etc.

SUBSTANCE: binary number comparator contains OR logical element, OR-NOT logical element and two XOR logical elements, three AND-NOT logical elements. First input and output of i

XOR logical element are connected respectively to first and second inputs of i AND-NOT logical element, connected by second input to i input of OR-NOT logical element. First, second inputs and output of OR logical element are connected respectively to output of second, by second input of first logical element AND-NOT and second input of third logical element AND-NOT, connected by first input and output respectively to output of first logical element AND-NOT and to first output of binary number comparator, second output and i, (i+2) inputs of which are connected respectively to output of logical element OR-NOT and first, second inputs of i XOR logical element.

EFFECT: decreased hardware resource costs with preserved functional capabilities and speed of operation.

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Description

The invention relates to computer technology and can be used to build automation, functional units of control systems, etc.

Comparators of binary numbers are known (see, for example, the third from the bottom of the figure in table 3.5 on page 103 in the book Handbook of Digital Computing. Malinovsky B.N., Alexandrov V.Ya., Boyun V.P. and others. / Under the editorship of B.N. Malinovsky, Kiev: Technique, 1974), which form the sign of the relation x ₂ > x ₁ , where x ₁ , x ₂ ∈ {0,1} are single-bit binary numbers given by binary signals.

The reason that impedes the achievement of the technical result indicated below when using known binary number comparators is limited functionality, due to the fact that it is not allowed to compare two-digit binary numbers given by binary signals.

The closest device of the same purpose to the claimed invention in terms of features is the binary number comparator adopted for the prototype (Fig. 8.32a on p. 500 in the book of B. Shevkoplyas Microprocessor structures. Engineering solutions: Reference book. M: Radio and communications, 1990), which contains logical elements and forms the signs of the relations A> B, A = B, where A = a ₁ a ₀ and B = b ₁ b ₀ are two-digit binary numbers given by binary signals a ₀ , a ₁ , b _0, b ₁ ∈ {0,1}, with the maximum signal propagation delay time in the prior art was determined by the expression τ = 4τ _E, where T _e - time delay logic element.

The reason that impedes the achievement of the technical result indicated below when using the prototype includes high hardware costs.

The technical result of the invention is to reduce hardware costs while maintaining the functionality and speed of the prototype.

логического элемента ИСКЛЮЧАЮЩЕЕ ИЛИ соединены соответственно с первым и вторым входами i-го логического элемента И-НЕ, подключенного вторым входом к i-му входу логического элемента ИЛИ-НЕ, первый, второй входы и выход логического элемента ИЛИ соединены соответственно с выходом второго, вторым входом первого логических элементов И-НЕ и вторым входом третьего логического элемента И-НЕ, подключенного первым входом и выходом соответственно к выходу первого логического элемента И-НЕ и первому выходу компаратора двоичных чисел, второй выход и i-й, (i+2)-й входы которого соединены соответственно с выходом логического элемента ИЛИ-НЕ и первым, вторым входами i-го логического элемента ИСКЛЮЧАЮЩЕЕ ИЛИ.The specified technical result during the implementation of the invention is achieved by the fact that in the comparator of binary numbers containing the logical element OR, the logical element OR-NOT and two logical elements EXCLUSIVE OR, the peculiarity lies in the fact that it additionally introduced three logical elements AND-NOT, first entry and exit of i

EXCLUSIVE OR gates are connected respectively to the first and second inputs of the i-th AND gate NOT connected to the i-th input of the OR gate, the first, second inputs and outputs of the OR gate are connected respectively to the output of the second, second the input of the first logical elements AND-NOT and the second input of the third logical element AND-NOT connected by the first input and output, respectively, to the output of the first logical element AND-NOT and the first output of the binary number comparator, the second output i-th, (i + 2) -th inputs of which are respectively connected to the output of the NOR and the first, second, i-th inputs of NAND gate XOR.

The drawing shows a diagram of the proposed comparator of binary numbers.

) соединены соответственно с первым и вторым входами элемента 2_i, подключенного вторым входом к i-му входу элемента 4, первый, второй входы и выход элемента 3 соединены соответственно с выходом элемента 2₂, вторым входом элемента 2₁ и вторым входом элемента 2₃, подключенного первым входом и выходом соответственно к выходу элемента 2₁ и первому выходу компаратора двоичных чисел, второй выход и i-й, (i+2)-й входы которого соединены соответственно с выходом элемента 4 и первым, вторым входами элемента 1_i.The binary numbers comparator contains EXCLUSIVE OR 1 ₁ , 1 ₂ logic elements, AND logical elements - NOT 2 ₁ , 2 ₂ , 2 ₃ , logical element OR 3 and logical element OR - NOT 4, with the first input and output of element 1 _i (

) are connected respectively to the first and second inputs of element 2 _i connected by the second input to the i-th input of element 4, the first, second inputs and output of element 3 are connected respectively to the output of element 2 ₂ , the second input of element 2 ₁ and the second input of element 2 ₃ connected by the first input and output, respectively, to the output of element 2 ₁ and the first output of the binary number comparator, the second output and the ith (i + 2) -th inputs of which are connected respectively to the output of element 4 and the first, second inputs of element 1 _i .

The work of the proposed comparator of binary numbers is as follows. Arbitrary binary signals a ₁ , a ₀ ∈ {0,1} and b ₁ , b ₀ ∈ {0,1} are supplied to its first, second, third, fourth inputs, respectively, which specify two-digit binary numbers A = a _{1 to} be compared a ₀ and B = b ₁ b ₀ (a ₁ , b ₁ and a ₀ , b ₀ determine the values of the higher and lower digits, respectively). Then the signals at the first, second outputs of the proposed comparator will be determined by the expressions

The table below shows the values of the functions realized by expressions (1) on all possible sets of values of their arguments.

BUT B Q _{A> B} Q _{A = B} a ₁ a ₀ b ₁ b ₀ 0 0 0 0 0 one 0 0 0 one 0 0 0 0 one 0 0 0 0 0 one one 0 0 0 one 0 0 one 0 0 one 0 one 0 one 0 one one 0 0 0 0 one one one 0 0 one 0 0 0 one 0 one 0 0 one one 0 one 0 one 0 0 one one 0 one one 0 0 one one 0 0 one 0 one one 0 one one 0 one one one 0 one 0 one one one one 0 one

Given the table, we have Q _{A> B} = 1 if A> B, Q _{A = B} = 1 if _{A = B.} Moreover, the proposed comparator contains seven logic elements, and the maximum delay time of the propagation of a signal in it is determined by the expression τ = 4τ _E , where τ _E is the delay time of the logical element. Note that the prototype includes eleven logical elements.

The above information allows us to conclude that the proposed binary number comparator forms the signs of the relations A> B, A = B, where A = a ₁ a ₀ and B = b ₁ b ₀ are two-bit binary numbers defined by binary signals a ₀ , a ₁ , b ₀ , b ₁ ∈ {0,1}, has the speed of the prototype and has lower hardware costs compared to it.

Claims (1)

A binary number comparator containing an OR logical element, an OR-NOT logical element and two EXCLUSIVE OR logical elements, characterized in that it additionally contains three AND-NOT logical elements, the first input and output of the ith

EXCLUSIVE OR gates are connected respectively to the first and second inputs of the i-th AND gate NOT connected to the i-th input of the OR gate, the first, second inputs and outputs of the OR gate are connected respectively to the output of the second, second the input of the first logical elements AND-NOT and the second input of the third logical element AND-NOT connected by the first input and output, respectively, to the output of the first logical element AND-NOT and the first output of the binary number comparator, the second output i-th, (i + 2) -th inputs of which are respectively connected to the output of the NOR and the first, second, i-th inputs of NAND gate XOR.