RU2248663C1 - Flip-flop device - Google Patents

Abstract

FIELD: pulse engineering.

SUBSTANCE: proposed flip-flop device has RS flip-flop 1, EXCLUSIVE OR gates 2,3, NOR gates 4, 5, inverters 6, 7, 8, diodes 15, 16, resistors 9 through 12, capacitors 13, 14, memory items 17, 18 built around magnetic cores with rectangular hysteresis loop and single coil, input bus 19, and common bus 20. Combining write and read coils of memory items 17 and 18 makes it possible to increase coil number of write and read coils by 1.5 times, in each of half-coils of memory items 17 and 18, which reduces magnetizing current through cores of memory items 17 and 18 by approximately 1.5 times due to enhancing ratings of limiting resistors 11 and 12.

EFFECT: reduced input current from power supply.

1 cl, 1 dwg

Description

The invention relates to a pulse technique and can be used in computing devices and control systems.

A trigger device is known (see USSR author's certificate No. 1753919 of 05.10.90, MKI N 03 K 3/037 “Trigger device”, authors LB Egorov, GI Shishkin, publ. 10.09.97, bull. No. 25), containing the first and second memory elements on magnetic cores, the outputs of the reading windings of which are connected to a common bus, the inputs of the recording windings are connected respectively to the direct and inverse outputs of the exclusive-OR element, the first and second inputs of which are connected to the input bus and RS output -trigger, respectively, the installation and reset inputs of which are connected through respectively, the first and second resistors with inputs of the reading windings of the first and second memory elements, respectively. The first input of the control unit is connected to the input bus, the second and third inputs of the control unit are connected respectively to the direct and inverse outputs of the Exclusive OR element, and the first and second outputs of the control unit, respectively, through the third and fourth resistors are connected to the outputs of the recording windings, respectively, of the first and second elements of memory.

The disadvantage of this trigger device is the relatively large current consumption from the power source.

Known trigger device (see RF patent No. 2106742 from 08.16.95, MKI N 03 K 3/286 "Trigger device", authors E.I. Ryzhakov, G.I. Shishkin, publ. 10.03.98, bull. No. 7 ), which is the closest in technical essence to the claimed object and is selected as a prototype, containing an RS-trigger, the installation and reset inputs of which are connected to the first terminals of the first and second resistors, respectively, and through the first and second capacitors, respectively, with a common bus, and direct and inverse outputs are connected to the first inputs of the first and second, respectively of the “Exclusive OR” elements, the second inputs of which are connected to the input bus of the trigger device, and the outputs are connected to the inputs of the recording windings of the first and second memory elements on magnetic cores, the inputs of the reading windings of which are connected to a common bus, the first and second elements are NAND , the third and fourth XOR elements, the third, fourth, fifth and sixth resistors. The RS-trigger is made on AND-NOT elements. The outputs of the first and second exclusive-OR elements are connected to the first inputs of the third and fourth exclusive-OR elements, respectively, whose outputs are connected through the third and fourth resistors to the outputs of the write windings of the first and second memory elements, respectively, whose read-through outputs are respectively through the fifth and the sixth resistors are connected to the first inputs of the first and second AND-NOT elements respectively, the outputs of which are connected to the second terminals of the second and first cuts, respectively tors and to the second inputs, respectively, third and fourth elements of the "exclusive OR". The second inputs of the first and second elements AND NOT combined and connected to the input bus of the trigger device.

The disadvantage of the prototype is the relatively large current consumption from the power source.

The problem solved by the claimed invention is to reduce the current consumption from the power source.

The specified technical result is achieved by the fact that in the trigger device containing the RS trigger, the first and second exclusive-OR elements, the first inputs of which are combined and connected to the input bus, the first and second memory elements on magnetic cores with a rectangular hysteresis loop (PPG) , the first and second resistors, the first conclusions of which are connected to the common bus through the first and second capacitors, respectively, the third and fourth resistors, the new one is the introduction of the first and second elements OR NOT, the first, second and third about inverters, first and second diodes, the first and second memory elements on magnetic cores with BCPs contain one winding each, the midpoints of which are connected to the cathodes of the first and second diodes, respectively, and respectively through the third and fourth resistors are connected to the outputs of the first and second inverters, respectively the inputs of which are connected to the inputs of the windings of the first and second memory elements, respectively, and respectively to the direct and inverse outputs of the RS-flip-flop, the reset and installation inputs of which are connected to the outputs of the of the second and exclusive XOR elements, respectively, whose second inputs are connected to the first terminals of the first and second resistors, respectively, the second terminals of which are connected to the outputs of the first and second elements OR NOT, respectively, whose first inputs are connected to the outputs of the windings of the second and first memory elements respectively, and the second inputs are combined and connected to the output of the third inverter, the input of which is connected to the input bus, the RS-trigger is made on the elements of OR-NOT.

The specified set of essential features allows to reduce the current consumption of the trigger device from the power source due to the possibility of reducing the bias current of the core by increasing the number of turns in the recording windings of the cores.

The drawing shows a circuit diagram of a trigger device. The trigger device contains RS-trigger 1, elements 2 and 3 "exclusive OR", elements 4 and 5 OR-NOT, inverters 6, 7 and 8, resistors 9, 10, 11 and 12, capacitors 13 and 14, diodes 15 and 16 , memory elements 17 and 18 on magnetic cores with BCP with one winding having a tap from the midpoint, an input bus 19 and a common bus 20. The first inputs of the exclusive-OR elements 2 and 3 are combined and connected to the input bus 19 and to the inverter input 8. The second input of the exclusive-OR element 2 through a capacitor 13 is connected to a common bus 20 and through a resistor 9 to the output of the element 4 OR NOT, the first input to which is connected to the output of the winding of the memory element 18. The second input of the exclusive-OR element 3 is connected via a capacitor 14 to a common bus 20 and through a resistor 10 to the output of the OR-NOT element 5, the first input of which is connected to the end of the winding of the memory element 17. The second inputs of elements 4 and 5 OR are NOT connected and connected to the output of the inverter 8. The outputs of elements 2 and 3 are connected respectively to the reset and installation inputs of the RS-trigger 1. The direct output of the RS-trigger 1 is connected to the input of the inverter 6, with the anode of the diode 15 and with the input of the winding of the memory element 17. The inverse output of the RS-trigger 1 is connected to the input of the inverter 7, with the anode of the diode 16 and with the input of the winding of the memory element 18. The output of the inverter 6 through the resistor 11 is connected to the cathode of the diode 15 and with the midpoint of the winding of the memory element 17. The output of the inverter 7 through a resistor 12 is connected to the cathode of the diode 12 and to the midpoint of the winding of the memory element 18. The RS-trigger 1 contains elements 21 and 22 OR NOT, with the first inputs of the elements 21 and 22 being respectively the reset and installation inputs of the RS-trigger 1, the outputs of the elements 21 and 22 are the direct and inverse outputs of the RS-trigger 1, respectively, the second inputs elements 21 and 22 are connected respectively to the outputs of elements 22 and 21.

) - сигнал "лог.1", на выходах инверторов 6 и 7 - сигналы "лог.1" и "лог.0" соответственно. Направление тока, протекающего через обмотку элемента 17 памяти, совпадает с направлением его намагниченности, в этом случае на выходе обмотки элемента 17 памяти возникает короткий импульс помехи положительной полярности относительно общей шины 20, связанный с непрямоугольностью петли гистерезиса сердечника. Диод 15 закрыт нулевым (в импульсе - отрицательным) напряжением, присутствующим на половине обмотки элемента 17 памяти. В отсутствие тактового сигнала на входной шине 19 присутствует сигнал "лог.1", на выходе инвертора 8 - сигнал "лог.0", поэтому указанный импульс помехи появится на выходе элемента 5 ИЛИ-НЕ, но на сигнал на входе элемента 3 "Исключающее ИЛИ" влияния не окажет, так как последний определяется напряжением на заряжающемся конденсаторе интегрирующей RC-цепи, состоящей из резистора 10 и конденсатора 14. При включении устройства, пока напряжение на конденсаторе 14 не наросло до уровня "лог.1", на выходе элемента 3 "Исключающее ИЛИ", а значит и на входе установки (S-входе) RS-триггера 1, некоторое короткое время будет присутствовать сигнал "лог.1". Это вызовет кратковременное появление сигнала "лог.0" на инверсном выходе (

) RS-триггера 1 и сигнала "лог.1" на выходе инвертора 7, ток в обмотке элемента 18 памяти изменит свое направление, на выходе обмотки элемента памяти 18 появится импульс положительной полярности, подтверждающий разреженное состояние конденсатора 13; на выходе элемента 2 "Исключающее ИЛИ" и на входе сброса (R-входе) RS-триггера 1 при этом - сигнал "лог.1", подтверждающий сигнал "лог.0" на прямом (Q) выходе RS-триггера 1. После заряда конденсатора 14 на выходе элемента 3 и на входе установки (S-входе) RS-триггера 1 установится сигнал "лог.0", на

-выходе RS-триггера 1 - сигнал "лог.1", на выходе инвертора 7 - сигнал"лог.0". В результате, после окончания переходных процессов в элементах памяти 17 и 18 направление тока, протекающего через обмотку элемента 18 памяти, также совпадает с направлением его намагниченности с той разницей, что напряжение на полуобмотке элемента 18 памяти, то есть между входом и средней точкой обмотки, шунтируется открытым диодом 16. Поэтому амплитуда импульса помехи на выходе обмотки элемента памяти 18 относительно ее входа не будет превышать значения 2 U_d, где U_d - падение напряжения на открытом диоде 16 (при равенстве числа витков в полуобмотках элементов 17 и 18 памяти, то есть при равенстве числа витков между входом и средней точкой обмотки и между средней точкой и выходом обмотки). На выходе обмотки элемента памяти 18 относительно общей шины 20 установится сигнал "лог.1", на выходе элемента 4 - сигнал "лог.0". Конденсатор 13 поддерживается в разреженном состоянии, на выходе элемента 2 и на входе сброса RS-триггера присутствует сигнал "лог.1". Таким образом, в результате переходных процессов после включения напряжения питания RS-триггер останется в нулевом состоянии.The trigger device operates as follows. When the power is turned on (power circuits of logic elements 2, 3, 4, 5, 6, 7, 8, 21, 22 are not shown in the drawing for simplicity), the trigger device will be set to the state corresponding to the state of the memory elements 17, 18 that they acquired in previous work cycle. Consider the case when the memory elements 17 and 18 were magnetized to the state “log.0”, which corresponds to the direction of current flow in the winding of the memory element 17 from the midpoint to its input, and in the winding of the memory element 18 from the input to the midpoint (inputs windings in the drawing are indicated by the sign (*)). If, after turning on the power, the RS-flip-flop is set to zero, at which its direct output (Q) is the signal “log.0”, at its inverse output (

) - signal "log.1", at the outputs of inverters 6 and 7 - signals "log.1" and "log.0", respectively. The direction of the current flowing through the winding of the memory element 17 coincides with the direction of its magnetization, in this case, at the output of the winding of the memory element 17, a short pulse of positive polarity interference with respect to the common bus 20 occurs, associated with the non-squareness of the core hysteresis loop. The diode 15 is closed by a zero (in pulse - negative) voltage present on half the winding of the memory element 17. In the absence of a clock signal on the input bus 19 there is a signal "log.1", at the output of the inverter 8 there is a signal "log.0", therefore, the indicated interference pulse will appear at the output of element 5 OR-NOT, but on the signal at the input of element 3 "Exclusive OR "will have no effect, since the latter is determined by the voltage on the charging capacitor of the integrating RC circuit, consisting of resistor 10 and capacitor 14. When the device is turned on, until the voltage on capacitor 14 has increased to the level of" log.1 ", at the output of element 3 "Exclusive OR", and therefore at the input of the installation (S -input) of RS-flip-flop 1, a signal “log.1” will be present for some short time. This will cause the “log.0” signal to appear briefly on the inverted output (

) RS-trigger 1 and the signal "log.1" at the output of the inverter 7, the current in the winding of the memory element 18 will change its direction, a pulse of positive polarity will appear at the output of the winding of the memory element 18, confirming the rarefied state of the capacitor 13; at the output of element 2 “Exclusive OR” and at the reset input (R-input) of the RS-trigger 1, this is the signal “log.1”, confirming the signal “log.0” at the direct (Q) output of the RS-trigger 1. After the charge of the capacitor 14 at the output of element 3 and at the input of the installation (S-input) of the RS-trigger 1, the signal "log.0" is set,

-output of the RS-flip-flop 1 - signal "log.1", at the output of the inverter 7 - signal "log.0". As a result, after the end of the transient processes in the memory elements 17 and 18, the direction of the current flowing through the winding of the memory element 18 also coincides with the direction of its magnetization with the difference that the voltage at the half-winding of the memory element 18, that is, between the input and the midpoint of the winding, open shunted diode 16. Therefore, the amplitude of the pulse interference at the output winding of the memory element 18 relative to its input will not exceed 2 U _d, where U _d - the voltage drop across diode 16 open (with equal number of turns in the half-time Kah elements 17 and the memory 18, i.e. with equal number of windings between the input winding and the middle point between the midpoint and output winding). At the output of the winding of the memory element 18 relative to the common bus 20, the signal "log.1" will be established, at the output of the element 4, the signal "log.0". The capacitor 13 is maintained in a rarefied state, at the output of element 2 and at the reset input of the RS-trigger there is a signal "log.1". Thus, as a result of transient processes after turning on the supply voltage, the RS-trigger will remain in the zero state.

) RS-триггера 1. Вследствие этого, направление тока через обмотку элемента 17 памяти изменяет свое направление, совпадая с направлением намагничивания сердечника элемента 17 памяти; на выходе обмотки элемента 17 памяти возникнет короткий импульс помехи положительной полярности относительно общей шины 20, который, как было показано выше, не будет влиять на процессы в схеме, после чего на выходе обмотки элемента 17 памяти установится сигнал "лог.0". Поскольку длительность импульса, возникающего на выходе обмотки элемента 17 памяти, выбирается больше, чем постоянная времени интегрирующей цепи (резистор 10, конденсатор 14), конденсатор 14 зарядится до напряжения "лог.1", и на выходе элемента 3 и на S-входе RS-триггера 1 с задержкой установится сигнал "лог.0", на инверсном (

) выходе RS-триггера 1 установится сигнал "лог.1". На выходе обмотки элемента 18 памяти сохранится сигнал "лог.1". На этом заканчивается процесс восстановления состояния RS-триггера 1. Аналогичным образом происходит восстановление состояния RS-триггера 1 в соответствии с состояниями намагниченности сердечников элементов 17 и 18 памяти в случае, когда в элементы 17, 18 памяти в предыдущем цикле работы триггерного устройства было записано состояние "лог.1".If, after turning on the power, the RS-trigger is set to a single state, in which its direct (Q) output is the signal “log1”, currents flow in the windings of the memory elements 17 and 18, the direction of which does not coincide with the direction of the magnetization of the core elements of the memory 17 and 18 wherein the initial voltage at the output of the winding of the memory element 17, taking into account the shunt effect of the diode 15, is E-2U _d , where E is the supply voltage of the circuit, U _d is the voltage drop across the open diode 15; at the output of the winding of the memory element 18, a voltage close to the value of E. The last circumstance is explained by the fact that the resistance values of the resistors 11 and 12 are selected so that when the cores are magnetically reversed, a voltage pulse with an amplitude of ≈ E / 2 appears in the semi-windings of the memory elements. At the output of element 4, a signal "log.0" is formed, which supports the capacitor 13 in a rarefied state, at the output of element 2 and at the reset input (R) of the RS-trigger 1 - signal "log.1"; at the output of element 5, a "log.0" signal is generated, which maintains the capacitor 14 in a rarefied state. As a result, “log.1” signals appear at the outputs of elements 2 and 3 and at the R- and S-inputs of the RS-trigger 1, which leads to the appearance of “log.0” signals at both outputs (Q and

) RS-trigger 1. As a result, the direction of the current through the winding of the memory element 17 changes its direction, coinciding with the direction of magnetization of the core of the memory element 17; at the output of the winding of the memory element 17, a short pulse of positive polarity interference will occur with respect to the common bus 20, which, as shown above, will not affect the processes in the circuit, after which the signal “log.0” will be established at the output of the winding of the memory element 17. Since the duration of the pulse arising at the output of the winding of the memory element 17 is selected longer than the time constant of the integrating circuit (resistor 10, capacitor 14), the capacitor 14 is charged to the voltage of "log 1", and at the output of the element 3 and at the S-input RS -trigger 1 with a delay will set the signal "log.0", on the inverse (

) the output of the RS-trigger 1 will set the signal "log.1". At the output of the winding of the memory element 18, the signal "log.1" will be saved. This completes the process of restoring the state of the RS-trigger 1. Similarly, the state of the RS-trigger 1 is restored in accordance with the magnetization states of the cores of the memory elements 17 and 18 when the state was recorded in the memory elements 17, 18 in the previous operation cycle of the trigger device "log.1".

) RS-триггер 1, при этом диод 16 смещен в обратном направлении, на выходе обмотки элемента 18 - напряжение, близкое к значению Е. После перемагничивания сердечников элементов 17 и 18 памяти на выходе обмотки элемента 17 памяти установится напряжение, равное напряжению на прямом выходе RS-триггера 1 (≈Е), на выходе обмотки элемента 18 памяти установится напряжение, близкое к нулю. Указанные сигналы через элементы 4 и 5 не передаются, поскольку состояние последних определяется сигналом с выхода инвертора 8, поэтому в течение действия тактового импульса не изменяется и состояние RS-триггера 1. После окончания тактового сигнала на входе 19 элементы 2 и 3 переходят в режим инверторов сигналов, снимаемых с конденсаторов 13 и 14 соответственно, на выходе инвертора 8 снова появляется сигнал "лог.0". Сигналом "лог.0" с выхода обмотки элемента 18 памяти конденсатор 13 заряжается до уровня "лог.1", при этом на R-входе RS-триггера 1 кратковременно появляется сигнал "лог.1", после чего устанавливается сигнал "лог.0". Сигналом "лог.1" с выхода обмотки элемента 17 памяти подтверждается разреженное состояние конденсатора 14, на S-входе RS-триггера 1 устанавливается сигнал "лог.1". В результате, RS-триггер 1 после окончания тактового импульса останется в состоянии "лог.1", элементы 17 и 18 памяти намагничены в состояние "лог.1". Аналогичным образом происходит переключение триггерного устройства из состояния "лог.1" в состояние "лог.0".To switch the trigger device to the input bus 19, a clock signal with a level of "log.0" is supplied. At the same time, the output of inverter 8 is the signal "log.1", elements 2 and 3 of the "exclusive OR" begin to work in the repeater mode of the signals taken from the capacitors 13 and 14, respectively. Consider the process of switching a trigger device in the state “log.0”, characterized in that the RS-trigger 1 is in the state “log.0”, the capacitor 13 is sparse to the level of “log.0”, the capacitor 14 is charged to the level of “log.0” .1". With the start of switching, the signal “log.0” is confirmed at the output of element 4, the signal “log.0” is set at the output of element 5, these signals will be transmitted through repeaters on elements 2 and 3 to the R- and S-inputs of the RS-trigger 1, but the signal to the S-input is transmitted with a delay determined by the time constant of the RC circuit, composed of resistor 10 and capacitor 14, so the RS-trigger 1 will have time to switch to the state "log.1". Then, the magnetization reversal of the cores of the memory elements 17 and 18 occurs in a state opposite to that which they had in the previous clock cycle. The current from the direct output (Q) of the RS flip-flop 1 flows through the diode 15 and through the winding of the memory element 17 (from its input to the midpoint), through the resistor 11 to the output of the inverter 6, while at the output of the winding of the memory element 17, due to its bypass diode 15, the voltage is close to the value of E (E-2U _d ). The current from the output of the inverter 7 flows through the resistor 12, the winding of the memory element 18 (from the midpoint to its input) to the inverse output (

) RS-flip-flop 1, while the diode 16 is biased in the opposite direction, at the output of the winding of element 18 there is a voltage close to the value of E. After magnetization reversal of the cores of memory elements 17 and 18 at the output of the winding of memory element 17, a voltage equal to the voltage at the direct output is established RS-trigger 1 (≈Е), at the output of the winding of the memory element 18, a voltage close to zero is established. These signals are not transmitted through elements 4 and 5, since the state of the latter is determined by the signal from the output of inverter 8, so the state of the RS-trigger 1 does not change during the action of the clock pulse. After the end of the clock signal at input 19, elements 2 and 3 go into inverter mode signals removed from the capacitors 13 and 14, respectively, at the output of the inverter 8, the signal "log.0" again appears. The signal "log.0" from the output of the winding of the memory element 18, the capacitor 13 is charged to the level of "log.1", while the signal "log.1" appears briefly on the R-input of the RS-trigger 1, after which the signal "log.0" is set " The signal "log.1" from the output of the winding of the memory element 17 confirms the rarefied state of the capacitor 14, the signal "log.1" is set at the S-input of the RS-trigger 1. As a result, the RS-trigger 1 after the end of the clock pulse will remain in the state "log.1", the memory elements 17 and 18 are magnetized to the state "log.1". Similarly, the trigger device switches from the state "log.1" to the state "log.0".

=0), то на выходе обмотки элемента 17 памяти появится сигнал "лог. 1, на выходе обмотки элемента 18 памяти сохранится сигнал "лог. 1″, который присутствовал и до переключения RS-триггера помехой. С задержкой, определяемой разрядом конденсатора 14, сигнал "лог.1" появится на S-входе RS-триггера 1; на R-входе RS-триггера 1 сохранится сигнал "лог.1", который присутствовал и до переключения RS-триггера 1 помехой. На прямом (Q) выходе RS-триггера появится сигнал "лог.0", на инверсном (

) выходе сохранится сигнал "лог.0". Направление тока через обмотку элемента памяти 17 восстановится, при этом на выходе обмотки элемента 17 памяти появится сигнал "лог.0", конденсатор 14 зарядится до напряжения "лог.1", соответственно снимется сигнал "лог.1" с S-входа RS-триггера 1 и на его инверсном выходе (

) восстановится сигнал "лог.1".The restoration of the state of the trigger device, if it fails due to interference in the information storage mode, is carried out in accordance with the state of the memory elements 17 and 18, similar to how it is restored when the supply voltage is turned on. For example, if the trigger device is in the state “log.0” (at the Q-output of the RS-trigger there is a signal “log.0”, the cores of the memory elements 17 and 18 are magnetized to the state “log.0”, as shown by the arrows in the drawing) , and the interference switches the RS-trigger 1 to the state “log.1” (U _Q = l,

= 0), then at the output of the winding of the memory element 17 the signal “log. 1” will appear, at the output of the winding of the memory element 18 the signal “log. 1 ″, which was present even before switching the RS-trigger by interference. With a delay determined by the discharge of the capacitor 14, the signal "log.1" appears on the S-input of the RS-trigger 1; at the R-input of the RS-flip-flop 1, the signal "log.1" will be stored, which was present even before the RS-flip-flop 1 was switched by an interference. On the direct (Q) output of the RS-flip-flop, the signal “log.0” will appear, on the inverse (

) the output will save the signal "log.0". The direction of the current through the winding of the memory element 17 is restored, while at the output of the winding of the memory element 17 the signal "log.0" appears, the capacitor 14 is charged to the voltage "log.1", respectively, the signal "log.1" is removed from the S-input RS- trigger 1 and at its inverse output (

) the signal "log.1" will be restored.

From the description of the operation of the trigger device, it can be seen that its normal operation is ensured when the number of turns in the half-windings of the memory elements 17 and 18 is equal, while one half-winding (between the input and the middle point of the winding), by analogy with the prototype, serves as the recording winding, and both half-windings connected in series perform the role of a read winding. In the prototype circuit for its normal functioning, the read winding should contain about 2 times more turns than the write winding, therefore, in the inventive device, taking into account the combination of write and read windings, each memory element may contain one third fewer turns, or the selected core sizes, it is possible to increase by 1.5 times the number of turns in the write and read windings (in each of the half-windings of the memory elements 17 and 18), and thus reduce the magnetizing current by about 1.5 times Nia cores memory elements by increasing the resistance of limiting resistors 11 and 12. As a result, it decreases the current consumption of the trigger device from the power supply in static and dynamic modes of operation.

Thus, as follows from the description of the work, the claimed trigger device has a lower current consumption from the power source.

Tests of the laboratory layout of the trigger device confirmed the feasibility and practical value of the claimed device.

Claims (1)

A trigger device containing an RS-trigger, the first and second exclusive-OR elements, the first inputs of which are combined and connected to the input bus, the first and second magnetic memory elements with a rectangular hysteresis loop, the first, second resistors, the first conclusions of which are connected to a common bus through the first and second capacitors, respectively, the third and fourth resistors, characterized in that the first and second elements OR NOT, the first, second and third inverters, the first and second diodes, the first and second elements p memories on magnetic cores with a rectangular hysteresis loop contain one winding each, the midpoints of which are connected to the cathodes of the first and second diodes, respectively, and respectively through the third and fourth resistors are connected to the outputs of the first and second inverters, respectively, the inputs of which are connected to the inputs of the windings of the first and second elements memory, respectively, respectively, with direct and inverse outputs of the RS-flip-flop, the reset and installation inputs of which are connected to the outputs of the first and second elements OR ”, respectively, whose second inputs are connected to the first terminals of the first and second resistors, respectively, the second terminals of which are connected to the outputs of the first and second elements OR NOT, respectively, the first inputs of which are connected to the outputs of the windings of the second and first memory elements, respectively, and the second inputs combined and connected to the output of the third inverter, the input of which is connected to the input bus, the RS-trigger is made on the elements OR-NOT.