RU2230427C2 - Nonvolatile memory location - Google Patents

Abstract

FIELD: pulse engineering, computer engineering, and control systems. SUBSTANCE: nonvolatile memory location that has Schmitt flip-flop, majority element, and inverter is provided in addition with two diodes and capacitor. EFFECT: enhanced output noise immunity, reduced power requirement in data storage mode. 1 cl, 1 dwg

Description

The invention relates to a pulse technique and can be used in computing devices and control systems.

A non-volatile memory cell is known (see AS USSR No. 1811353 dated 04/02/90, MKI N 03 K 3/286. Non-volatile memory cell. G. I. Shishkin, publ. 07.20.95, bull. No. 20), containing a core with a rectangular hysteresis loop and two windings, an RS-flip-flop, three logic elements, a resistor, an output bus and polling buses, resolution and setting to zero and one. The end of the first core winding is connected to the output of the first logic element, one input of which is connected to the output bus and the direct output of the RS-trigger. The output of the second logic element is connected to one of the inputs of the third logic element. The other input of the first logic element is connected to the installation bus in the unit. The beginning of the first core winding through a resistor is connected to the output of the third logic element, the other input of which is connected to the installation bus to zero. One of the inputs of the second logic element is connected to the direct output of the RS-trigger, the other input is connected to the polling bus. The enable bus is connected to the R-input of the RS-flip-flop, the S-input of which is connected to the beginning of the second core winding, the end of which is connected to a common bus. The first and third logical elements are made in the form of EXCLUSIVE OR elements, and the second logical element is in the form of an OR-NOT element.

A disadvantage of the known non-volatile memory cell is the limited functionality associated with the lack of the ability to continuously retrieve information.

Known non-volatile memory cell (see RF patent No. 2036547 from 04.04.91, MKI N 03 K 3/286, 3/037. Non-volatile memory cell. GI Shishkin, publ. 27.05.95, bull. No. 15), containing an RS flip-flop, the direct output of which is connected to the output bus, three logic elements, the first inputs of the first and third of which are connected to the unit buses to one and zero, respectively, a core with a rectangular hysteresis loop and the first and second windings, the ends of which are connected to the output of the first logic element and the common bus, respectively, the first resistor and bus power, a second core with a rectangular hysteresis loop and two windings, the second - fourth resistors. The second logic element is equipped with a third input, second and third outputs and is made in the form of a four-channel switch, and the first and third logic elements are in the form of, respectively, the first and second bidirectional keys, the control inputs of which are the first inputs of these logic elements. The first and second address inputs of the four-channel switch are connected to the unit buses to one and zero, respectively, and the information input is to the information inputs of bidirectional keys and the power bus, the first output is from the beginnings of the first core windings, the second input is from the S-input of the RS-flip-flop and through the first resistor with the beginning of the second winding of the first core, the third output with the R-input of the RS-trigger and through the second resistor with the beginning of the second winding of the second core, the end of which is connected to a common bus. The direct and inverse outputs of the RS flip-flop through the third and fourth resistors are respectively connected to the ends of the first windings of the first and second cores, and the output of the second bidirectional switch is connected to the end of the first winding of the second core.

Non-volatile memory cell is the closest in technical essence to the claimed device and is taken as a prototype.

The disadvantages of the prototype are low noise immunity at the inputs and increased consumption in the information storage mode.

The problem solved by the invention is the creation of a non-volatile memory cell with increased noise immunity at the inputs and low power consumption in the information storage mode.

The technical result is achieved by the fact that in a non-volatile memory cell containing three logic elements, installation buses of one and zero, a common bus, two cores with a rectangular hysteresis loop and two windings each, the first windings of which are connected to each other and two resistors, the first output the first resistor is connected to the beginning of the first winding of the second core with a rectangular hysteresis loop, and the end of the first winding of the first core with a rectangular hysteresis loop is connected to the output of the third logical ele cient, the output of the second NAND gate connected to a first terminal of the second resistor. New is that the first logic element is made in the form of a Schmitt trigger, the second logic element is made in the form of a majority element, and the third logic element is made in the form of an inverter, two diodes and a capacitor are additionally introduced, the first output of which is connected to the common bus, and the second output the capacitor is connected to the second terminal of the second resistor and the input of the Schmitt trigger, the inverse output of which is connected to the second terminal of the first resistor and to the input of the inverter, the output of which is connected to the first input of the majority element and anode of the first diode, the cathode of which is connected to the beginning of the first winding of the first core with a rectangular hysteresis loop and to the cathode of the second diode, the anode of which is connected to the first output of the first resistor, the second input of the majority element is connected to the beginning of the second winding of the first core with a rectangular hysteresis loop, the end of which is connected to the installation bus to one, and the installation bus to zero is connected to the end of the second winding of the second core with a rectangular hysteresis loop, the beginning of which is connected to tim entrance majority element.

The specified set of features allows to increase noise immunity at the inputs and reduce power consumption in the information storage mode.

The drawing shows a schematic diagram of a non-volatile memory cell.

The non-volatile memory cell contains a setup bus of 1, a setup bus of zero 2, a common bus 3, Schmitt trigger 4, a majority element 5, an inverter 6, the first and second resistors 7 and 8, respectively, the first and second cores with a rectangular hysteresis loop and two windings 9 and 10, respectively, the first and second diodes 11 and 12, respectively, and a capacitor 13.

The installation bus to unit 1 is connected to the end of the second core winding with a rectangular hysteresis loop 9, the beginning of which is connected to the second input of the majority element 5, the first input of which is connected to the end of the first winding of the core with a rectangular hysteresis loop 9 and the anode of the diode 11, the cathode of which is connected to the beginning of the first winding of the core with a rectangular hysteresis loop 9, with the cathode of the diode 12 and the end of the first winding of the core with a rectangular hysteresis loop 10, the beginning of which is connected to the anode of the diode 12 and the first output at the resistor 7. The beginning of the second core winding with a rectangular hysteresis loop 10 is connected to the zero bus 2, and its end is connected to the third input of the majority element 5, the output of which is connected to the first output of the resistor 8, the second output of which is connected to the input of the Schmitt trigger, the inverse output of which is connected to the second output of the resistor 7 and to the input of the inverter 6, the output of which is connected to the anode of the diode 11. The first output of the capacitor 13 is connected to a common bus 3, and its second output is connected to the second output of the resistor 8.

Non-volatile memory cell operates as follows.

In the initial state, a signal with a logic level of “0” is sent to the installation bus to unit 1 of the device, and a signal with a logic level of “1” is sent to the installation bus to zero 2: The device is in information storage mode.

Suppose that the output of the majority element 5 and the cores with a rectangular hysteresis loop 9, 10 are in a logical “0” state. The state “logical” “0” of cores with a rectangular hysteresis loop 9, 10 is taken to be the state in which they are magnetized by the current flowing into the beginning of their first winding. Logic level “1” is present at the output of Schmitt trigger 4, and logic level “0” is at the output of inverter 6, which is a direct output of the device, therefore, current limited by resistor 7 flows through the first windings of the cores with a rectangular hysteresis loop 9, 10. this voltage on the first winding of the core with a rectangular hysteresis loop 10 is limited by the direct voltage of the diode 12. At the first and second inputs of the majority element 5 there is a logic level of “0”, and its third input is a level of logic “1”.

When a positive polarity pulse arrives at the unit bus at unity 1, a logical “1” level appears at the second input of the majority element 5, which leads to the appearance of a logical “1” level at its output. This leads to the appearance of a logical “0” signal at the output of Schmitt trigger 4 and a logical “1” signal at the output of inverter 6. Therefore, a current limited by resistor 7 starts to flow through the first windings of the cores with a rectangular hysteresis loop 9, 10 and magnetizing cores with a rectangular hysteresis loop 9, 10 to the logical “1” state. In this case, the voltage at the first winding of the core with a rectangular hysteresis loop 9 is limited by the direct voltage of the diode 11 and the time of its magnetization reversal is longer than the magnetization reversal time of the core with a rectangular hysteresis loop 10, at which moment the diode 12 is turned on in the opposite direction, and a pulse is generated on its second winding , leading to the appearance of an impulse with a logic level of “0” at the third input of the majority element, an impulse is formed, the duration of which is equal to the core remagnetization time. But since at the first two inputs of the majority element 5 there is a logic level “1”, the state of its output does not change. A pulse is generated on the second winding of the core with a rectangular hysteresis loop 9, which is associated with the process of its magnetization reversal, but it does not lead to the appearance of a signal with a logic level “0” at the second input of the majority element 5, since the voltage on the first winding is limited by the direct voltage of diode 11. The resistance value of the resistors 13 and 14 in the prototype is greater than the resistance value of the resistor 7 of the proposed device, since in the prototype each of them provides the magnetization reversal current of both cores with the same speed Yu. Therefore, in the information storage mode, the proposed device consumes less current than the prototype in a similar mode.

After the magnetization reversal of the cores to the logical “1” state, the pulses on the second windings of the cores with a rectangular hysteresis loop 9, 10 end. A pulse of positive polarity on the installation bus to unit 1 ends. At the first and third inputs of the majority element 5 and its output there is a logical level of “1”.

Similarly, the non-volatile memory cell switches to the logical “0” state when a pulse with a logical “0” level is sent to the zero bus 2.

When interference arrives at unit 1, the duration of which does not exceed the magnetization reversal time of the core with a rectangular hysteresis loop 10, the voltage on the first winding of which is not limited by the direct voltage of the diode 12, the processes in the device during its operation are similar to those described above. After the end of the interference, signals with a logic level of “0” are set at the second and third inputs of the majority element 5 and its output, which leads to the appearance of a logic level of “1” at the output of Schmitt trigger 4 and a level of logical “0” at the output of inverter 6. Therefore, through the first windings of the cores with a rectangular hysteresis loop 9, 10, a current begins to flow, limited by a resistor 7 and magnetizing the cores with a rectangular hysteresis loop 9, 10 to a logical “1” state, while the voltage on the first winding of the core with a rectangular hysteresis loop 10 is limited by the direct voltage of the diode 12, after which the logical “1” level appears at the third input of the majority element 5, and the logical “0” level at its first and second inputs. On the second winding of the core with a rectangular hysteresis loop 9, in which at that moment the diode 11 is turned on in the opposite direction, an interference pulse is generated due to the imperfect core hysteresis loop and its partial magnetization reversal during the action of the interference. This leads to the appearance of the logical level “1” at the second input of the majority element 5, the output of which forms an interference pulse with a logical level “1”, absorbed by the integrating RC circuit, consisting of a resistor 8 and a capacitor 13. The cores are magnetized to the initial state of the logical “ 0 ”.

It should be noted that the considered interference pulse can occur several times between the installation pulses in the unit and zero, and each time the cores restore their state.

Similarly, processes occur when interference occurs with a logic level of “0” on the installation bus to zero 2 and under the influence of power interference.

Schmitt trigger 4, majority element 5 and inverter 6 can be performed on 564TL1, 564LP13 and 564LN2 microcircuits, respectively. As resistors 7, 8, C2-33 type resistors can be used, as cores 9, 10 - zMch-3 / 2.5-60 cores de4.804.005TU. As diodes 11, 12, diodes of type 2D522 can be used, and as a capacitor 9, a capacitor of type K10-17c.

A laboratory model of a non-volatile memory cell was made, made according to the drawing scheme, tests of which confirmed the feasibility and practical value of the claimed object.

Claims (1)

A non-volatile memory cell containing three logic elements, installation buses at “1” and “0”, a common bus, two cores with a rectangular hysteresis loop and two windings each, the first windings of which are connected together, and two resistors, the first output of the first resistor connected to the beginning of the first winding of the second core with a rectangular hysteresis loop, and the end of the first winding of the first core with a rectangular hysteresis loop is connected to the output of the third logic element, the output of the second logic element is connected n with the first output of the second resistor, characterized in that the first logic element is made in the form of a Schmitt trigger, the second logic element is made in the form of a majority element, and the third logic element is made in the form of an inverter, two diodes and a capacitor are additionally introduced, the first output of which is connected to a common bus, and the second output of the capacitor is connected to the second output of the second resistor and the input of the Schmitt trigger, the inverse output of which is connected to the second output of the first resistor and to the input of the inverter, the output of which is single with the first input of the majority element and the anode of the first diode, the cathode of which is connected to the beginning of the first winding of the first core with a rectangular hysteresis loop and the cathode of the second diode, the anode of which is connected to the first output of the first resistor, the second input of the majority element is connected to the beginning of the second winding of the first core with a rectangular hysteresis loop, the end of which is connected to the installation bus at “1”, and the installation bus at “0” is connected to the end of the second winding of the second core with a rectangular hysteresis loop Isa, the beginning of which is connected to the third input of the majority element.