RU2023314C1 - Device for representation of symbols on tv display screen - Google Patents

Abstract

FIELD: automatics and computer engineering, alpha-numeric and alpha-mosaic information display systems. SUBSTANCE: device has sync pulse generator 1, regeneration address counter 2, switch, buffer 12, control unit 7, two gangs 10,11 of AND gates, random-access storage unit 4, adder 9, read-only storage unit 5, gang 6 of OR gates, code converter 13, encoding unit 14. EFFECT: enhanced reliability, improved quality. 13 dwg

Description

 The invention relates to automation and computer technology and can be used to build alphanumeric and alphanumeric information display systems.

 The purpose of the invention is the expansion of the scope of the device due to the possibility of displaying subscript and superscript indices and alphabetic-mosaic information and increasing its speed by increasing the exchange rate by using a phase-independent exchange regeneration cycle.

 In FIG. 1 presents a structural diagram of the proposed device; in FIG. 2 is a block diagram of a storage unit; figure 3 - driver control signals; figure 4 - adder; figure 5 is an example of encoding alphabetic-mosaic information; 6 is an example of encoding a mosaic symbol; 7 is an example of an image of superscript and subscript characters; on Fig is a block diagram of a control unit; figure 9 is a code Converter; in FIG. 10 and 11 - fragments of figure 1 - structurally and physically; in FIG. 12 is a fragment of figure 3 - structurally and physically; Fig.13 - adder. In FIG. 11-13, fragments of the structural diagram shown in Fig. 1 are additionally shown in order to explain its connections, which being single-wire and multi-wire (not trunk) are graphically depicted in the same way, with each functional unit connecting to the multi-wire line only to the necessary wires.

 The device comprises a clock generator 1, a regeneration address counter 2, a switch 3, a RAM block 4, a permanent memory block 5, an OR block 6, a control block 7, a control signal generator 8, an adder 9, the first 10 and second 11 blocks of And elements, buffer 12, code converter 13, coding unit 14.

 Positions 15, 16, 17, 18 and 19 indicate the outputs of the control unit 7.

 Block 10 contains elements 20-35 AND, and block 11 contains elements 36-51 I.

 Shaper 8 control signals contains multiplexers 52 and 53, elements 54-69 I.

 The control unit 7 contains AND elements 70-74, AND-NOT element 75, D-flip-flops 76 and 77, NOT elements 78 and 79. Code converter 13 comprises a counter 80 and a shift register 81.

 For each of the wires, the communication bus with the switch 3 from the control unit 7 receives signals that are used by the switch 3 as clock pulses and selection signals.

 The use of a buffer in solving the problem of matching the recording of information from a computer to a random access memory (RAM) provides the following modes of operation with a random access memory of regeneration: independent access of a computer, sequential access, direct access of the regeneration node to RAM.

 The disadvantage of the independent computer access mode is the appearance of interference on the display screen during the editing of information and data exchange caused by asynchronous interruption of the regeneration process.

 Sequential access mode provides sequential access to RAM. In this mode, the computer is put into a standby state when accessing the RAM working with the regeneration unit. The way out of this state is carried out by means of regeneration schemes. These signals are issued when accessing the RAM from the side of the regeneration unit during the return stroke of the CRT beam of the display in a row and in a frame.

 The direct access mode of the regeneration unit to RAM is characterized by the fact that the regeneration RAM is considered as the RAM of the processor and the regeneration unit organizes direct access to it by putting the microprocessor in the "capture" mode with the lock of its operation for the period of information regeneration, which reduces the system performance.

 The proposed device uses the independent access mode of the computer, but unlike the above does not contribute to the appearance of interference on the screen.

 This is achieved by the fact that the operating time is divided into two periods: the period of use of RAM for regeneration and the period of other possible uses of RAM, i.e. recording information from a computer to RAM, reading information from RAM to a buffer, followed by asynchronous reading of its computer.

 In known communication devices of a video monitor controller having a random access memory (RAM), a microprocessor is possible without interference on the screen only during a CRT beam backward line or frame. This is half the duration of the video monitor, which, delaying the issuance of the signal "readiness", slows down the exchange of information and reduces the speed of the device forming characters in general.

 In the proposed device, there is no such restriction, since half of the time for drawing a raster line of each character is used to connect block 4 (screen RAM) with a microprocessor, and the other half is enough to provide a regenerative fragment, i.e. to load the code converter 13 with character bitmap data. The repetition rate of characters during regeneration is greater than the maximum possible frequency of microprocessor exchange.

 Thus, the moments of possible communication of the microprocessor with the RAM of the video monitor controller are more often than the clock frequency of the microprocessor and exchange delays are significantly reduced. In the known device (prototype), the maximum delay corresponds to the duration of the visible part of the raster line.

 The foregoing considerations can be illustrated by such an example. If in the raster line of the sign there are 16 points, in one line of the image 48 characters are placed, and the clock frequency is 20 MHz, then in the known device the delay is 50x16x48 = 38.4 μs.

In the case of using the proposed technical solution, the delay will be
50x16 = 0.8 μs.

 This example shows that the delay is reduced, and therefore, the speed increases in this example by 48 times.

 Thus, the positive effect of using the proposed technical solution in relation to improving performance is obvious.

 A feature of the proposed device is the ability to exchange RAM and a computer independent of the regeneration cycle, while the device circuit is constructed in such a way that the exchange with the computer occurs via the data bus bytes, and reading during regeneration is carried out in double-byte words, and thus it is possible to perform regeneration more exact characters - with a large number of segments and character attributes than the width of the data bus of the applied computer allows. Thus, the device creates an internal data bus of double width in comparison with the width of the bus in the computer.

 The adder 9 transcodes the address of the line of the symbol raster in order to display subscript or superscript indices. This is achieved by adding to the code the line number of the raster constants "12", "2" or "0" depending on the attribute of the character: normal character, superscript, subscript, respectively (see Fig.7). In the proposed device, an adder is used in the connection diagram of the operands (figure 4). The third and fourth inputs of operand B are combined, the first input is grounded. Thus, the adder performs the formation of superscripts in a simple way by regenerating superscripts and subscripts.

 The driver 8 of the control signals in combination with the code converter 13 and the control from the symbol attribute bus creates the possibility of simple mosaic display of information using simple means.

 Figure 5 shows the familiarity, consisting of 16x16 segments. All segments are grouped into 8 sectors, each of which, in the case of the presence of an alphabetic code attribute (attribute bit, for example, "8" bit): is controlled by the corresponding bit of the eight-bit byte of the symbol code in the alphabetic-mosaic manner, as shown in Fig.6.

 Figure 7 shows the familiarity, where a) a normal character, b) a superscript character, and c) a subscript character.

Claims (1)

 DEVICE FOR DISPLAYING SIGNS ON THE TELEVISION INDICATOR SCREEN, containing a clock generator, the output of which is connected to the counting input of the regeneration address counter, the first output of which is connected to the control input of the switch, the first output of which is connected to the address input of the main memory block, the first output of which is connected to the first input-output of the permanent memory block and the information input of the buffer, the control input of which is connected to the first output of the control unit, the second output of which is connected n to the control input of the RAM unit, the second output of the switch is connected to the control input of the control unit, the sync input of which is connected to the second output of the address counter, the information input of the switch is connected to the address bus of the device, the control bus of which is connected to the information input of the control unit, and a code converter, characterized in that in order to expand the scope of the device by displaying subscript and superscript indices and alphabetic-mosaic information and increasing its speed action by increasing the exchange rate by using a phase-independent regenerative exchange cycle, the device contains the first and second blocks of AND elements, an EL element, an adder, a coding unit and a driver of control signals, the output of which is connected to the first input of the OR element block, the output of which is connected to the information input of the code converter, the control input of which is connected to the output of the clock generator, and the output to the control input of the coding block, the output of which is the output m device for connecting to the video input of a television indicator, the third output of the control unit is connected to the first control inputs of the first and second blocks of elements And, the second control inputs of which are connected respectively to the fourth and fifth outputs of the control unit, the information input of the first block of elements And is connected to the output of the buffer, the input-output of the first block of elements And - with the data bus of the device, the first output-input of the block of RAM - with the input-output of the first block of elements And, with the first input-output of the second about the block of elements AND, the first information input-output of the driver of control signals and the information input of the adder, the second output-input of the block of RAM is connected to the second input-output of the second block of elements AND, the information input of the adder, with the second input-output of the block of permanent memory, the second information input-output of the driver of the control signals and information input of the coding unit, the third output of the counter of the regeneration address is connected to the control inputs of the driver of the control signals and an adder whose output is connected to the address input of the read-only memory block, the output of which is connected to the second input of the OR block.

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