RU2017142876A - LOGICAL TRANSFORMER - Google Patents
LOGICAL TRANSFORMER Download PDFInfo
- Publication number
- RU2017142876A RU2017142876A RU2017142876A RU2017142876A RU2017142876A RU 2017142876 A RU2017142876 A RU 2017142876A RU 2017142876 A RU2017142876 A RU 2017142876A RU 2017142876 A RU2017142876 A RU 2017142876A RU 2017142876 A RU2017142876 A RU 2017142876A
- Authority
- RU
- Russia
- Prior art keywords
- majority
- group
- input
- majority elements
- elements
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
- G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
- G06F7/57—Arithmetic logic units [ALU], i.e. arrangements or devices for performing two or more of the operations covered by groups G06F7/483 – G06F7/556 or for performing logical operations
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/20—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits characterised by logic function, e.g. AND, OR, NOR, NOT circuits
- H03K19/23—Majority or minority circuits, i.e. giving output having the state of the majority or the minority of the inputs
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Computational Mathematics (AREA)
- Mathematical Physics (AREA)
- Mathematical Analysis (AREA)
- Mathematical Optimization (AREA)
- Pure & Applied Mathematics (AREA)
- Computer Hardware Design (AREA)
- Logic Circuits (AREA)
Claims (1)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
RU2017142876A RU2700558C2 (en) | 2017-12-07 | 2017-12-07 | Logic converter |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
RU2017142876A RU2700558C2 (en) | 2017-12-07 | 2017-12-07 | Logic converter |
Publications (3)
Publication Number | Publication Date |
---|---|
RU2017142876A true RU2017142876A (en) | 2019-06-10 |
RU2017142876A3 RU2017142876A3 (en) | 2019-07-17 |
RU2700558C2 RU2700558C2 (en) | 2019-09-17 |
Family
ID=66793016
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
RU2017142876A RU2700558C2 (en) | 2017-12-07 | 2017-12-07 | Logic converter |
Country Status (1)
Country | Link |
---|---|
RU (1) | RU2700558C2 (en) |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2414874B2 (en) * | 1974-03-27 | 1977-05-05 | SYNCHRONOUS SLIDING REGISTER WITH SERIES AND PARALLEL INPUT AND BASIC INPUT | |
SU1439750A1 (en) * | 1987-04-03 | 1988-11-23 | Предприятие П/Я Г-4190 | Device for receiving and majority decoding of information |
RU2248034C1 (en) * | 2003-05-12 | 2005-03-10 | Ульяновский государственный технический университет | Logical converter |
RU2281545C1 (en) * | 2005-05-11 | 2006-08-10 | Государственное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" | Logical transformer |
RU2294007C1 (en) * | 2005-11-03 | 2007-02-20 | Государственное образовательное учреждение высшего профессионального образования "Ульяновский государственный технический университет" | Logical transformer |
-
2017
- 2017-12-07 RU RU2017142876A patent/RU2700558C2/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
RU2700558C2 (en) | 2019-09-17 |
RU2017142876A3 (en) | 2019-07-17 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MM4A | The patent is invalid due to non-payment of fees |
Effective date: 20191208 |