RU2016146518A - Матричная подложка и устройство отображения - Google Patents
Матричная подложка и устройство отображения Download PDFInfo
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- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
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- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
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- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
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- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
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Claims (18)
1. Матричная подложка, содержащая линию общего электрода, множество линий затвора и множество линий данных, которые пересекаются друг с другом, и пиксельные модули, заданные посредством соседних линий затвора и соседних линий данных, каждых из пиксельных модулей содержит пиксельный электрод и общий электрод, первый изолирующий слой размещен между пиксельным электродом и общим электродом, отличающаяся тем, что каждый из пиксельных модулей дополнительно содержит линию электрода хранения, линия электрода хранения и пиксельный электрод, по меньшей мере, частично перекрываются, второй изолирующий слой размещен между линией электрода хранения и пиксельным электродом, и линия электрода хранения и общий электрод соединены с линией общего электрода, соответственно.
2. Матричная подложка по п. 1, отличающаяся тем, что область без отображения матричной подложки содержит предварительно заданный участок, в котором размещена контактная площадка электрода хранения, линия электрода хранения соединена с контактной площадкой электрода хранения, и в предварительно заданном участке линия общего электрода соединена с общим электродом и контактной площадкой электрода хранения, соответственно.
3. Матричная подложка по п. 2, отличающаяся тем, что линия общего электрода изготовлена из того же материала, что и линии данных, и размещена в том же слое, что и линии данных, и линия электрода хранения и контактная площадка электрода хранения изготовлены из того же материала, что и линии затвора, и размещены в том же слое, что и линии затвора.
4. Матричная подложка по п. 3, отличающаяся тем, что общий электрод расположен выше пиксельного электрода, линия общего электрода, линии данных и пиксельный электрод размещены на втором изолирующем слое, и линии затвора расположены ниже пиксельного электрода.
5. Матричная подложка по п. 3, отличающаяся тем, что первое сквозное отверстие размещено в участке первого изолирующего слоя, соответствующем предварительно заданному участку, общий электрод соединен с линией общего электрода посредством первого сквозного отверстия; второе сквозное отверстие размещено в участке второго изолирующего слоя, соответствующем предварительно заданному участку, линия общего электрода соединена с контактной площадкой электрода хранения посредством второго сквозного отверстия.
6. Матричная подложка по п. 2, отличающаяся тем, что линия электрода хранения, контактная площадка электрода хранения и линии общего электрода изготовлены из того же материала, что и линии затвора, и размещены в том же слое, что и линии затвора, и линия общего электрода и контактная площадка электрода хранения образуют цельную конструкцию.
7. Матричная подложка по п. 6, отличающаяся тем, что общий электрод расположен выше пиксельного электрода, и линии затвора расположены ниже пиксельного электрода.
8. Матричная подложка по п. 6, отличающаяся тем, что третье сквозное отверстие размещено в участке первого изолирующего слоя и второго изолирующего слоя, соответствующем предварительно заданному участку, и общий электрод соединен с контактной площадкой электрода хранения посредством третьего сквозного отверстия.
9. Матричная подложка по любому из пп. 2-8, отличающаяся тем, что предусмотрено множество линий электрода хранения, которые являются параллельными с направлением прохождения линий затвора, и каждая из множества линий электрода хранения соответствует ряду пиксельных электродов.
10. Матричная подложка по п. 9, отличающаяся тем, что предусмотрено множество предварительно заданных участков и множество контактных площадок электрода хранения, и каждая из контактных площадок электрода хранения соединена с одной из линий электрода хранения;
предусмотрено множество линий общего электрода, каждая из множества линий общего электрода, по меньшей мере, соединена с контактной площадкой электрода хранения в одном из предварительно заданных участков и дополнительно соединена с общим электродом в предварительно заданном участке.
11. Матричная подложка по п. 9, отличающаяся тем, что предусмотрено множество предварительно заданных участков и множество контактных площадок электрода хранения, и каждая из контактных площадок электрода хранения соединена с одной из линий электрода хранения;
предусмотрена только одна линия общего электрода, линия общего электрода соединена с контактной площадкой электрода хранения в каждом из предварительно заданных участков и соединена с общим электродом в каждом из предварительно заданных участков.
12. Матричная подложка по п. 10, отличающаяся тем, что каждый из предварительно заданных участков расположен между линиями прохождения двух соседних линий затвора, и каждый из предварительно заданных участков соответствует ряду пиксельных электродов; направление прохождения каждой из линий общего электрода является параллельным с направлением прохождения линий затвора.
13. Матричная подложка по п. 11, отличающаяся тем, что каждый из предварительно заданных участков расположен между линиями прохождения двух соседних линий затвора, и каждый из предварительно заданных участков соответствует ряду пиксельных электродов; направление прохождения линии общего электрода является параллельным с направлением прохождения линий данных.
14. Матричная подложка по любому из пп. 3-8, отличающаяся тем, что щели размещены в общем электроде и в участке, соответствующем лежащему ниже пиксельному электроду.
15. Матричная подложка по любому из пп. 3-8, отличающаяся тем, что первый изолирующий слой имеет толщину 1-3 мкм.
16. Устройство отображения, отличающееся тем, что содержит матричную подложку по любому из пп. 1-15.
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