RU2012140006A

RU2012140006A - THREE-START PULSE DISTRIBUTOR WITH AUTOMATIC SINGLE ERROR CORRECTION

Info

Publication number: RU2012140006A
Application number: RU2012140006/07A
Authority: RU
Inventors: Валентин Михайлович Люханов; Владимир Васильевич Копытин
Priority date: 2012-09-18
Filing date: 2012-09-18
Publication date: 2014-03-27
Also published as: RU2526859C2

Abstract

Трехтактный распределитель импульсов с автоматической коррекцией одиночных ошибок, содержащий реверсивный двоичный счетчик, тактовый вход которого соединен с шиной тактовых импульсов, вход разрешения счета - с шиной управления, а вход задания направления счета - с шиной реверса, первый, второй, третий мультиплексоры, стробирующие входы которых объединены и подключены к шине стробирования, разрядные выходы счетчика а, aсоединены с одноименными адресными входами мультиплексоров, отличающийся тем, что в него введены первая, вторая, третья схемы свертки, дешифратор и индикатор синдрома ошибки, первый, второй, третий управляемые инверторы, выходы которых являются выходами распределителя, а первые входы первого-третьего управляемых инверторов соединены соответственно с первыми выходами первого-третьего мультиплексоров, вторые выходы которых соединены с первыми входами схем свертки, выходы которых соединены с одноименными входами индикатора и дешифратора синдрома ошибки, выходы дешифратора третий, пятый, шестой соединены соответственно со вторыми входами первого-третьего управляемых инверторов, вторые входы первой и второй схем свертки соединены с первым выходом первого мультиплексора, а третьи входы второй и третьей схем свертки соединены с первым выходом третьего мультиплексора, объединение второго входа третьей схемы свертки с третьим входом первой схемы свертки подключено к первому выходу второго мультиплексора, при этом нулевой, четвертый, пятый информационные входы первого мультиплексора, первый, четвертый, шестой информационные входы второго мультиплексора, второй, пятый, шестой информационныA three-stroke pulse distributor with automatic correction of single errors, containing a reversible binary counter, the clock input of which is connected to the clock bus, the resolution enable input is to the control bus, and the input of the direction of the counting input is to the reverse bus, the first, second, third multiplexers, gate inputs which are combined and connected to the gating bus, the counter outputs a, a are connected to the same address inputs of the multiplexers, characterized in that the first, second, third convolution gates, decoder and indicator of the error syndrome, the first, second, third controlled inverters, the outputs of which are the outputs of the distributor, and the first inputs of the first and third controlled inverters are connected respectively to the first outputs of the first and third multiplexers, the second outputs of which are connected to the first inputs of the convolution schemes the outputs of which are connected to the same inputs of the indicator and the decoder of the error syndrome, the outputs of the decoder third, fifth, sixth are connected respectively to the second inputs of the first or third controlled inverters, the second inputs of the first and second convolution schemes are connected to the first output of the first multiplexer, and the third inputs of the second and third convolution schemes are connected to the first output of the third multiplexer, combining the second input of the third convolution scheme with the third input of the first convolution circuit is connected to the first output of the second multiplexer while the zero, fourth, fifth information inputs of the first multiplexer, the first, fourth, sixth information inputs of the second multiplexer, the second, fifth, sixth information

Claims

A three-stroke pulse distributor with automatic correction of single errors, containing a reversible binary counter, the clock input of which is connected to the clock bus, the resolution enable input is to the control bus, and the input of the direction of the counting input is to the reverse bus, the first, second, third multiplexers, gate inputs which are combined and connected to the gating bus, the counter outputs a ₀ , a _{1 are} connected to the same address inputs of the multiplexers, characterized in that the first, second, third it has convolution schemes, a decoder and an indicator of the error syndrome, the first, second, third controlled inverters, the outputs of which are the outputs of the distributor, and the first inputs of the first and third controlled inverters are connected respectively to the first outputs of the first and third multiplexers, the second outputs of which are connected to the first inputs of the circuits convolutions, the outputs of which are connected to the same inputs of the indicator and the decoder of the error syndrome, the outputs of the decoder third, fifth, sixth are connected respectively to the second inputs of the first-third of its controlled inverters, the second inputs of the first and second convolution schemes are connected to the first output of the first multiplexer, and the third inputs of the second and third convolution schemes are connected to the first output of the third multiplexer, combining the second input of the third convolution scheme with the third input of the first convolution circuit is connected to the first output of the second multiplexer, with zero, fourth, fifth information inputs of the first multiplexer, first, fourth, sixth information inputs of the second multiplexer, second, fifth, sixth information these inputs of the third multiplexer are combined and connected to the power bus (+ E), and the first is the third, sixth, seventh information inputs of the first multiplexer, zero, second, third, fifth, seventh information inputs of the second multiplexer, zero, first, third, fourth, the seventh information inputs of the third multiplexer are combined and connected to a common bus, the zero output of the error syndrome decoder through the inverter is connected to the "device failure" bus.