RU2010138007A

RU2010138007A - FOUR-STEP REVERSE PULSE DISTRIBUTOR FOR CONTROLLING A STEP-BY-STEP ENGINE WITH AUTOMATIC SINGLE ERROR CORRECTION

Info

Publication number: RU2010138007A
Application number: RU2010138007/07A
Authority: RU
Inventors: Валентин Михайлович Люханов (RU); Валентин Михайлович Люханов; Сергей Михайлович Пашенцев (RU); Сергей Михайлович Пашенцев
Original assignee: Общество с ограниченной ответственностью "Антарес" (RU); Общество с ограниченной ответственностью "Антарес"
Priority date: 2010-09-13
Filing date: 2010-09-13
Publication date: 2012-03-20
Also published as: RU2475933C2

Abstract

Четырехтактный реверсивный распределитель импульсов для управления шаговым двигателем с автоматической коррекцией одиночных ошибок, содержащий шины управления, реверса, тактовых импульсов, двухразрядный реверсивный двоичный счетчик, два инвертора и элемент Исключающее ИЛИ, входы которого соединены с выходами реверсивного счетчика, причем тактовый вход счетчика подключен к шине тактовых импульсов, его входы разрешения и направления счета соединены соответственно с шинами управления и реверса, выход элемента Исключающее ИЛИ соединен с входом первого, а вход второго инвертора подключен к выходу старшего разряда счетчика, отличающийся тем, что в него дополнительно введены первая-третья схемы свертки, дешифратор и первый-четвертый управляемые инверторы, при этом первый вход первой схемы свертки объединен с третьими входами второй и третьей схем свертки, а также со вторым входом третьего управляемого инвертора и подключен к выходу элемента Исключающее ИЛИ, вторые входы первой и второй схем свертки объединены с первым входом третьей схемы свертки, а также и со вторым входом первого управляемого инвертора и подключены к выходу первого инвертора, третий вход первой схемы свертки объединен с первым входом второй схемы свертки, а также со вторым входом третьей схемы свертки и вторым входом второго управляемого инвертора и подключен к выходу второго инвертора, а объединенные четвертые входы первой-третьей схемы свертки и второй вход четвертого управляемого инвертора подключены к выходу старшего разряда счетчика, а первые входы первого-четвертого управляемых инверторов соединены соответственно с третьим, A four-stroke reversible pulse distributor for controlling a stepper motor with automatic correction of single errors, containing control buses, reverse, clock pulses, a two-bit reversible binary counter, two inverters and an exclusive OR element, the inputs of which are connected to the outputs of the reversible counter, and the clock input of the counter is connected to the bus clock pulses, its resolution inputs and counting directions are connected respectively to the control and reverse buses, the output of the element is an exclusive OR connection with the input of the first, and the input of the second inverter is connected to the output of the high order of the counter, characterized in that it additionally introduces the first or third convolution circuits, a decoder and the first and fourth controlled inverters, while the first input of the first convolution circuit is combined with the third inputs of the second and the third convolution schemes, as well as with the second input of the third controlled inverter and is connected to the output of the exclusive OR element, the second inputs of the first and second convolution schemes are combined with the first input of the third convolution scheme, as well as with the second input the house of the first controlled inverter and connected to the output of the first inverter, the third input of the first convolution circuit is combined with the first input of the second convolution circuit, and also with the second input of the third convolution circuit and the second input of the second controlled inverter and connected to the output of the second inverter, and the combined fourth inputs of the first the third convolution circuit and the second input of the fourth controlled inverter are connected to the output of the high order of the counter, and the first inputs of the first and fourth controlled inverters are connected respectively to the third,

Claims

A four-stroke reversible pulse distributor for controlling a stepper motor with automatic correction of single errors, containing control buses, reverse, clock pulses, a two-bit reversible binary counter, two inverters and an exclusive OR element, the inputs of which are connected to the outputs of the reversible counter, and the clock input of the counter is connected to the bus clock pulses, its resolution inputs and counting directions are connected respectively to the control and reverse buses, the output of the element is an exclusive OR connection with the input of the first, and the input of the second inverter is connected to the output of the high order of the counter, characterized in that it additionally introduces the first or third convolution circuits, a decoder and the first and fourth controlled inverters, while the first input of the first convolution circuit is combined with the third inputs of the second and the third convolution schemes, as well as with the second input of the third controlled inverter and is connected to the output of the exclusive OR element, the second inputs of the first and second convolution schemes are combined with the first input of the third convolution scheme, as well as with the second input the house of the first controlled inverter and connected to the output of the first inverter, the third input of the first convolution circuit is combined with the first input of the second convolution circuit, and also with the second input of the third convolution circuit and the second input of the second controlled inverter and connected to the output of the second inverter, and the combined fourth inputs of the first the third convolution circuit and the second input of the fourth controlled inverter are connected to the output of the high order of the counter, and the first inputs of the first and fourth controlled inverters are connected respectively to the third, fifth, sixth, seventh outputs of the decoder, the address inputs of which the first, second, fourth are connected respectively to the outputs of the first to third convolution circuits, and the outputs of the first to fourth controlled inverters are the first to fourth outputs of the distributor.