RU2012044C1 - Device for visual control of program execution - Google Patents

Abstract

FIELD: computer engineering. SUBSTANCE: device has unit 1 for registers of current address and data, mode setting unit 2, multiplexers unit 3, initial address register unit 4, comparison unit 5, memory unit 6, number selection unit 7. In addition device has group of inputs for states and synchronization, address input and data input. This inputs serves as device inputs for connection to state synchronization output, address and outputs of controlled device. In addition device has first clock pulse input of memory unit, group of inputs for control of mode in unit for registers of current address and data, group of inputs for control of mode in unit for registers of initial address, which serve as control inputs of device for connection to corresponding outputs of mode control in microcomputer. EFFECT: increased amount of information , increased precision, increased speed. 9 dwg

Description

 The device relates to computer technology and can be used to control the execution of programs of controlled devices (system controller, digital computer, microcomputer, computer, etc.).

 The aim of the invention is to expand the functionality (increase information content, accuracy of control, reduce time spent on control) of the device for visual control by ensuring the registration of the results of the control in the form of an information array, by ensuring compliance of the registered address and the data of the program fragment for the time interval of the functioning of the controlled device Relatively multiple address selected by the operator.

 In FIG. 1 shows a structural diagram of a device for visual control of program execution; in FIG. 2 is a block diagram of the registers of the current address and data; in FIG. 3 is a diagram of a mode setting unit; in FIG. 4 is a block diagram of a multiplexer, in FIG. 5 is a diagram of a block of registers of the starting address; in FIG. 6 is a diagram of a comparison unit; in FIG. 7 is a diagram of a block of RAM; in FIG. 8 is a diagram of a block for selecting a number; in FIG. 9 - algorithm for the joint operation of the device with a microcomputer and with a controlled device.

 A device for visual control of program execution (Fig. 1) contains a block 1 of the registers of the current address and data, a block of 2 mode settings, a block of 3 multiplexers, a block of 4 registers of the starting address, a block of comparison 5, a block of 6 random access memory, a block of number selection 7, a group synchronization and status inputs 8, address input 9, data input 10, which are device inputs for connecting to a group of synchronization and status outputs, to the output of the address and data of a monitored device (system controller, digital computer, computer, etc.), a group of outputs 11 blocks 2, which is connected to the first group of control inputs of the unit 3 of multiplexers, the group of information outputs 12 of the block 4 of the initial address registers, which is connected to the first group of information inputs of the comparison unit 5, the first and second group of inputs / outputs of the block 6 of random access memory, which is the address input and device data and data output of block 6, the first group of outputs-inputs connected to the first group of information inputs of block 1 of the registers of the current address and data and to the second group of information inputs of block 5 comparison, and the second group - to the second group of information inputs of block 1 of the registers of the current address and data, the group of inputs of the control modes of block 1 registers of the current address and data, the group of inputs of the control of the mode of block 4 registers of the starting address, the first clock input of block 6 of RAM, which are the control inputs 13-20 of the device for connecting to the corresponding control outputs of the microcomputer, the information output of block 1 of the registers of the current address and data, which is the output of 21 signs of information activity and a device for connecting to the confirmation input of the presence of a microcomputer, output 22 of the initial installation of the mode setting block 2, which is connected to the reset inputs of the block 1 of the registers of the current address and data, block 4 of the registers of the starting address, to the first input of the control of the block of comparison 5, block 6 operational memory and number selection unit 7, the second input of the mode control of which is the first output 23 of the equality of the operands of the comparison unit 5, and the first output 24 of the RAM unit 6 is the output of the buffer fill indicator for Connections to the information input of block 1 of the registers of the current address and data, the second output of block 5 of comparison is output 25 for connecting to the clock output of block 7 of selecting the number, the second clock input of block 6 of RAM is connected to the output 26 of the status gate of block 3 of multiplexers, the input and the second the group of inputs of which are a group of synchronization inputs 8 and device states for connecting to the synchronization outputs and device states, the second output 27 of the RAM block 6 is the output of the sign of filling bu EPA for connection to a second input of the comparator unit control mode 5, a third output 28 which is the third input of the control unit 7 mode selection number output 29 which is connected to the second input of the mode control unit 6 memory.

 Block 1 registers the current address and data (Fig. 2) contains the registers 30 shift.

 Block 2 of the job modes (Fig. 3) contains a block of 31 registers, RS-trigger 32, element And 33, switches 34, push button switch 35, capacitor 36.

 Block 3 of the multiplexers (Fig. 4) contains AND elements 37, OR elements 38, AND element 39.

 Block 4 registers of the starting address (Fig. 5) contains the registers 40 shift, bus driver 41, the element OR 42.

 Block 5 comparison (Fig. 6) contains a comparison circuit 43, the element And 44, RS-trigger 45, one-shot 46.

 The RAM block 6 (Fig. 7) contains an RAM element 47, a counter 48, an OR element 49, AND 50 elements, an OR-NOT 51 element, an IK trigger 52.

 Block 7 number selection (Fig. 8) contains a block of counters 53 and 54 block of switches 55, block of resistors 56, LEDs 57, IK-trigger 58, element 2I 59.

 Block 1 of the registers of the current address and data is intended for temporary storage in the register 30 of the current address and data coming from block 6 of the RAM through the first and second groups of outputs-inputs to the first and second groups of information inputs of block 1 for storing the signal "Buffer full" through output 24 of the sign of filling the buffer of block 6 with RAM, through the first and second groups of outputs-inputs to the first group of information inputs of block 1 for storing the signal "Buffer full" through the output 24 of block 6 to the information input d of block 1, as well as for generating a confirmation signal in the microcomputer, which is fed to input 21 of the information activity indicator of block 1 from the output of register 30 in accordance with the algorithm (Fig. 9). The width of the register 30 is determined by the width of the address buses and data buses of the monitored device, which are connected to the address input 9 and input 10 of the device data.

 The mode setting unit 2 is intended for selecting the states of the monitored device (selecting a command from the ROM, accessing the ROM, RAM, accessing external devices) via the switches 34, and also for generating a reset signal that comes from the push-button switch 35 via the RS-trigger 32, and the initial installation signal from the RC chain of the block of resistors and capacitor 36 and to the reset output 22 (initial installation for power supply), which initializes the device.

 Unit 3 of the multiplexers is intended for the formation of pulses at time instants determined by the position of the switches 34 of the mode setting unit 2.

 Block 4 registers of the starting address is designed to store the address that defines the beginning of the fragment of the program required for viewing the program by the operator. The address is entered in the register 40 and transmitted to the output of the comparison unit 5 through the bus driver 41 using control signals from the microcomputer, which are fed to the device mode control inputs 16, 17, 18, 19 in accordance with the algorithm (Fig. 9). The width of the register 40 is determined by the width of the address buses of the controlled device, which are connected to the address input 9 of the device.

 Comparison unit 5 is intended for comparing the current address of the monitored device, which is supplied to the second group of information inputs A of the comparison circuit 43 through the device's address input, and the specified address, which is fed to the first group of information inputs B of the comparison circuit 43 from the information output 12 of the initial register block 4 addresses. When comparing the addresses, the comparison circuit 43 gives a pulse to the input of the RS-flip-flop setup 45, the signal from the output of which is transmitted to the output 23 of the equality of the operands of the comparison unit 5 to the number selection unit 7, which allows the passage of clock signals from the output 26 of the state strobe of the unit 3 of multiplexers to a certain moment.

 The RAM block 6 is designed to store a fragment of a program that runs in a controlled device in real time, i.e., current information received from the controlled device through address input 9 and input 10 of the device data to the information input / output of RAM 47.1 and 47 .m at the moments determined by the signals from the output 26 of the state strobe of the unit 3 of the multiplexers and from the output 29 of the recording permission of the selection unit 7 through the AND 50.2 and OR NOT 51 elements and the clock input of the counter 48 for reading the recorded tech data from the block 6 of the RAM through the input-output of random access memory 47.1 and 47. m to the first and second groups of information inputs of block 1 of the registers of the current address and data at the moments determined by the control signal from the microcomputer, in accordance with the algorithm (Fig. 9) through the control input 20 of the device, namely through the AND 50.2, OR NOT 51 elements to the clock input of the counter 48 and through the AND 50.2, OR NOT 51 and OR 49 elements to the write-read permission input of the RAM 47.1 and 47. m , as well as for the formation of the signal "Buffer full" from the output p tolerated by the counter 48 via IK-trigger 52 arrives at the first output characteristic filling buffer RAM unit 6, and for generating a signal "ban" supplied from the counter 48 through the transfer element and the output 50.1 to a second output 27 of memory block 6. The width of the RAM 47.1 and 47. m is determined by the width of the address buses and data buses of the monitored device, which are connected to the address input 9 and input 10 of the device data.

 The informational capacity of the RAM 47.1 and 47. m is determined by the maximum amount of memory required to fill the required fragment of the program.

 Block 1 of the registers of the current address and data are eight-bit shift registers of the type K555IR13.

 Block 4 registers of the starting address are eight-bit shift registers of type K555IR13 and eight-bit bus shapers of type 580BA86.

 As comparison circuit 43 of comparison unit 5, comparison circuits of type 555SP1 may be used.

 The RAM 47.1 and 47. m of the RAM block 6 is a statistical type RAM with a capacity (for example, 1K110) 132RUZ, and a chip type 555IE7 (four-bit asynchronous counter) can be used as counter 48.

 As a circuit 46, a single-shot 555AGZ can be used.

 In block 7, the selection of numbers can be applied indicators 57 type ZLSZ41.

 The device is intended for visual control of the execution of programs of a controlled device built on the basis of microprocessors K680VM80A, KR1821VM85A, KR180VM86, as well as for controlled devices built on the basis of microprocessor sets 1802, 1804, 589 (see. Reference. Digital and analog integrated circuits. / Ed. S.V. Yakubovsky.: Radio and communications, 1990, sections 3.2, 3.6, 3.7, 3.8).

 The device operates as follows.

 To bring the visual control device for program execution to its initial state, the reset input of block 1 of the current address and data registers, block 4 of the start address registers, RAM block 6, the signal "Reset + Initial" is sent to the first reset input of comparison block 5 and RAM block 6 installation "from the output 22 of the initial installation of the mode setting unit 2, which is formed after turning on the device’s power supply from the output of the RC chain 31, 36 or by pressing the button switch 35 by the operator.

 As a result, registers 30 and 40, the shifts of blocks 1 and 4 of the registers of the current address and data and registers of the starting address are set to the initial state, at the output of the IK trigger 58 of the number selection block 7, a prohibition signal of the resulting state clock sequence is generated, which comes through the output 29 of the operand equality to the first input of the AND element 50.2 of the RAM block 6, at the output of the IK-trigger 52 of which a write permission signal is generated, which, by convolution OR 49 with the signal from the output of the OR-NOT 51 element, goes to the input solving the recording of RAM 47, at the inverse output of the IK-trigger 52 of the block, the signal is absent "Fill buffer", which is fed to the first output 24 of the sign of filling the buffer of block 6 of the RAM, the initial code of the address of the RAM 47 appears on the outputs of the counter 48 of the block, which is formed by the signal of the initial installation received at the input of the resolution of the parallel counter download from the output of the And 50.1 element.

 The device operates in two modes: in the recording mode of a fragment of the address program, when data arrives in the RAM block 6 from the outputs of the monitored device in real time through address input 9 and input 10 of the device data; in the mode of reading information from block 6 of the RAM in the microcomputer from the information output of block 1 of the registers of the current address and data through output 21 confirming the presence of the signal of the device.

 The first and second modes are performed together. The separation of these modes in time is solved by the device equipment and control signals from the outputs of the microcomputer to the control inputs 13-20 of the device.

 Blocks 1, 4, 6 of the registers of the current address and data, registers of the starting address and RAM are controlled from the control outputs of the microcomputer, which are connected to the control inputs of the device 13-20 in accordance with the algorithm shown in FIG. 9.

 The starting address of an arbitrary fragment of the program is fed sequentially to the information input for shifting to the left of shift register 40 of block 4 of the starting address registers through the control input 19 of the device, accompanied by control signals received at the clock input, the first and second inputs of register mode selection 40 through control inputs 16, 17 18 of the device according to FIG. 9a. The starting address is stored in the shift register 40 and transmitted when it enters the storage mode at the output of the bus driver 41 by generating a signal from the output of the OR element 42, the first and second inputs of which receive permission signals from the control inputs 17, 18 of the device. The starting address from the output 12 of the block 4 registers of the starting address goes to the first group of information inputs of the comparison unit 5, the second group of information inputs of which the current address is transmitted from the address outputs of the monitored device through the address input 9 of the device. When comparing the address codes present on the first and second information inputs of the comparison circuit 43, a signal is generated at its output, which is fed to the installation input of the RS flip-flop 45 and the inverse input of the single-shot 46, which generates a pulse at an address of a certain duration. From the output of the RS-flip-flop 45 through the output 23 of the equality of operands and from the output of the single-shot 46 through the output 25, the signals are respectively sent to the download input and the clock input of the counter 54 and put it into the counting state of an n-repeatedly repeating address, the number of repetitions of which is preselected by the operator using the push-button switches 55, loaded in the reverse code into the counter 54 through the counter 53 and highlighted on the indicators 57 through the resistor assembly 56. When counting the n-address at the transfer output of the counter 54, a transfer sign is formed, which through And 50.2 tonnes fed to the clock input IK-flop 58. The output of the last sign is generated write enable which, via output unit July 29 to a first input of AND 50.2 and permit passage of the resulting clock signal of a sequence. This sequence comes from the output 26 of the unit 3 of multiplexers, to the second group of state inputs and strobe of which signals from the state output and from the synchronization output of the controlled device through the group of inputs of the device 8 are supplied.

 The processor state of the monitored device changes with each of its internal clock cycles. Therefore, on the second group of state inputs of block 3 of multiplexers, a pulse sequence is formed corresponding to certain moments of the controlled device (accessing the first byte, i.e., a command from ROM, accessing RAM, accessing RAM, accessing external devices and etc.). All generated sequences of states go to the inputs of the elements 37.1. . . 37. n block 3 of the multiplexer, however, only those selected by the operator using the switches 34.1 pass to their outputs. . . 34n block 2 mode settings. After convolution by OR 38.1. . . 38n with a clock signal input to the elements OR 38.1. . . 38n from the controlled device, and then after their convolution according to AND 39, the resulting clock sequence is output 26 of the block 3 multiplexers.

 Addresses and data of the current fragment of the program come from the outputs of the controlled device through the address input 9 and input 10 of these devices to the first and second groups of inputs and outputs of block 6 of RAM.

 Addresses and data are recorded in the RAM 47.1 and 47. m by the resulting clock sequence of state signals from the output 26 of the state strobe, which is fed to the second input of the And 50.2 element. The output of the AND 50.2 element is connected to the first input of the OR-NOT 51 element, from the output of which the signal enters through the OR element 49 to the write enable input to the RAM 47 and at the same time this signal goes to the clock input of the counter 48, from which the next operational address is selected memory 47 block 6 of RAM. After filling the RAM buffer 47 with information of the current program fragment, the signal from the transfer output of the counter 48 through the And 50.1 element goes to the clock input of the IK-trigger 52, from the direct output of which through the OR element 49 a read permission signal is generated from the RAM 47 and from the inverse output of which The signal "Buffer full" is generated. The latter enters through the output 24 of the sign of filling the buffer of the block 6 of the random access memory to the information input of the block 1 of the registers of the current address and data, from the output 21 of the sign of information activity of which the signal is transmitted to the confirmation input of the microcomputer in accordance with the algorithm in FIG. 9b.

 Upon the formation of the signal "Buffer full", the device is switched to the mode of reading information in the microcomputer.

 At the microcomputer control outputs, control signals are transmitted to the device control inputs 13, 14, 15 to the clock input of the mode selection of the shift register 30 of block 1 of the registers of the current address and data and through the input to the second input of the OR element 49, from the output of which the signal goes to the clock input of the counter 48. Information is read from the first and second groups of outputs of the block 6 of RAM into block 1 of the registers of the current address and data, is stored in the register 30 of the shift and transmitted sequentially from its information output 21 to the input confirm waiting for the microcomputer, where it is stored in a specific array A in accordance with the algorithm in FIG. 9th century From the control output of the microcomputer through the control input 20 of the device, a signal is received to the clock input of the RAM block 6, the next address of the RAM 47 is selected from the output of the counter 48, the information is read from the first and second groups of outputs and inputs of the RAM block 6 as described above in accordance with the algorithm of FIG. 9th century

 Information recorded in array A of the microcomputer can be viewed from any address of a fragment of the current program, both in the forward and in the opposite direction of the reference address. Therefore, there is no need for a block of registers of the conical address of the device for visual control of program execution.

 Technical and economic advantages of the proposed technical solution - expanding the functionality of the proposed device by ensuring the preservation of an arbitrary fragment of the program under study, the ability to repeatedly view the program progress and control arbitrary information (including address, data) is determined by the combination of technical means used in the device and the new organization of relations .

 The claimed technical solution provides a reduction in real-time costs when monitoring the execution of programs of a controlled device, in particular for NMLES5740 with an integrated system controller. The effectiveness of the proposed technical solution arises from the calculated data confirming the reduction of real-time costs.

Claims (1)

 DEVICE FOR VISUAL CONTROL OF PROGRAM EXECUTION, comprising a control unit, a block of registers of the current address and data, a block of mode settings, a block of multiplesors, a block of registers of the starting address, a comparison block, and the group of outputs of the block of mode settings is connected to the group of control inputs of the block of multipliers, a group of information outputs block of registers of the starting address is connected to the first group of information inputs of the comparison unit, characterized in that, the device has a RAM block, a selection block n a measure of the address, and the first and second groups of inputs and outputs of the RAM block are connected to the inputs of the address and data of the device for connecting to the outputs of the address and data of the monitored device, and the first group of inputs and outputs of the RAM block is connected to the first group of information inputs of the register block of the current addresses and data to the second group of information inputs of the comparison unit, the second group of inputs and outputs of the RAM block is connected to the second group of information inputs of the reg the current address and data, the group of control mode inputs of which, the group of control mode inputs of the block of registers of the starting address, the first clock input of the block of RAM are connected to the corresponding outputs of the control block, the information input of the block of registers of the current address and data is connected to the sign input, activity of the information of the block control, the output of the initial installation of the mode setting block is connected to the reset inputs of the block of registers of the current address and data and the block of registers of the starting address, to the first input m control the mode of the comparison block, the RAM block and the address number selection block, the second mode control input of which is connected to the first output of the comparison block, the output of the buffer block filling indicator is connected to the information input of the register block of the current address and data, the second output of the comparison block is connected to the clock input of the address number selection block, the second clock input of the RAM block is connected to the output of the multiplexer block, the second group of inputs of which is a group of inputs with synchronization of device states for connecting to the synchronization outputs and states of the monitored device, the output of the prohibition sign of the RAM block is connected to the second mode control input of the comparison unit, the third output of which is connected to the third mode control input of the address number selection unit, the output of which is connected to the second mode control input RAM, and the address number selection block contains the first and second counters, a switch node, an indicator node, a JK trigger, an AND element, a first the first input of which and the boot input of the second counter are the second control input mode of the address number selection block, the second input of the AND element is connected to the transfer output of the second counter, the clock input of which is connected to the clock input of the address number selection block, the information inputs of the second counter are connected to the outputs of the first counter and inputs of the indicator node, the clock inputs of the first counter are connected to the outputs of the switch node, the boot inputs of the first counter are connected to the first input of the control unit mode selection block nom Address range, reset inputs of the first and second counter and K-input of the JK-trigger are connected to the bus of the potential zero of the device, the J-input of the JK-trigger is connected to the unit potential bus, the reset input of the JK-trigger is connected to the third mode control input of the selection block address numbers, the clock input of the JK trigger is connected to the output of the And element, the inverse output of the JK trigger is the output of the address number selection block.

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