RU2001517C1 - Fractionally-proportional frequency converter - Google Patents

Abstract

Usage: in radio engineering, in receiving-transmitting and measuring equipment Summary of the invention: a fractionally proportional frequency converter comprises a low-pass filter 1. a controlled generator 2. a controlled frequency divider 3, a delay element 4. an accumulating adder 5, a digital-to-analog converter ( DAC) 6, phase dividers 7.8, controlled inverters 9.10, adder 11. Reducing distortion of the output signal by reducing spurious phase modulation when expanding the frequency range of input sines and expanding the range A change in the frequency conversion coefficient is achieved due to the correction circuit including the DAC 6, controlled inverters 9, 10, delay elements 4. phase detectors 7.8 and adder 11 2 or

Description

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ABOUT

The invention relates to a radio engineer and can be used in transceiver and measuring equipment.

The aim of the invention is to reduce distortion of the output signal by reducing the phase-shift phase modulation while expanding the frequency range of the input signals and expanding the range of variation of the frequency conversion coefficient.

In FIG. 1 is a functional diagram of a fractional-proportional frequency converter; in Fig 2 a 0, c, d, d, e, f, h, and, k, l are timing diagrams of its operation.

The fractional-proportional frequency converter contains (Fig. 1) a low-pass filter (LPF) 1, a controlled oscillator 2, a controlled frequency divider 3, a delay element 4, an accumulating adder (H Z) 5, a digital-to-analog converter (DAC) 6, the first and second phase detectors (PD) 7, 8, first and second controlled inverters 9, 10, adder 11. In FIG. 1, 12, 13, 14, 15 denote respectively the output, input of the integer part of the frequency conversion coefficient, input of the fractional part of the frequency conversion coefficient, and the signal input of the fractional proportional frequency converter,

In FIG. Figure 2 shows the timing diagrams of the operation in the case when the integer and fractional parts of the frequency conversion coefficient supplied to the inputs 13, 14, Kel. 4, KDR 1, and those accumulating the adder are two-bit (binary). Figure 2a shows the output sequence at output 12. whose frequency f2

 Kfi 4 - fi, de fi - input 4 frequency

the signal (Fig. 26) supplied to input 15, the fractional-proportional frequency converter operates as follows. In the absence of a signal at the transfer output HZ 5 in the controlled frequency divider 3, the frequency of the output signal is divided by e times equal to Kel. The transfer signals from H25 (Fig. 2c), fed to the control input of the controlled divider 3, increase the division coefficient by one, after which the former division coefficient is again established. The output signal of the controlled divider 3 and the same signal, delayed by one period of the output frequency, are shown in FIGS. 2d, e, respectively. PD 7 and 8 are shown respectively in FIG. 2e, W B N 25 with the frequency of the signal arriving at its clock input, its

contents with the number of Cdr arriving at exit 14. The values of the sum S and transfer P are shown respectively in FIG. 2e, b.

DAC 6 converts the sum value of the accumulating adder 5 into analog form. The signals of the direct and inverse outputs of the DAC 6 are shown in Fig. 2i, k, respectively.

The frequency of the output signal of the controlled divider 3 coincides with the frequency of the input signal, however, due to the fragmentation of the division coefficient and the resolution of digital devices, the output pulses of the controlled divider 3 follow unevenly

(Fig.2g). Their direct comparison in the phase detector 7 with the input ci-element leads to the appearance of a low-frequency parasitic component, which is not eliminated by the low-pass filter 1 and leads to the parasitic

phase modulation of the output of the controlled oscillator 2.

Low-frequency noise at the input of the low-pass filter 1 is eliminated by a correction circuit including a digital-to-analog converter 6, controlled inverters 9 and 10, delay element 4, phase detectors 7 and 8, and adder 11. The fact that the sum of e accumulative adder 5 is used is a temporary error

position of the pulses. The output of adder 11 is shown in FIG. 2l.

The operation of the correction circuit is based on the total summation of phase mismatches between the input signal and two

signals having a fixed phase shift.

The phase of the signal at the output of the controlled divider 3 has two components: p is the phase shift between the input signal

and the output of a controlled divider in the absence of fractional noise,

x is the phase noise. resulting from the discrete operation of digital devices.

If we take the period of the output signal as the unit of measurement of the phase, then at the output of the delay element 4 we obtain a signal with the phase

p + x -1.

in the process of weighted summation

at the output of adder 11, a signal is obtained whose constant component is equal to: V (1 - ХХу + х) 4 X (mind х - 1) р + + х-Х-Х + Ху) -Хх + Хх х-Х, where X and (1 - X) are weighting factors obtained at the outputs of the DAC 6 in accordance with the numerical code X at its input. The claimed device uses the fact that the output number of the accumulating

adder 5. equal to the input code X of the DAC 6, is equal to the current phase error x, as a result of which at the output of the adder 11 we obtain a signal whose constant component characterizes the current phase mismatch and does not contain noise. This signal is applied to the input of the low-pass filter 1, which cuts the higher harmonics and determines the dynamic properties of the phase-locked loop (PLL). The filtered signal is controlled by a controlled oscillator 2, driving the frequency of the output signal in accordance with the frequency of the input signal and a given division ratio.

The fractional-proportional frequency converter allows to reduce the phase modulation of the output signal while expanding the frequency range of the input signals and expanding the range of variation of the conversion coefficient K. three times the input signal frequency). The correction circuit is equally operable at all frequencies beyond the noise band of the PLL loop; the exact operation of the correction circuit in the prototype is ensured only with a small phase shift between the two signals. This condition is only satisfied when the conversion coefficient K is available.

35

40

A Fractional-Proportional Frequency Converter comprising a low-pass filter and a controlled generator, a delay element, a controlled frequency divider, an accumulator, the clock input of which is connected to the output of the delay element, a digital-to-analog converter, the input of which is connected to the output of the accumulator adder - 4t. phase detector and adder, while the transfer output of the accumulating adder is connected to the control input of the controlled frequency divider, the output of which is connected to the information input of the delay element, the first input of the phase detector is the signal input of a fractional-proportional frequency converter, the output of the controlled generator connected to the clock inputs 55 of the delay element and the controlled frequency divider and is the output of a fractional proportional frequency converter, the digital inputs of the controlled del bodies of frequency and accumulating summatically large. If an 8-bit DAC is used, then in the prototype at K - 8 the accuracy of phase noise compensation

determined by the DAC and equal, 004 256

period of the output signal, at K - A the error is already 0.045 periods, and at K 2 the correction circuit generally ceases to work. In a fractional-proportional frequency converter, even at such small K, the correction circuit remains operational and, in accordance with the calculations, ensures high accuracy of phase compensation 1

noise

period of the output signal.

71 256

In addition, in the prototype, the phase detector compares the input signal and the signal passed through the second filter, which introduces an additional delay, depending on the frequency and filter parameters. As a result, the output signal receives an additional phase shift, depending on the frequency of the input signal. In this device, phase detectors are compared

Directly digital signals without pre-filtering. This ensures that the output signal is directly linked to the input signal and eliminates additional phase shift.

(56) Copyright certificate of the USSR N 1631721, cl. H 03 L 7/18. 1988.

5

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torus are respectively the input of the integer part of the frequency conversion coefficient and the input of the fractional part of the frequency conversion coefficient of the proportional-frequency converter, characterized in that, in order to reduce distortion of the output signal by reducing spurious phase modulation while expanding the frequency range of the input signals and expanding the range of variation frequency conversion coefficient, a second phase detector is introduced, the first input of which is connected to the first input of the first phase detector ora, the first and second controlled inverters, the signal inputs of which are connected respectively to the direct and inverse outputs of the digital-to-analog converter, while the control inputs of the first and second controlled inverters are connected to the outputs of the first and second phase detectors, the outputs of the first and second controlled inverters are connected to the corresponding inputs of the adder. the output of which is connected to the input of a low-pass filter, the second inputs of the first and second phase detectors are connected to the outputs of the delay element and the controlled frequency divider, respectively.

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