RU184381U1 - Dual-channel PWM with dual regulating effect on ramp slope - Google Patents

Abstract

The utility model relates to the field of electronics and can be applied in the development of secondary power sources (VIP).

The proposed scheme of a two-channel pulse-width modulator with a double regulating effect on the inclination of the sawtooth voltage differs from the prototype by a smaller number of logic elements (gates), higher reliability and lower power consumption.

All these positive qualities were achieved by introducing a pulse-width modulator RS flip-flop on two 2ILI-NE elements, a counting flip-flop performed on the D flip-flop triggered on the rising edge of the input signal (front 01), an electronic switch and two channel 3IL gates -NOT connected by new inter-element connections.

The introduced elements and inter-element communications allowed realizing the digital part of the pulse-width modulator circuit on OR-NOT elements of the same type, reducing the number of elements (gates, transistors) and thereby increasing reliability and reducing power consumption.

Description

The utility model relates to the field of electronics and can be applied in the development of secondary power sources (VIP). Pulse width modulator (PWM) in the composition of the VIP (secondary power source) is used as a device that generates pulse signals, the duration of which depends on both input (Uin) and output (Uout) voltages.

Known two-channel PWM (see Fig. 1) with a double regulating effect on the inclination of the sawtooth voltage (hereinafter abbreviated as saws), with fixing information about the switching of the threshold element on the R-S trigger, shown in the product: IHEP K275.010 module. ShUKR.436434.004.

Two-channel PWM contains the actual PWM performed on the elements indicated in FIG. 1 numbers 1-9 and a pulse distributor for two channels, performed on the elements designated by the numbers 10-12. The disadvantage of such a PWM circuit is that the pulse distributor in this circuit, performed on a counting trigger 10 and two 2ILI-NE 11 and 12 gates, which function as a two-channel decoder, operates on pulses of variable duration, coming from the output of the PWM itself (element 2I-NOT 9) to the counting input "C" of the counting trigger 10. When the VIP operates in idle mode and with the maximum input voltage, the input "C" of the counting trigger 10 from the output of the element 9 actually PWM pulses can be received, the duration of which is less than the duration tg pulse generated by the master oscillator. As a result, the trigger 10 may not work, due to too short a pulse, which will lead to failure of the VIP circuit. The closest in technical essence is the scheme of two-channel PWM given in the application for which a positive decision was received on issuing a patent for a useful model (application No. 201614421313/08 (070875) of November 10, 2016).

The PWM circuit from the application is shown in FIG. 2. PWM includes a timing circuit consisting of a resistor 1 and a capacitor 2, an electronic switch 3 with three pins: a control (U), “common” and “output”, an input gate 2И – НЕ 4, a feedback phototransistor 5, an inverter 6 , RS type trigger on two 2I-NE 7 and 8 valves, with the first output of resistor 1 connected to the positive terminal of the input power supply Uin, and its second output connected to the first capacitor plate 2, to the output of the electronic switch 3, the emitter of the phototransistor 5, (the collector of which is connected to the terminal plus the internal Power supply Evn.pit.) and to the input of the inverter 6, the output of which is connected to the input S of the RS flip-flop, and its R input is connected to the first input of the input valve 2I-HE 4, the second input of which is connected to the output of the valve 2I-HE8 trigger RS type, the output of the input valve 2I-NOT 4 is connected to the control input of the electronic switch 3, while the second plate of the capacitor 2 and the output "common" of the electronic switch 3 are combined and connected to the bus "common" input power source. In addition, the PWM circuit of the prototype also includes: counting trigger 9, performed on D trigger, triggered on the front edge of the input signal (front 10), and two channel gates 3I, 10 and 11. At the same time, the clock input “C” of the counting trigger 9 is connected to the first input of the input valve 2I-HE4 and to the first inputs of the channel valves 3I, 10 and 11, the second inputs of which are connected respectively to the direct and inverse outputs of the counting trigger 9, and the third inputs of the channel valves 3I, 10 and 11 are connected to the output of the valve 2I-HE 8 RS trigger, with the first input input 2I of the two-input gate - NOT 4 is a two-channel PWM input.

As can be seen from FIG. 2, the circuit operates from short (narrow) pulses with a log level. 0. constant duration.

Consider the operation of the prototype circuit, from the moment when a pulse signal with a log level is applied to the input of the 2I-NO 4 gate. 0 from the pulse generator. In this case, the following distribution of logical levels at the outputs of the 2I-NOT gate of the two-channel PWM circuit will take place.

The output of the valve 2I-NOT 4 will form a level log. 1, which will unlock the electronic key 3, and the capacitor 2 will begin to discharge through the low resistance of the public key 3. At the same time, the signal from the pulse generator will go to the R input of the R-S trigger on the 2I-HE 7, 8 valves, and set it to the log state. 1, i.e. the output of the valve 2I-NOT 8 will establish the level of the log. 1, and at the outlet of the valve 2-NOT 7 level log. 0. Level log. 1, acting on the inputs of the channel valves 3I 10 and 11, will form at their outputs the levels of the log. 0. That is, at the moment of the pulse coming from the generator, there will be a reliable ban on the transmission of information from the outputs of the counting trigger 9 to the gates of the power switches of the MOS transistors of the VIP converter, which is very important. This is the so-called guaranteed pause (perforation) or “dead” time in foreign literature. Simultaneously, the signal level log. 1 from the output of the 2I-NOT 8 valve goes to the second input of the 2I-NOT 4 valve, but it does not affect its operation at this time. Consider the process of operation of the circuit after the end of the pulse from the generator, i.e. when the input of the valve 2I-NOT 4 there is a level log. 1. In this case, the output of the valve 2I-NOT 4 will form the level of the log. 0, the electronic key 3 closes, and the charge of the capacitor 2 through the resistance 1 starts with a practically constant current. In this case, the output of the valve 8 will act level log. 1, and at the output of K1 or K2, i.e. only one of the two channel valves 3I 10 or 11, will form the level of the log. 1, which will be input to the gate of the MOS transistor of the VIP converter. When the voltage on the capacitor 2 reaches the switching threshold of the inverter 6, the level of the log will be formed at its output. 0, and the R-S trigger on the valves 2I-NOT 7, 8 is set in the inverse state, in which the output of the valve 2I-NOT 7 will have a level log. 1, and at the exit of the valve 2-NOT 8 - the level of the log. 0. The latter, acting on the inputs of the channel valves 3I 10 and 11, will form at their outputs K1 and K2 log levels. 0, thus completing the cycle of obtaining a working impulse. In this case, the signal with the level of the log. 0 from the output of the 2I-NE 8 valve will form a 4-level signal at the output of the valve. 1, which will open the electronic key 3, and allow the process of discharging the capacitor 2 through the low resistance of the public key 3. That is, the voltage on the capacitor 1 will never exceed the voltage equal to the switching threshold voltage of the inverter 6.

It is interesting to note that in this two-channel PWM scheme, in principle, the presence of narrow pulses is not observed on any of the inputs of both the counting trigger 9 and the inputs of the ZI, 10 and 11, which is extremely important. Indeed, the narrowest pulse at the input of the counting trigger 9 is a pulse with a duration equal to the duration of the pulse tг. And at the inputs of the ZI gates, 10 and 11 the shortest pulse (with the level of the log. 1) cannot have a duration less than the duration tг.

And that is purely theoretical, since practically the duration of the pulse with the level of the log. 1 here must always be longer than the duration of tg. This suggests that in this scheme, the fill factor is Kz (Kz = tish / (Tg / 2), where tish is the pulse duration at the output of any of the 3I, 10 or 11 elements formed by the PWM circuit, Tg is the repetition period of the pulses pulse generator) can vary almost from zero to the maximum value. Let the circuit work at maximum input voltage and at idle. In this case, taking into account the current through the phototransistor 4 and the current through the resistor 1, the capacitor 2 will be charged most quickly. And at the output of the 2I-HE8 valve, a signal is generated with a log level. 1 with a duration of td + Δt, where Δt <tg is the additive to the impulse of thi due to the fast charge of the capacitor 2. But the value of the additive At can be nanoseconds and therefore the ZI valves 10 and 11 can not miss them. In order for a signal to pass through a valve, its duration must be greater than the value determined by the average propagation delay. But such short duration pulses can hardly have any effect on the gates of the power MOS transistors, i.e. will not be able to set them in the on state (instead of the MOS transistor, they often use a MOS transistor).

So, since the PWM circuit shown in FIG. 2 counting trigger 9 operates from pulses with a log level. 0 of a constant duration equal to tг, then the probability of its failure due to non-response from a short pulse is excluded. Referring to the prototype circuit shown in FIG. 2, it can be seen that the digital part of this circuit is implemented on logical elements of not one functional type, i.e. it contains elements of NAND and elements I. This requires a logical series of a wider functional series, which can lead to complication of the PWM scheme in the absence of 3I elements in the selected series of integrated circuits.

Therefore, the purpose of the utility model is to simplify the prototype PWM circuit by performing its digital part on the same type of elements, reducing the number of logic elements (gates) and, as a result, increasing reliability and reducing power consumption.

This goal is achieved by the fact that the two-channel PWM circuit contains time-sensitive resistor 1 and capacitor 2, electronic switch 3 with three outputs: control “U”, “common” and “output”, feedback phototransistor 4, counting trigger 7, D trigger, while the first output of the resistor 1 is connected to the positive terminal of the input power source Uin, and its second output is connected to the first plate of the capacitor 2, to the output of the electronic switch 3, the output of which is “common” connected to the bus “common” input power source to The phototransistor 4 mitter, the collector of which is connected to the Evn.pit internal power supply bus, has been introduced: RS trigger on two 2IL-NOT 5 and 6 elements, two 3IL-NOT channel gates, 8 and 9, electronic switch 10, with the first lining the capacitor 2 is connected to the first input element 2ILI-NOT 6 RS trigger, and the clock input "C" of the counting trigger 7, triggered on the rising edge of the input signal (front 01), is connected to the control input "U" of the electronic switch 3, to the third valve inputs 3 OR-NO 8 and 9 and to the first input of element 2 OR-N 5 RS flip-flops, while the output of the 2ILI-HE element 5 RS of the trigger is connected to the first inputs of the 3ILI-HE 8, 9 gates and to the control input “Y” of the electronic key 10, the second inputs of the 3ILI-HE 8 and 9 elements are connected respectively to the direct and inverse outputs of the counting trigger 7, and the output of the “common” electronic key 10 is connected to the bus “common” input power source, while the control input “U” of the electronic key 3 is the input of a two-channel PWM. The PWM circuit is shown in FIG. Z. and works as follows.

Coming on the control input (input "U") of the key 3 impulse tgi (see Fig. 4. -diagram of signals at the outputs of the valves of the PWM circuit) with a logic level 1 (log. 1), simultaneously enters the input of element 5, input "C »Counting trigger 7 and two elements 3ИЛИ-НЕ 8 and 9. As a result, on the front of the input pulse (time t0 in Fig. 4) the counting trigger 7 will go to the inverse state, RS trigger to the state log. 0 (at the output of element 2IL-NOT 5 level log. 0, and at the output of element 2 OR-NOT 6 level log. 1), and at the outputs of elements ZILI-NO 8 and 9, the levels of log will act. 0, i.e. at the moment of the pulse tgi action, blocking (prohibition) of information transfer from the outputs of the counting trigger 7 to the inputs of the ZILI-NE elements 8 and 9 is performed. This blocking will be valid for the entire duration of the pulse tgi. After the termination of the pulse tg (moment t1 Ha of Fig. 4), the output of the 2IL-NOT 5 gate will remain a signal with a log level. 0, and at the exit of the valve 2 OR-NOT 6 - the level of the log. 1. As a result, only at the output of one of the two elements 3ILI, NOT 8 (Kn1) or 3ILI, NOT 9 (Kn2), a working signal with a log level will be formed. 1, which will then go to the gate of one of the power MOS transistors of the VIP converter. At the same time, at the end of the pulse tg, the time-charging capacitor 2 will start charging through the resistor 1 and capacitor 2 circuits with almost constant current. Consequently, the voltage on the capacitor 2 will increase according to a linear law, i.e. according to law

When capacitor 2 reaches voltage Uc2 (instant t2 in Fig. 4) equal to the response threshold of element 2ILI – NO 6 (Uc2 = Upor. element 2OR or NOT 6), R-S flip-flop on elements 2IL-HE 5 and 6 will be set to log. 0 (at the output of element 2IL-NOT 6 the level of the log. 0, and at the output of the element 2 OR-NOT 5 - the level of the logic. 1), and the formation of the pulse width of the PWM (third and highest) is completed. In this case, the signal with the level of the log. 1 from the output of the gate 2IL-HE5 enters the control input "Y" of the electronic key 10, and the capacitor 2 begins to discharge through the low resistance of the open electronic key 10. In other words, this means that the discharge of the capacitor 2 will begin before the next pulse, tg, t. e. as in the PWM prototype circuit. So, the scheme of the proposed PWM fully performs the functions of the prototype, since its counting trigger 7 is controlled by signals of constant duration equal to the duration generated by the generator i.e. the duration of the tag. It remains to compare them in terms of efficiency ie. according to the number of logic elements or, which is the same with the number of transistors in the case of realization of PWM in the form of a crystal during the implementation of the latter on complementary MOS transistors by conduction of n and p-types. Recall that the implementation of the inverter requires two MOS transistors (one transistor with n-type conductivity and one transistor with p-type conductivity), and 4 MOS transistors (two transistors with n-type conductivity and two transistors with p-type conductivity).

A comparison of the PWM circuit of the prototype performed on the NAND elements with the proposed PWM circuit shown in FIG. 3 by the number of elements shows that the last of these two circuits is implemented on a smaller number of elements with the same number of inputs or, which is the same in this case, on a smaller number of transistors. That is, it is more economical in the number of transistors and, therefore, consumes less power. In particular, the discharge circuit of the capacitor 2 in the PWM circuit shown in FIG. 3, is implemented on two transistors (meaning that the MOSFETs of n-type conductivity are used as electronic switches 3 and 10), whereas in the PWM circuit of the prototype shown in FIG. 2 for its implementation requires 5 transistors (two transistors with p-type conductivity and 2 transistors with n-type conductivity go to the construction of the element 2I-NOT and one transistor with n-type conductivity goes to build an electronic key). Moreover, in the proposed PWM circuit implemented on the OR-NO elements there is no inverter, and this is still minus two transistors in its favor. In addition, the digital part of the proposed PWM circuit is fully implemented on the same type of elements, namely, on the OR-NOT elements only, while the AND-NOT elements and the I.I. elements of the prototype PWM circuit use the number of transistors for its realization in the form of a crystal. In other words, the proposed PWM circuit shown in FIG. 3, more economical in terms of the number of elements (gates, transistors). Consequently, it has higher reliability, consumes less power, and can find wider application.

It should be noted that the efficiency in the number of transistors is a point that is especially important when implementing PWM in the form of a crystal, since LEs themselves are the source of interference in the crystal. But reducing the number of LEs will not only reduce internal noise, but also reduce heat generation inside the crystal. And, as a result, increase the service life of the elements (ie, increase reliability), because the elements operate in a more lightweight thermal mode.

Claims (1)

A two-channel pulse-width modulator containing a time-conducting resistor and a capacitor, an electronic switch with three pins: a control “U”, a “common” and “output”, a feedback phototransistor, a counting trigger made on the D trigger, the first output of the resistor connected to The positive terminal of the input power source Uin, and its second output is connected to the first capacitor plate, to the output of the electronic switch, the output of which is “common” connected to the bus “common” input power supply, to the emitter of the phototransistor, call The vector of which is connected to the Evn.pit internal power supply bus is introduced: RS trigger on two elements 2 OR NOT, two channel valves 3 OR NOT, electronic key, with the first capacitor plate connected to the first input of element 2 OR NOT RS trigger, and the clock input “C” of the counting trigger, triggered by the rising edge of the input signal (front 01), is connected to the control input “U” of the electronic key, to the third inputs of the 3 OR-NOT gates RS trigger, while the output element 2 OR NOT RS the trigger is connected to the first inputs of valves 3 OR-NOT and to the control input "U" of the electronic key, the second inputs of elements 3 OR-NOT are connected respectively to the forward and inverse outputs of the counting trigger, and the output of the "common" electronic key is connected to the bus "common" the input power source, while the control input "Y" of the electronic key is the input of a two-channel pulse-width modulator.