RU166651U1 - TRANSFORMER CONTROL IC - Google Patents

Abstract

A transformer control microcircuit containing a low-power generator with a reference frequency divider, a clocked clock drop, logic elements forming a delay between the antiphase outputs of the microcircuit, and two output high-power MOS transistors, characterized in that the logic elements are changed to 2I-NOT elements, the circuit is introduced the second reference frequency divider, clocked in antiphase by the front of the clock pulse, with the switching of logic elements 2I-NOT, forming a delay between antiphase outputs, equal to d the pulse frequency of the reference frequency signal, and the inverse outputs of the reference frequency dividers are connected to one 2I-NOT logical element, the direct outputs of the reference frequency dividers are connected to another 2I-NOT element, while the signals from which through the inverters provide sequential opening of the output transistors with the specified time delay .

Description

TRANSFORMER CONTROL IC

The transformer control microcircuit relates to a pulse technique and can be used as a high-frequency driver of out-of-phase pulses for an inductive load, in particular a transformer of a DC-DC converter.

Known chips MAX253 (1994 Maxim Integrated Products, www.maxim-ic.com) and MAX845 (1997 Maxim Integrated Products, www.maxirn-ic.com) containing an economical integrated oscillator with a large duty cycle of the reference frequency, the division of which by counting trigger provides inverse signals at the outputs of the trigger. These signals connected to the gates of n-MOS transistors provide control of the transformer of the DC-DC converter with out-of-phase signals.

The disadvantage of these microcircuits is the coincidence in time of the front and the fall of antiphase signals, which at the moment of this coincidence leads to the passage of through current through the transformer and the release of stray power.

As a prototype, the transformer driver microcircuit was selected (RU 160154 U1 IPC H03K 3/00, published March 10, 2016), shown in FIG. 1 and containing a low-power generator, a reference frequency divider, and logic elements forming a delay between the out-of-phase outputs equal to the pulse width of the reference frequency signal.

The main disadvantage of the prototype is the low noise immunity at high frequencies, with values of the pulse width close to the propagation delays of the functional elements. A functional diagram of the prototype, taking into account the time delays of the functional elements, is shown in FIG. 2. In fact, time delays on the counting triggers lead to the fact that the delay signal does not fall between the antiphase outputs.

The utility model is aimed at obtaining a technical result — providing an interference-resistant delay of the on-time between antiphase outputs at high frequencies.

This goal is achieved by the fact that in the transformer driver microcircuit containing a low-power generator with a reference frequency divider, a clocked clock drop, the logic elements that form the delay between the antiphase outputs of the microcircuit, and two powerful output MOS transistors, the logic elements are changed to 2I-NOT elements, the circuit introduced a second reference frequency divider, clocked in antiphase by the front of the clock pulse, with the switching of logic elements 2I-NOT, forming a delay between antiphase outputs equal to the pulse width of the reference frequency signal, and the inverse outputs of the reference frequency dividers are connected to one 2I-NOT logic element, the direct outputs of the reference frequency dividers are connected to another 2I-NOT element, while the signals from which through the inverters provide sequential opening with the specified time delayed output transistors.

In FIG. 1 is a structural diagram of a transformer control chip. Timing diagrams of the signals of the transformer control chip are shown in FIG. 2.

The transformer control chip operates as follows. The signal from the generator of FIG. 1 is fed to the inverting logic elements DD1 (Schmidt trigger) and DD2 (inverter), which form antiphase signals for controlling counting triggers DD3 and DD4 connected to the clock signal in antiphase. At the output of DD3, a signal with a frequency divided by 2 relative to the reference frequency is formed by a clock signal drop; at the output DD4, a signal with a frequency divided by 2 relative to the reference frequency is also formed at the edge of the clock signal (shown in Fig. 2).

Sequentially to the triggers DD3, DD4 in FIG. 1, triggers DD5, DD6, DD8 and DD7, DD9, DD14 are included, respectively, which also successively divide the frequency by 2, as shown in FIG. 2.

The outputs DD8 and DD14 generate signals divided by 16 relative to the clock frequency and shifted relative to each other by the time duration of the clock pulse, which is reflected in FIG. 2.

The signals from the direct outputs of the triggers DD8 and DD14 are received in accordance with FIG. 1 to the element DD10, performing the function 2I-NOT; signals from the inverse outputs of the triggers DD8 and DD14 - to the element DD11 (2I-NOT). The output signals from DD10 and DD11 are supplied to the inverters DD12 and DD13, respectively. The signals from outputs DD12 and DD13 are shown in FIG. 2. The signals are in antiphase, but at the same time, when changing phases between the signals, there is a time interval equal to the pulse width of the reference frequency signal.

In fact, it turns out that the output transistors of the control transformer VT1 and VT2 open sequentially, but with a delay, which eliminates the passage of through current in the transformer.

The technical result is achieved due to the formation of a delay between the antiphase outputs, equal to the pulse width of the signal of the reference frequency, using two dividers of the reference frequency, clocked separately by the decay and the front of the clock signal.

Claims (1)

A transformer control microcircuit containing a low-power generator with a reference frequency divider, a clocked clock drop, logic elements forming a delay between the antiphase outputs of the microcircuit, and two output high-power MOS transistors, characterized in that the logic elements are changed to 2I-NOT elements, the circuit is introduced the second reference frequency divider, clocked in antiphase by the front of the clock pulse, with the switching of logic elements 2I-NOT, forming a delay between antiphase outputs, equal to d the pulse frequency of the reference frequency signal, and the inverse outputs of the reference frequency dividers are connected to one 2I-NOT logical element, the direct outputs of the reference frequency dividers are connected to another 2I-NOT element, while the signals from which through the inverters provide sequential opening of the output transistors with the specified time delay .

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