RU2549136C1 - Push-pull shift register - Google Patents

Abstract

FIELD: electricity.

SUBSTANCE: push-pull shift register consists of cells, each of them containing a trigger based on the left and right switching MOS-transistors and the left and right load MOS-transistors, the left and right input MOS-transistors, a stabilising MOS-transistor, a latching MOS-transistor, a MOS-transistor used as a delay element, two SCLs, a power supply bus, a zero potential bus and their connections, at that an auxiliary MOS-transistor, the third SCL and their connections are introduced into each cell additionally.

EFFECT: providing potential reversible data shift inside the push-pull shift register and bidirectional data transmission and stable operation of the push-pull shift register in conditions of essential parasitic capacitance of SCLs.

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Description

The invention relates to optoelectronics and microelectronics and can be used to build push-pull shift registers in photodetector submodules for mosaic photodetectors, in particular in photodetectors on microbolometers.

Known shift register (RF patent for the invention No. 2344498, IPC G11C 19/00, H03K 3/037, H03K 9/001, published January 20, 2009), which is performed on RS-triggers and AND and OR elements, containing each category, the first and second RS-flip-flops, four logical AND elements, one OR element, an information input, the first and second control buses for receiving the code in the first and second triggers when performing the code shift operation, an information output, while the outputs of the first and third AND elements connected to the R-inputs of the first and second RS-triggers, respectively, the output of the second element And AND is connected to the first input of the first OR element, the second input of which is connected to the information input, and the output of the said OR element is connected to the S-input of the first trigger, the first inputs of the first and second elements AND are connected to the first bus for controlling the reception of the code in the first trigger, the first the inputs of the third and fourth elements And are connected to the second bus for controlling the reception of the code in the second trigger, and the zero and single outputs of the first trigger of the i-th category are connected to the second inputs of the third and fourth elements of the I (i + 1) -th discharge Accordingly, the zero and single outputs of the second trigger of the i-th category are connected to the second inputs of the first and second elements of the (i + 1) -th category, respectively, in addition, the first and second inputs of the second OR element are connected to the S-inputs of the first and second triggers , the output of the said OR element is the information output of the i-th category, etc.

The disadvantage of this shift register is that it has a complex structure and control, consists of a large number of transistors and, as a result, when used as a vertical addressing block in mosaic photodetectors, it leads to a decrease in the image conversion efficiency in the mosaic photodetector as a whole. (Image conversion efficiency is the ratio of the number of working photosensitive elements (PSEs) in the mosaic photodetector to the sum of the PSEs lost in the “blind zones” and working in the mosaic photodetector.)

Known reverse shift register (RF patent for the invention No. 2022372, IPC G11C 19/00, publ. 10/30/1994), the essence of which is that it contains in each category JK-trigger, four elements And, in each category except for the first and last, four OR elements, in the first and last digits - three OR elements, left and right shift direction control buses, register reset input, shift input, register direct and inverse information inputs and information in a direct sequential code during shift right, direct and inverse information Paraphase register inputs and information output in a direct sequential code when shifting to the left, shift mode control input — multiplex units, and shift mode control input — multiplex zeros, and the direct output of the JK trigger of each category, except the last, is connected respectively to the first input of the first element And the subsequent discharge, and the direct output of the JK trigger of each discharge, except for the first, is connected respectively to the first input of the second element AND of the previous discharge, the outputs of the first and second elements And of each discharge with are the same as the inputs of the first OR element, the input of which is connected to the J-input of the JK trigger of this category, the second inputs of the first and second elements AND of all bits are respectively inputs for controlling the shift to the right and left shift of the register, etc. The introduction into the well-known shift register in each category, except the first and last, two OR elements (fifth and sixth), in the first cell of the fifth OR element, in the last cell of the sixth OR element, as well as new relationships, allows expanding the functionality of the reverse shift register due to seals zeros of the code combination both to the left and to the right of the register.

The disadvantage of this reverse shift register, as well as the previous one, is that it has a complex structure and control, consists of a large number of transistors and, as a result, when used as a vertical addressing block in mosaic photodetectors, it leads to a decrease in the efficiency of image conversion in a mosaic photodetector in whole.

The shift register for MOS transistors is known (copyright certificate No. 1269210, IPC G11C 19/00, publ. 11/07/1986), in which the output of each of the inverters making up the register is connected through switching transistors to the inputs of the subsequent and previous inverters. In this case, during the first cycle of the shift register, triggers are formed consisting of even and subsequent odd inverters, and during the second cycle of operation - from the even and previous odd inverters.

The disadvantage of this shift register on MOS transistors is that it requires a large number of clock buses for control signals and a complex diagram of control signals, which complicates its manufacturing technology, reduces performance, increases the cost of the device and significantly reduces the efficiency of the mosaic photodetector as a whole.

Also known is the push-pull shift register on MOS transistors, adopted for the prototype shown in the copyright certificate No. 736172, IPC G11C 19/00, publ. 05/25/1980

The push-pull shift register consists of cells, each of which contains a trigger made on the left and right switching and on the left and right load MOS transistors, the left and right input MOS transistors, the stabilizing MOS transistor, the key MOS transistor, the MOS transistor as a delay element, two clock buses, a power bus and a bus of zero potential, moreover, in each cell the drain of the key MOS transistor is the input to the cell, and in the first cell of the push-pull shift register is, at the same time, the first When reading information from the left-right push-pull shift register, the gate of the key MOS transistor is connected to the first clock bus, and its source is connected to the gate of the left input MOS transistor, the drain of which is connected to the drain of the left switching, with the gate of the right switching and to the source left load MOS transistors; drains and gates of the left and right load MOSFETs are connected to the power bus, the sources of the left and right switching MOSFETs are connected to the bus of zero potential; the source of the left input MOS transistor is connected to the source of the right input and to the drain of stabilizing MOS transistors, the source of the latter is connected to the zero potential bus, and its gate is connected to the source of the MOS transistor, which forms a delay element, the gate of which is connected to the power bus, and its drain - with the gate of the right input MOS transistor and with a second clock bus; the drain of the right input MOSFET is connected to the drain of the right switching, with the gate of the left switching and with the source of the right load MOS transistor, this connection is the output of the cell, and in the last cell of the push-pull shift register is also the first information output of the push-pull shift register when reading information from left to right.

This push-pull shift register, adopted as a prototype, was created on the basis of a more economical circuit and does not require an increased amplitude of clock signals in comparison with well-known analogues.

However, it has significant drawbacks, namely, it shifts information in only one direction and the stray capacitance of its clock buses significantly affect the operation of the push-pull shift register.

The technical result of the invention is:

- expansion of functionality by providing reversibility of the shift of information inside the push-pull shift register,

- minimization of the occupied area of the crystal IP,

- expanding the scope due to the possibility of bi-directional transmission of information and the stable operation of the push-pull shift register in conditions of significant parasitic capacitances of clock buses.

The technical result of the invention is achieved by the fact that in the push-pull shift register, consisting of cells, each of which contains a trigger made on the left and right switching and on the left and right load MOS transistors, the left and right input MOS transistors, stabilizing the MOS transistor , a key MOS transistor, a MOS transistor as a delay element, two clock buses, a power bus and a zero potential bus, and in each cell the drain of the key MOS transistor is an input to the cell, and in the first cell there are two the clock shift register is, at the same time, the first information input of the push-pull shift register when reading information from left to right, the gate of the key MOS transistor is connected to the first clock bus, and its source is connected to the gate of the left input MOS transistor, the drain of which is connected to the drain of the left switching , with the gate of the right switching and with the source of the left load MOS transistors, the drains and gates of the left and right load MOS transistors are connected to the power bus; the sources of the left and right switching MOSFETs are connected to the zero potential bus, the source of the left input MOSFET is connected to the source of the right input and to the drain of the stabilizing MOSFETs, the source of the latter is connected to the zero potential bus, and its gate is connected to the source of the MOS transistor forming a delay element, the gate of which is connected to the power bus, and its drain is connected to the gate of the right input MOS transistor and to the second clock bus, the drain of the right input MOS transistor is connected to the drain of the right switch This, with the gate of the left switching and with the source of the right load MOS transistors, this connection is the output of the cell, and in the last cell of the push-pull shift register is, at the same time, the first information output of the push-pull shift register when reading information from left to right, an additional The MOS transistor and the third clock bus, and the gate of the additional MOS transistor is connected to it, the source of which is connected to the gate of the left input MOS transistor, and the drain is connected to the output the house of the next cell is the second input of the cell, in the last cell of the push-pull shift register it is, at the same time, the second information input of the push-pull shift register for reading information from right to left, the output of the first cell of the push-pull shift register is, at the same time, the second information output of the push-pull shift register when reading information from right to left.

The proposed push-pull shift register due to the introduction of an additional MOS transistor, a third clock bus and additional links into each of its cells provides the ability to shift information inside the push-pull shift register in the forward and reverse directions (from left to right and from right to left) and the ability to minimize cell size, as well as expanding the scope due to the possibility of bi-directional transmission of information and stable operation of the push-pull shift register in conditions of significant spurious e ikost of clock tires.

The invention is illustrated by the following description and the accompanying drawings.

In FIG. 1 is a functional diagram of a push-pull shift register; FIG. Figure 2 shows the timing diagrams of the operation of a push-pull shift register when performing an operation of shifting information from left to right and from right to left.

In FIG. 1 is a functional diagram of a push-pull shift register, where 1 is a cell, 2, 3 are left and right trigger MOSFETs of a trigger; 4, 5 - left and right load MOSFETs of the trigger; 6, 7 - left and right input MOS transistors; 8 - stabilizing MOS transistor; 9 - key MOS transistor; 10 - MOS transistor forming a delay element; 11 - additional MOS transistor; 12 - the first input of the cell, 13 - the second input of the cell; 14 - cell output; 15 - the first information input of the push-pull shift register; 16 - the second information input of the push-pull shift register; 17 - the first information output of the push-pull shift register; 18 - the second information output of the push-pull shift register; 19 is the first clock bus, 20 is the second clock bus, 21 is the third clock bus, 22 is the power bus, 23 is the zero potential bus.

The push-pull shift register is organized as follows (Fig. 1). In each cell 1, the drain of the MOS transistor 9 is the first input 12 of the cell, and in the first cell of the push-pull shift register it is, at the same time, the first information input of the push-pull shift register 15 when performing the information shift operation from left to right. The gate of the key MOSFET 9 is connected to the first clock bus 19, and its source is the gate of the left input 6 and the source of the additional 11 MOS transistors. The drain of the left input MOSFET 6 is connected to the drain of the left switching 2, the gate of the right switching 3 and the source of the left load 4 MOS transistors, the drain and gate of which are connected to the power bus 22. The sources of the left 2 and right 3 switching MOSFETs are connected to bus zero potential 23. The source of the left input MOS transistor 6 is connected to the source of the right input 7 and with the drain stabilizing 8 MOS transistors. The gate of the right input MOS transistor 7 is connected to the drain of the MOS transistor 10, which forms the delay element, and to the second clock bus 20. The drain of the right input MOS transistor 7 is connected to the drain of the right switching MOSFET 3, with the gate of the left switching 2 and with the source of the right load 5 MOSFETs. This connection is the output of the 14 cell, the output of the first cell of the push-pull shift register is, at the same time, the second information output 18 of the push-pull shift register when performing the operation of shifting information from right to left, and the output of the last cell of the push-pull shift register is, at the same time, the first information output 17 of the push-pull shift register when performing the operation of shifting information from left to right. The drain and gate of the right MOSFET 5 are connected to the power bus 22. The source of the stabilizing MOS transistor 8 is connected to the zero potential bus 23, and its gate is connected to the source of the MOS transistor 10, which forms a delay element, the gate of which is connected to the power bus 22 The gate of the additional MOS transistor 11 is connected to the third clock bus 21, its drain is connected to the output of the next cell and is the second input 13 of the cell, and in the last cell of the push-pull shift register, it is also the second information input th shift register 16 two-stroke.

In FIG. 2a, a time diagram of the operation of a push-pull shift register during the operation of shifting information from left to right is shown, where

24 - signal at the first information input 15 push-pull shift register,

25, 26 - signals on the first 19 and second 20 clock buses, respectively,

27, 28 - signals at the outputs 14 of the first and second cells of the push-pull shift register, respectively.

Figure 2, b shows the timing diagram of the push-pull shift register when performing the operation of shifting information from right to left, where

29 is a signal at the second information input 16 of a push-pull shift register,

30, 31 - signals on the third 21 and second 20 clock buses, respectively;

32, 33 - signals at the outputs 14 of the penultimate and last cells of the push-pull shift register, respectively.

Consider the operation of a push-pull shift register.

The push-pull shift register (Fig. 1) works as follows when performing the operation of shifting information in the form of a logical unit “1” or a logical zero “0” to the right (reading information from left to right, Fig. 2, a).

The input signal 24 from the first information input 15 of the push-pull shift register and, simultaneously, from the first input 12 of the first cell 1 is fed through the key MOS transistor 9 to the gate of the left input MOS transistor 6. The first clock signal 25 is supplied via the first clock bus 19 to the gate the key MOS transistor 9, the second clock signal 26 through the second clock bus 20 to the gate of the right input MOS transistor 7 and through the delay element (MOS transistor 10) to the gate of the stabilizing 8 MOS transistor. The output signal from the output of cell 14 is removed from the right trigger inverter, assembled on the right switching 3 and the right load 5 MOS transistors.

The recorded information is stored in the cells of the push-pull shift register until the pulses of the clock signals 25 and 26, which have a logic level of “1”, are received on the gate circuit capacitance of the left input MOS transistor 6. The information is shifted by the pulses of two clock signals 25 and 26, which are received via buses 19 and 20, respectively. The information is taken in the intervals between the clock pulses of the signal 26 received on the bus 20.

In the absence of clock pulses, key 9, stabilizing 8 and right input 7 MOS transistors are locked. The first clock pulse of the signal 25 on the first clock bus 19 opens the key MOS transistor 9 for a time sufficient to charge or discharge the gate circuit capacitance of the left input MOS transistor 6 to a level close to the level of the input signal at input 15. Subsequently, the left gate voltage the input MOSFET 6 varies with a time constant, which for MOSFETs is several hundred microseconds or more. The interval between the clock pulses of the signals 25 and 26, arriving on the first 19 and second 20 clock buses, and the duration of the clock pulse of the signal 26 are chosen small enough so that by the time the signal 26 is removed, this level has not had time to change significantly. Since before applying the clock pulse of the signal 26, incoming via the second clock bus 20, the stabilizing 8 and the right input 7 MOS transistors are closed, the left input MOS transistor 6 does not affect the state of the trigger.

The clock pulse of the signal 26, arriving on the second clock bus 20, opens the right input 7 and stabilizes 8 MOS transistors, as a result of which output level 14 is set to “0”, and the left switching MOS transistor 2 is closed.

If the input signal level 24 is close to the voltage of the zero potential bus 23, i.e. has a logic level of “0”, then the closed left input MOS transistor 6 does not affect the state of the trigger even after opening the right input 7 and stabilizing 8 MOS transistors. After the end of pulse 26 on the bus 20 in the trigger will be recorded "0".

If the input signal level 24 is close to the voltage of the power bus 22, i.e. has a logic level of “1”, then the left input MOSFET 6 will be open. Therefore, when the clock pulse of signal 26 on the second clock bus 20 opens the right input 7 and stabilizing 8 MOS transistors, the level “0” is set not only at output 14, but also at the drain of the left switching MOS transistor 2, and the right switching MOS transistor transistor 3 is closed.

To write “1” to the trigger, it is necessary that the current in the circuit of MOSFETs 4-6-8 exist for some time after the disappearance of current in the circuit of MOSFETs 5-7-8. This ensures that the left MOS transistor 2 is opened when the right MOS transistor 3 is locked. At the end of the clock pulse of the signal 26 received via the second clock bus 20, the right input MOS transistor 7 closes earlier than the stabilizing MOS transistor 8 (signal 27 , Fig. 2, a).

The required sequence of closing the right input 7 and stabilizing 8 MOS transistors during the action of the trailing edge of the clock pulse of the signal 26 coming through the second clock bus 20 can be achieved in two ways. The increase in the threshold voltage of the right input MOS transistor 7 in comparison with the stabilizing MOS transistor 8 provides the required sequence of closing these transistors during the action of the trailing edge of the clock pulse 26. The same effect can be achieved if the clock pulse of the signal 26 from the shutter of the right input MOS the transistor 7 to the gate of the stabilizing MOS transistor 8 through the delay element, for example through a constantly open MOS transistor 10, forming an integrated circuit together with it awn stabilizing circuit gate MOSFET 8.

Since in the circuit of the push-pull shift register the output signal of the trigger of each cell serves as the input signal of the subsequent one, and the buses of the same name clock signals are combined, the logical “1” from the output 14 of the first cell will simultaneously be at the input 12 of the second cell of the push-pull shift register. The above operations will be repeated, and the signal 28 will appear at the output 14 of the second cell (signal 28, Fig. 2, a), and after all the cells of the push-pull shift register have passed through the first information output 17 of the push-pull shift register, the signal that was input from the first information input will appear 15 push-pull shift register.

The push-pull shift register (Fig. 1) works as follows when performing the operation of shifting information in the form of a logical unit “1” or a logical zero “0” to the left (reading information from right to left, Fig. 2, b).

The input signal 29 from the second information input 16 of the push-pull shift register and, simultaneously, from the input 13 of the last cell 1 of the push-pull shift register is fed through an additional MOS transistor 11 to the gate of the left input MOS transistor 6 of the last cell of the push-pull shift register. The first pulse of the clock signal 30 is supplied via the third clock bus 21 to the gate of the additional MOS transistor 11. Then, the pulse of the clock signal 31 fed through the second clock bus 20 is supplied to the gate of the right input MOS transistor 7 and through the delay element (MOS transistor 10 ) to the gate of the stabilizing MOS transistor 8. The output signal 33 (signal 33, Fig.2, b) from the output 14 is removed from the right inverter of the trigger, assembled on the right switching 3 and right load 5 MOS transistors of the last cell of the push-pull shift register pa, and fed to the second input 13 of the penultimate cell push-pull shift register. Then, signal 32 is removed from output 14 of the penultimate cell of the push-pull shift register (signal 32, FIG. 2, b).

When shifting information in the form of a logical unit “1” or logical zero “0” to the left, the push-pull shift register works similarly to the above shift of information to the right, except that an additional MOS transistor 11 and a third clock bus 21 are used instead in the key MOS transistor 9 and the first clock bus 19.

After all the cells of the push-pull shift register have passed through the second information output 18 of the push-pull shift register, a signal will appear that was input from the second information input 16 of the push-pull shift register.

Claims (1)

A push-pull shift register consisting of cells, each of which contains a trigger made on the left and right switching and left and right load MOS transistors, left and right input MOS transistors, stabilizing MOS transistor, key MOS transistor, MOS transistor as a delay element, two clock buses, a power bus and a bus of zero potential, and in each cell the drain of the key MOS transistor is the input to the cell, and in the first cell of the push-pull shift register it is, at the same time, the first when reading information from the push-pull shift register when reading information from left to right, the gate of the key MOS transistor is connected to the first clock bus, and its source is connected to the gate of the left input MOS transistor, the drain of which is connected to the drain of the left switching, with the gate of the right switching and to the source of the left MOSFETs, the drain and gate of the left and right MOSFETs are connected to the power bus, the sources of the left and right switching MOSFETs are connected to the zero potential bus Alas, the source of the left input MOS transistor is connected to the source of the right input and to the drain of stabilizing MOS transistors, the source of the latter is connected to the zero potential bus, and its gate is connected to the source of the MOS transistor, which forms a delay element, the gate of which is connected to the power bus, and its drain - with the gate of the right input MOS transistor and with the second clock bus, the drain of the right input MOS transistor is connected to the drain of the right switching, with the gate of the left switching, with the source of the right load MOS transistor, and this connection is the output of the cell, and in the last cell of the push-pull shift register is, at the same time, the first information output of the push-pull shift register when reading information from left to right, characterized in that an additional MOS transistor and a third clock bus are introduced into each cell the gate of the additional MOS transistor is connected to it, the source of which is connected to the gate of the left input MOS transistor, and the drain is connected to the output of the next cell, and is the second input of the cell, and in the last cell of the push-pull shift register, it is, at the same time, the second information input of the push-pull shift register, the output of the first cell of the push-pull shift register is, at the same time, the second information output of the push-pull shift register when reading information from right to left.

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