RU184381U9 - Two-channel PWM with double regulating effect on ramp voltage slope - Google Patents

Abstract

The utility model relates to the field of electronics and can be used in the development of secondary power sources (VIP).

The proposed scheme of a two-channel pulse-width modulator with a double regulatory effect on the slope of the sawtooth voltage differs from the prototype in the smaller number of logic elements (gates), higher reliability and lower power consumption.

All these positive qualities were achieved due to the introduction of a pulse-width modulator RS trigger on two 2OR-NOT elements, a counting trigger executed on a D trigger, triggering along the rising edge of the input signal (front 01), an electronic key and two 3-OR channel gates -NOT connected by new interelement bonds.

The introduced elements and inter-element communications made it possible to implement the digital part of the pulse-width modulator circuit on the same elements OR-NOT, to reduce the number of elements (valves, transistors) and thereby increase reliability and reduce power consumption.

Description

The utility model relates to the field of electronics and can be used in the development of secondary power sources (VIP). A pulse-width modulator (PWM) as part of a VIP (secondary power supply) is used as a device that generates pulse signals, the duration of which depends on both input (Uin) and output (Uout) voltages.

Known two-channel PWM (see Fig. 1) with a double regulatory effect on the slope of the sawtooth voltage (hereinafter abbreviated saws), with fixing information about switching the threshold element on the R-S trigger, shown in the product: IVEP K275.010СФ module. ShUKR. 436434.004.

The two-channel PWM contains the PWM proper, made on the elements indicated in FIG. 1 in numbers 1-9 and a pulse distributor for two channels, made on the elements indicated by numbers 10-12. The disadvantage of such a PWM circuit is that the pulse distributor in this circuit, made on a counting trigger 10 and two 2IL-NOT 11 and 12 gates, performing the function of a two-channel decoder, operates from pulses of variable duration coming from the output of the PWM proper (element 2I-NOT 9) to the counting input "C" of the counting trigger 10. When the VIP is idling and at the maximum input voltage, the input "C" of the counting trigger 10 from the output of element 9 of the PWM proper can receive pulses whose duration is shorter than the duration pulse tgi generated by the master oscillator. As a result, trigger 10 may not work, due to too short a pulse, which will lead to a failure of the VIP circuit. The closest in technical essence is the dual-channel PWM scheme given in the application, for which a positive decision was obtained on the grant of a patent for a utility model (application No. 201614421313 08 (070875) dated 10.11.2016).

The PWM scheme of the application is shown in FIG. 2. The PWM includes a timing circuit consisting of a resistor 1 and a capacitor 2, an electronic switch 3 with three outputs: control (U), "common" and "output", input gate 2I-NOT 4, feedback phototransistor 5, inverter 6 , RS type trigger on two gates 2I-NOT 7 and 8, while the first output of the resistor 1 is connected to the positive terminal of the input power source Uin, and its second output is connected to the first lining of the capacitor 2, to the output of the electronic key 3, to the emitter of the phototransistor 5, (whose collector is connected to the terminal plus the internal power supply source) and to the input of the inverter 6, the output of which is connected to the input S of the RS type trigger, and its R input is connected to the first input of the input valve 2I-NOT 4, the second input of which is connected to the output of the valve 2I-NOT8 of the RS trigger type, the output of the input gate 2I-NOT 4 is connected to the control input of the electronic key 3, while the second lining of the capacitor 2 and the output of the "common" electronic key 3 are combined and connected to the bus "common" input power source. In addition, the prototype PWM circuit also includes: counting trigger 9, executed on the D trigger, triggering along the falling edge of the input signal (front 10) and two channel gates 3I, 10 and 11. In this case, the clock input “C” of the counting trigger 9 is connected to the first input of the input gate 2I-NE4 and to the first inputs of the channel gates 3I, 10i 11, the second inputs of which are connected respectively to the direct and inverse outputs of the counting trigger 9, and the third inputs of the channel gates 3I, 10 and 11 are connected to the output of the 2I-NOT 8 RS flip-flops, with the first input being input 2I of the two-input gate - NOT 4 is a two-channel PWM input.

As can be seen from FIG. 2, the circuit operates from short (narrow) pulses with duration tg with log level. 0. constant duration.

Consider the operation of the prototype circuit, from the moment when a pulse signal with a log level is applied to the input of the 2I-NOT 4 valve. 0 from the pulse generator. In this case, there will be the following distribution of logic levels at the outputs of the 2I-NOT gates of the two-channel PWM circuit.

At the output of the valve 2I-NOT 4, a log level is formed. 1, which will lead to the unlocking of the electronic key 3, and the discharge of the capacitor 2 through the low resistance of the public key 3 will begin. At the same time, the signal from the pulse generator will go to the R input of the R-S trigger on the valves 2I-NOT 7, 8, and set it to the state log. 1, i.e. at the output of the 2I-NOT 8 valve, the log level will be set. 1, and at the output of the valve 2I-NOT 7 level log. 0. The level of the log. 1, arriving at the inputs of channel gates 3I 10 and 11, will form a log level at their outputs. 0. That is, at the moment of the pulse coming from the generator, there will be a reliable ban on the transfer of information from the outputs of the counting trigger 9 to the gates of the power keys of the MOS transistors of the VIP converter, which is very important. This is the so-called guaranteed pause (cut-out) or "dead" time in foreign literature. At the same time, a signal with a log level. 1 from the output of the valve 2I-NOT 8 goes to the second input of the valve 2I-NOT 4, but at the moment it does not affect its operation. Consider the process of the circuit after the end of the pulse from the generator, i.e. when at the input of the valve 2I-NOT 4 there is a log level. 1. In this case, a log level is formed at the output of the 2I-NOT 4 valve. 0, the electronic switch 3 closes, and the charge of the capacitor 2 begins through the resistance 1 with almost constant current. In this case, at the output of gate 8, the log level will act. 1, and at the output K1 or K2, i.e. only on one of the two channel valves 3I 10 or 11, will the level log be formed. 1, which will go to the gate input of the MOS transistor of the VIP converter. When the voltage across the capacitor 2 reaches the switching threshold of the inverter 6, a log level will be formed at its output. 0, and the R-S trigger on the 2I-NOT 7, 8 valves will be set to the inverse state, at which the log level will act on the output of the 2I-NOT 7 valve. 1, and at the output of the valve 2I-NOT 8 - level log. 0. The latter, entering the inputs of the channel gates 3I 10 and 11, will form the log levels at their outputs K1 and K2. 0, thereby completing the cycle of obtaining the working impulse. In this case, the signal level log. 0 from the output of gate 2I-NOT 8 will form a signal with a log level at the output of gate 4. 1, which will open the electronic key 3, and enable the discharge process of the capacitor 2 through the low resistance of the public key 3. That is, the voltage on the capacitor 1 will never exceed the voltage equal to the voltage of the switching threshold of the inverter 6.

It is interesting to note that in this two-channel PWM circuit, in principle, the presence of narrow pulses is not observed at any of the inputs, either the counting trigger 9, or at the inputs of the ZI, 10, and 11 gates, which is extremely important. Indeed, the narrowest pulse at the input of the counting trigger 9 is a pulse with a duration equal to the pulse duration tg. And at the inputs of gates ZI, 10 and 11, the shortest pulse (with a log level of 1) cannot have a duration shorter than the duration tg.

And that is purely theoretical, since in practice the pulse duration with the level of the log. 1 here always must be longer than the duration of tg. This suggests that in this scheme the duty cycle is Kz (Kz = tish / (Tg / 2), where t is the pulse width at the output of any of the elements 3I, 10 or 11, formed by the PWM circuit, Tg is the repetition period of the pulses tg generated pulse generator) can vary from almost zero to a maximum value. Let the circuit operate at maximum input voltage and in idle mode. In this case, taking into account the current through the phototransistor 4 and the current through the resistor 1, the capacitor 2 will be charged most quickly. And at the output of the 2I-NOT8 valve, a signal with a log level will be formed. 1 with the duration tgi + Δt, where Δt <tgi - additives to the pulse tgi due to the fast charge of the capacitor 2. But the value of the additive At can be nanoseconds and, therefore, the valves ZI, 10 and 11 may not let them through. For the signal to pass through the gate, its duration must be greater than the value determined by the average propagation delay. But such short pulses in duration will practically not be able to exert any effect on the gates of power MOS transistors, i.e. they will not be able to set them to the on state (instead of the designation, a MOS transistor is often used an MOS transistor).

So, since in the PWM circuit shown in FIG. 2 counting trigger 9 operates from pulses with a log level. 0 of constant duration equal to tgi, then the probability of its failure due to non-operation from a short pulse is excluded, Turning to the prototype circuit shown in FIG. 2, it can be seen that the digital part of this circuit is made on logical elements of more than one functional type, i.e. it contains AND-NOT elements and I. elements in its composition. This requires a wider functional series from the logical series, which can lead to complication of the PWM circuit if there are no 3I elements in the selected series of integrated circuits (IC).

Therefore, the purpose of the utility model is to simplify the PWM circuit of the prototype by performing its digital part on the same type of elements, reducing the number of logic elements (gates) and, as a result, increasing reliability and reducing power consumption.

This goal is achieved by the fact that in the circuit of a two-channel PWM, containing a timing resistor 1 and a capacitor 2, an electronic switch 3 with three outputs: control "U", "common" and "output", feedback phototransistor 4, counting trigger 7, made on D trigger, while the first output of the resistor 1 is connected to the positive terminal of the input power source Uin, and its second output is connected to the first lining of the capacitor 2, to the output "output" of the electronic key 3, the "common" terminal of which is connected to the "common" input bus power source, to Mitter phototransistor 4, the collector of which is connected to the positive bus of the internal power supply Ev.pit, introduced: RS trigger on two elements 2OR-NOT 5 and 6, two channel valves 3OR-NOT, 8 and 9, electronic key 10, while the first lining the capacitor 2 is connected to the first input of the trigger element 2 OR NOT 6 RS, and the clock input “C” of the counting trigger 7, triggered by the rising edge of the input signal (front 01), is connected to the control input “U” of the electronic key 3, to the third inputs of the valves 3 OR NOT 8 and 9 and to the first input of element 2 OR-N 5 RS of the trigger, while the output of the element 2 OR NOT 5 RS of the trigger is connected to the first inputs of the valves 3 OR NOT 8, 9 and to the control input "Y" of the electronic key 10, the second inputs of the elements 3 OR NOT 8 and 9 are connected respectively to the direct and the inverse outputs of the counting trigger 7, and the output “common” of the electronic key 10 is connected to the bus “common” of the input power source, while the control input “U” of the electronic key 3 is an input of a two-channel PWM. The PWM circuit is shown in FIG. Z. and works as follows.

The pulse tgi arriving at the control input (input “U”) of key 3 (see Fig. 4. is a diagram of the signals at the outputs of the PWM circuit valves) with logic level 1 (log. 1), is simultaneously input to element 5, input “C »Of the counting trigger 7 and two elements 3 OR NOT 8 and 9. As a result, along the edge of the input pulse (moment t0 in Fig. 4), the counting trigger 7 will go into the inverse state, the RS trigger will be in the log state. 0 (at the output of the element 2 OR NOT 5 the level is log. 0, and at the output of the element 2 OR NOT 6 the level is log. 1), and at the outputs of the elements ZILN NOT 8 and 9 the log levels will act. 0, i.e. at the moment of the action of the tgi pulse, blocking (prohibition) of information transfer from the outputs of the counting trigger 7 to the inputs of the ZILI-NOT 8 and 9 elements is carried out. This blocking will be valid for the entire duration of the tgi pulse. After the end of the action of the pulse tg (moment t1 Ha of Fig. 4), at the output of the valve 2 OR NOT 5, a signal with a log level will remain in effect. 0, and at the output of the valve 2OR-NOT 6 - the level of the log. 1. As a result, only at the output of one of the two elements 3OR-NOT 8 (Kn1) or 3OR-NOT 9 (Kn2) a working signal with a log level is formed. 1, which then goes to the gate of one of the power MOS transistors of the VIP converter. At the same time, at the end of the pulse tg, the process of charging the time-setting capacitor 2 along the circuit of resistor 1 and capacitor 2 with almost constant current will begin. Therefore, the voltage across the capacitor 2 will increase according to a linear law, i.e. according to law

When the voltage Uc2 reaches the capacitor 2 (moment t2 in Fig. 4) equal to the response threshold of the 2OR-NOT 6 element (Uc2 = Upolement of the 2OR-NOT 6 element), the R-S trigger on the 2OR-NOT 5 and 6 elements will be set to the log state. 0 (at the output of the element 2 OR NOT 6 the level is log. 0, and at the output of the element 2 OR NOT 5 is the level log. 1), and the formation of the pulse width of the PWM (t.sh) will be completed. In this case, the signal level log. 1 from the output of the gate 2OR-NOT5 will go to the control input "U" of the electronic key 10, and the discharge of the capacitor 2 will begin through the low resistance of the open electronic key 10. In other words, this means that the discharge process of the capacitor 2 will begin before the arrival of the next pulse tg, t. e. as well as in the PWM prototype circuit. So, the scheme of the proposed PWM fully performs the functions of the prototype, since its counting trigger 7 is controlled by signals of constant duration equal to the duration generated by the generator i.e. duration tgi. It remains to compare them in terms of profitability i.e. in terms of the number of logic elements or, which is the same in terms of the number of transistors in the case of PWM implementation in the form of a crystal when the latter is implemented on complementary MOS transistors with n and p-type conductivity. Recall that for the implementation of the inverter, two MOS transistors are required (one transistor with p-type conductivity and one p-type transistor), and for the implementation of the 2OR-NOT element or 2I-NOT element, 4 MOS transistors are required (two p-type transistors and two transistors with p-type conductivity).

Comparison of the PWM circuit of the prototype made on the NAND elements with the proposed PWM circuit shown in FIG. 3 in terms of the number of elements shows that the last of these two circuits is implemented on a smaller number of elements with the same number of inputs or, which in this case is the same, on a smaller number of transistors. That is, it is more economical in the number of transistors and, therefore, consumes less power. In particular, the discharge circuit of the capacitor 2 in the PWM circuit shown in FIG. 3, is implemented on two transistors (meaning that MOSFETs with p-type conductivity are used as electronic keys 3 and 10), while in the PWM circuit of the prototype shown in FIG. 2 for its implementation, 5 transistors are required (two transistors with p-type conductivity and 2 transistors with p-type conductivity go to build a 2I-NOT element and one transistor with p-type conductivity goes to build an electronic key). Moreover, in the proposed PWM scheme, implemented on the OR-NOT elements, there is no inverter, and this is another minus two transistors in her favor. In addition, the digital part of the proposed PWM circuitry is fully implemented on elements of the same type, namely, only OR-NOT elements, while the PWM circuitry of the prototype uses AND-NOT elements and I. And this can give an additional gain in the number of transistors when its implementation in the form of a crystal. In other words, the proposed PWM circuit shown in FIG. 3, more economical in the number of elements (valves, transistors). Therefore, it has higher reliability, consumes less power, and can find wider application.

It should be noted that profitability in the number of transistors is a point that is especially important when implementing PWM in the form of a crystal, since the LEs themselves are a source of interference in the crystal. But a reduction in the number of LEs will contribute not only to a decrease in internal noise, but also to a decrease in heat release inside the crystal. And, as a consequence, increase the service life of the elements (i.e., increasing reliability), since the elements operate in a more lightweight thermal mode.

Claims (1)

A two-channel pulse-width modulator containing a timing resistor and a capacitor, an electronic key with three outputs: control "U", "common" and "output", a feedback phototransistor, a counting trigger made on the D trigger, while the first output of the resistor is connected to the positive terminal of the input power supply Uin, and its second output is connected to the first capacitor plate, to the output of the electronic key, the common terminal of which is connected to the common input bus of the input power source, to the emitter of the phototransistor, call the vector of which is connected to the positive bus of the internal power supply Ev.pit, the following are entered: RS trigger on two elements 2 OR-NOT, two channel valves 3 OR-NOT, an electronic key, while the first capacitor plate is connected to the first input of element 2 OR-NOT RS of the trigger, and the clock input "C" of the counting trigger, triggered by the rising edge of the input signal (front 01), is connected to the control input "U" of the electronic key, to the third inputs of the gates 3 OR-NOT and to the first input of the element 2 OR-NOT RS trigger, with the output of element 2 OR NOT RS the trigger is connected to the first inputs of the gates 3 OR-NOT and to the control input “U” of the electronic key, the second inputs of the elements 3 OR-NOT are connected respectively to the direct and inverse outputs of the counting trigger, and the output “common” of the electronic key is connected to the bus “common” input power source, while the control input "U" of the electronic key is the input of a two-channel pulse-width modulator.

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