RU168842U1 - Two-channel PWM with double regulating effect on ramp voltage slope - Google Patents

Abstract

The utility model relates to the field of electronics and can be used in the development of secondary power sources (VIP). The proposed scheme of a two-channel PWM with a double regulating effect on the slope of the sawtooth voltage differs from the prototype in fewer logic elements (valves), higher reliability and a wider range of regulation fill factor. All these positive qualities were achieved by introducing into the circuit a counting trigger executed on the D trigger, triggered by to the drop edge of the input signal (front 10), two channel GI gates connected by new interconnects. The introduced elements and inter-element communications made it possible to exclude a part of the logical elements from the prototype circuit, ensure the operation of the counting trigger from pulses of constant duration, thereby increasing the reliability of the dual-channel PWM circuit and expanding the duty cycle of the duty cycle.

Description

The utility model relates to the field of electronics and can be used in the development of secondary power sources (VIP).

PWM as part of the VIP is used as a device that generates pulse signals, the duration of which depends on the input (Uin.) And the output (Uout) voltages.

Known two-channel PWM (see Fig. 1) with a double regulatory effect on the slope of the sawtooth voltage (hereinafter abbreviated saw), given in the literature (I. N. Bukreev, V. I. Goryachev, B. B. Mansurov. Microelectronic circuits of digital devices Publishing house "Technosphere", Moscow, 2009, p. 620. Fig. 11.15.2). The circuit contains the PWM itself, which contains a timing RC circuit, an electronic key (which can be either an MOS transistor, or a bidirectional key of type 564 KT3), an OR element 2, a countable trigger based on a D trigger, triggered by the rising edge of the input signal (front 01) and two channel gates 2OR-NOT, the signals from which then go to the gates of the power key MOS transistors, feedback photodiode VD1.2, connected in parallel to the resistor of the timing circuit in the reverse biased mode.

Such a scheme works as follows. We can assume that the current in the RC circuit increases according to a linear law (according to the law of a saw with a certain slope), since the capacitor is practically charged with a constant current I, determined from the expression:

Therefore, when Uin changes, the saw tilt will change. With an increase in Uin, the saw tilt will increase, and the voltage across the capacitor will quickly reach the switching voltage of the switching threshold of the 2OR element (Uper.per), which for elements based on KMDP-IS is approximately Ev.pit / 2, i.e. Upr.per. = Ev.pit / 2, where Evn.pit. - supply voltage of the internal power source. This voltage, as a rule, is significantly less than the voltage Uin and most often amounts to about 5 volts.

As a result, the pulse duration at the output of the 2OR valve will decrease. When the input voltage decreases, the saw tilt will decrease, and the pulse duration will increase. That is, the PWM scheme works in accordance with the law

where tsh is the PWM pulse duration at the output of the 2OR element.

Suppose that the voltage at the output of the VIP has increased (for example, the load current has decreased). In this case, the current increases through the LED VD1.1 and, therefore, through the photodiode VD1.2. That is, an additional current will flow into the capacitor C, comprising a certain part of the LED current, determined through the current transfer coefficient of the LED Ki. This will lead to an increase in the inclination of the saw and, consequently, to a decrease in the duration of the pulse generated at the output of the 2OR gate, and thus the voltage will stabilize at the output of the VIP.

Such a scheme has the following disadvantages.

1. The feedback element, in this case, the photodiode (or maybe a phototransistor), is under a large reverse voltage (for onboard VIPs it is usually 20-40 volts), which can exceed the specified reverse voltage reflected in the technical conditions (for example, reverse the voltage for the 3OD120 diode is 10 volts). Consequently, the scope of the scheme is narrowed.

2. At a voltage of Uin = Uin.max. the voltage across the capacitor C (Uc) can reach the value Uc = Ein.pit. + 0.7 volt., where Ein.pit. is the voltage of the internal power source. That is, this voltage Uc is significantly greater than the voltage of the switching threshold of the 2OR element, which, if it is performed on the KMDP-IS elements, is approximately E.s./2. And then for the discharge of the capacitor C to the level of logical zero (hereinafter abbreviated log. 0) through the electronic key Cl will take more time. And this means that the input pulse tg, coming from the pulse generator to the control input “U” of the key Kl, should have a longer duration. The latter is undesirable, since it will lead to a decrease in the fill factor C3, which is responsible for the efficiency of the power source. The fill factor Kz is determined from the expression:

where tish is the pulse duration generated by the PWM circuit itself;

Tg = tgi + tp - the period of the pulses arriving at the control input of the key K from the pulse generator; tп - pause duration between pulses tг.

3. The maximum pulse duration that can be generated by the PWM circuit, which occurs when Uin = Uin.min, is determined from the expression

But for the PWM scheme, not only the maximum pulse duration that it generates is important, but also the minimum, that is, the control range within which this duration varies is important. This is due to the fact that during the operation of the VIP in the regimes close to the idle mode or in the idle mode and at the maximum input voltage, the pulse width of the generated PWM can be significantly less than the pulse duration tg from the pulse generator. And here it is very important that this duration is enough for the counting trigger to fire (for example, the ТМ2 counting trigger of the most common KMDP-IS 564, 765 series, unpacked version of the 564 series, for 5 volt power supply, for its normal operation, it requires that the pulse duration and pause duration between they were identical and not less than 270 ns).

But since in the PWM circuit shown in FIG. 1, the counting trigger is controlled by pulses from the output of the 2OR element, the duration of which varies depending on the input and output voltages, it is clear that this duration can be less than the indicated 270 ns. And then the VIP circuit may fail. To avoid idling, load resistors are artificially installed at the output of the VIP, but they reduce the efficiency. But if the counting trigger in the PWM circuit shown in FIG. 1, would work from narrower pulses, then, probably, it would be possible to do without load resistors. But, and if with them, then these resistors will certainly have higher ratings. That is, the impulse duration control range is important here, i.e. the range within which the PWM scheme operates, as discussed above. For any PWM scheme, the best option is one in which the coefficient K3 is regulated within the entire duration of the pause tp, i.e. from Кзmax = tп / Тг to Kзmin = Δt / Тг, where Δt <tг. Thus, during the operation of the counting trigger from pulses of variable duration, a situation may arise in which the counting trigger does not work due to the pulse being too short in duration, insufficient for its reliable switching. The latter is quite possible when idling and, especially, with random surges of input voltage exceeding Uin.max, as a result of which the reliability of the circuit decreases, which is its third drawback.

The closest in technical essence is the dual-channel PWM scheme used in the product: IVEP K275.010SF module. ShUKR. 436434.004. The PWM circuit of this product is shown in FIG. 2. The PWM includes a timing circuit consisting of a resistor 1 and a capacitor 2, an electronic switch 3 having three outputs: a control, a "common" and an "output", an input gate 2I-HE4, a feedback phototransistor 5, an inverter 6, a tiger RS type on two gates 2I-HE7, 8, interrogation valve 2I-HE9, counting trigger 10 based on the D-trigger, triggered by the rising edge of the input signal (front 01), two channel gates 2OR-NOT, 11, 12. At the same time the first output of resistor 1 is connected to the positive input power bus Uin, and its second output is connected to the first circuit capacitor 2, to the output "output" of the electronic key 3, to the emitter of the phototransistor 5 (whose collector is connected to the plus terminal of the internal power supply Eut. power) and to the input of the inverter 6, the output of which is connected to the input S of the RS type trigger, input R which is connected to the first input of the input gate 2I-HE4 and to the first input of the interrogation valve 2I-HE9, the second input of which is connected to the output of the gate 2I-HE8 of the RS type trigger and the second input of the input gate 2I-HE4, the output of which is connected to the control input of the electronic key 3. At the same time, exit d of the interrogation valve 2I-HE9 is connected to the input “C” of the counting trigger 10 and to the first inputs of the channel gates 2IL-HE11 and 12, the second inputs of which are connected to the direct and inverse outputs of the counting trigger 10, respectively, the second lining of the capacitor 2 and the output “common” of the electronic key 3 are combined and connected to the “common” input power bus, pulses from the pulse generator are received at the first input of the input gate 2I-H4, and the signals from the outputs K1 K2 of the channel gates 2ILI-HE11 and 12 are then fed to the gates of the power MIS transistors atelier VIP (MOS transistors are not shown here).

Consider the operation of the prototype circuit, from the moment when a pulse signal with a log level is applied to the input of the 2I-HE4 gate. 0 from the pulse generator. In this case, there will be the following distribution of logic levels at the outputs of the 2I-NOT gates of the two-channel PWM circuit.

At the output of the valve 2I-HE4, a log level is formed. 1, which will lead to the unlocking of the electronic key 3, and the discharge of the capacitor 2 through the low resistance of the public key 3 will begin. At the same time, the signal from the pulse generator will go to the R input of the R-S trigger on valves 2I-HE7, 8, and set it to the state log. 1, i.e. at the output of the 2I-NOT 8 valve, the log level will be set. 1, and at the output of the valve 2I-NE7 level log. 0. The level of the log. 1 will be installed at the output of the interrogation valve 2I-HE9, which, entering the inputs of the channel gates 2IL-HE11 and 12, will form a log level at their outputs. 0. That is, at the moment of the pulse coming from the generator, there will be a reliable ban on the transfer of information from the outputs of the counting trigger 10 to the gates of the power keys of the MOS transistors of the VIP converter, which is very important. This is the so-called guaranteed pause (cut-out) or "dead" time in foreign literature. At the same time, a signal with a log level. 1 from the output of the valve 2I-HE8 goes to the second input of the valve 2I-HE4, but it does not currently affect its operation. Consider the process of the circuit after the end of the pulse from the generator, i.e. when at the input of the valve 2I-HE4 there is a log level. one.

In this case, the log level is formed at the output of the 2I-HE4 valve. 0, the electronic key 3 closes, and the charge of the capacitor 2 begins through the resistance! almost constant current. In this case, at the output of the interrogation valve 2I-NE9, the log level will act. 0, and at the output of K1 or K2, i.e. only on one of the two channel gates 2 OR NOT 11 or 12, the log level is formed. 1, which will go to the input gate of the MOS transistor of the VIP converter. When the voltage across the capacitor 2 reaches the switching threshold of the inverter 6, a log level will be formed at its output. 0, and the R-S trigger on the 2I-NE7, 8 gates will be set to the inverse state, at which the log level will act on the output of the 2I-HE7 gate. 1, and at the output of the valve 2I-NOT8 - level log. 0. The latter will form a level log. 1 at the output of the interrogation gate 2I-HE9, which, entering the inputs of the channel gates 2IL-HE11 and 12, will form the log levels at their outputs K1 and K2. 0, thereby completing the cycle of obtaining the working impulse. In this case, the signal level log. 0 from the output of the gate 2I-HE8 will form a signal with a log level at the output of the input gate 2I-HE4. 1, which will open the electronic key 3, and enable the discharge process of the capacitor 2 through the low resistance of the public key

3. That is, the voltage across the capacitor 1 will never exceed a voltage equal to the voltage of the switching threshold of the inverter 6, and thus the first drawback of the PWM circuit shown in FIG. one.

Since in this circuit the feedback photodiode is connected to the positive terminal of the internal power supply EHP, which is usually 5 volts, the second drawback of the PWM circuit shown in FIG. 1. But since this circuit at the input of the counting trigger is controlled by pulses of variable duration, the third disadvantage of the PWM circuit shown in FIG. 1., due to the operation of the counting trigger from pulses of variable duration.

Turning to the PWM scheme shown in FIG. 2, it can be seen that this circuit is implemented on a significantly larger number of logic elements, compared with the PWM circuit in FIG. 1, which is its drawback. Therefore, the purpose of the utility model is to simplify the PWM circuit of the prototype by reducing the number of logic elements (gates) and increasing its reliability due to the operation of the counting trigger from pulses of constant duration.

This goal is achieved by the fact that in the circuit of a two-channel PWM containing a timing resistor 1 and a capacitor 2, an electronic switch 3 with three outputs: control, "common" and "output", input gate 2I-HE4, feedback phototransistor 5, inverter 6, R-S type trigger on two gates 2I-HE7 and 8, while the first output of the resistor 1 is connected to the positive terminal of the input power Uin, and its second output is connected to the first lining of the capacitor 2, to the output terminal of the electronic key 3, to the emitter of the phototransistor 5, (whose collector is connected to um plus the internal power supply (Eut. power) and to the input of the inverter 6, the output of which is connected to the input S of the RS type trigger, and its R input is connected to the first input of the input valve 2I-NOT 4, the second input of which is connected to the output of the valve 2I- HE8 of the RS type trigger, the output of the input gate 2I-HE4 is connected to the control input of the electronic key 3, while the second lining of the capacitor 2 and the output of the "common" electronic key 3 are combined and connected to the "common" input power bus, a counting trigger 9, made on the D trigger, triggered by the drop in the input signal (front 10), two channel valves 3I, 10 and 11, while the clock input "C" of the counting trigger 9 is connected to the first input of the input valve 2I-HE4 and to the first inputs of the channel valves 3I, 10 and 11, the second the inputs of which are connected respectively to the direct and inverse outputs of the counting trigger 9, and the third inputs of the channel gates 3I, 10 and 11 are connected to the output of the 2I-HE8 RS gate of the trigger, while the first input of the 2I-HE4 input gate is a dual-channel PWM input.

As can be seen from FIG. 3, the circuit operates from short (narrow) pulses of duration tig with a log level. 0.

Consider the operation of the circuit of the proposed PWM, from the moment when a signal with a log level is applied to the input of the 2I-NE4 gate. 0 from the pulse generator. In this case, the following distribution of logic levels at the outputs of the gates of the dual-channel PWM circuit will take place.

At the output of the valve 2I-HE4, a log level is formed. 1, which will lead to the unlocking of the electronic key 3, and the discharge of the capacitor 2 through the low resistance of the public key 3 will begin. At the same time, the signal from the pulse generator will go to the R input of the R-S trigger on valves 2I-HE7, 8, and set it to the state log. 1, i.e. at the output of the 2I-NE8 valve, the log level will be set. 1, and at the output of the valve 2I-NE7 level log. 0. The same signal with a log level. 0 will go to the clock input “C” of the counting trigger 9 and to the first inputs of the channel gates 3I, 10 and 11. As a result, the counting trigger 9 will switch to the opposite state along the falling edge of the input signal (front 10), while the transmission of information from the outputs of the counting trigger 9 at the time of its switching to the outputs of the channel gates 3I will be reliably blocked by a signal with a log level. 0 acting on their inputs.

That is, at the time of the pulse with the level of the log. 0, coming from the generator, there will be a reliable ban on the transfer of information from the outputs of the counting trigger 9 to the gates of the power keys of the MOS transistors of the VIP converter, which is very important. This is the so-called guaranteed pause (cut-out) or "dead" time in foreign literature. At the same time, a signal with a log level. 1 from the output of the gate 2I-HE8 goes to the second input of the input gate 2I-HE4, but it does not affect its operation at this time. Consider the process of the circuit after the end of the pulse from the generator, i.e. when at the input of the input gate 2I-HE4 there is a log level. one.

In this case, the log level is formed at the output of the 2I-HE4 valve. 0, the electronic switch 3 closes, and the charge of the capacitor 2 begins through the resistance 1 with almost constant current. In this case, at the output of the valve 2I-HE8, the log level will act. 1, and at the output of K1 or K2, i.e. only on one of the two channel valves 3I, 10 or 11 will the log level be formed. 1, which will go to the input gate of the MOS transistor of the VIP converter. When the voltage across the capacitor 1 reaches the switching threshold of the inverter 6, a log level will be formed at its output. 0, and the R-S trigger on the 2I-NE7, 8 gates will be set to the inverse state, at which the log level will act on the output of the 2I-HE7 gate. 1, and at the output of the valve 2I-NOT8 - level log. 0. The latter, entering the inputs of the channel gates 3I, 10 and 11, will form the log levels at their outputs K1 and K2. 0, thereby completing the cycle of obtaining the working impulse. In this case, the signal level log. 0 from the output of the gate 2I-HE8 will form a signal with a log level at the output of the input gate 2I-HE4. 1, which will open the electronic key 3, and allow the process to discharge the capacitor 2 through the low resistance of the public key 3 before the next pulse comes from the pulse generator.

That is, the voltage across the capacitor 1 will never exceed a voltage equal to the voltage of the switching threshold of the inverter 6.

It is interesting to note that in this two-channel PWM circuit, in principle, the presence of narrow pulses is not observed at any of the inputs, either the counting trigger 9, or at the inputs of gates 3I, 10, and 11, which is extremely important. Indeed, the narrowest pulse at the input of the counting trigger 9 is a pulse with a duration equal to the pulse duration tg. And at the inputs of gates 3I, 10 and 11, the shortest pulse (with a log level of 1) cannot have a duration shorter than the duration tg.

And that is purely theoretical, since in practice the pulse duration with the level of the log. 1 here always must be longer than the duration of tg. This suggests that in this PWM scheme, the duty cycle Kz can vary from almost zero to the maximum value. Let the circuit operate at maximum input voltage and in idle mode. In this case, taking into account the current through the phototransistor 5 and the current through the resistor 1, the capacitor 2 will be charged most quickly. And at the output of the 2I-NOT8 valve, a signal with a log level will be formed. 0 with the duration tgi + Δt, where Δt <tgi - additives to the pulse tgi due to the fast charge of the capacitor 2. But the value of the additive Δt can be nanoseconds and therefore channel valves 3I, 10 and 11 may not let them through. For the signal to pass through the gate, its duration must be greater than the value determined by the average propagation delay. But such short duration pulses will not be able to exert any effect on the gates of power MOS transistors, i.e. will not be able to set them on.

And so, since in the PWM circuit shown in FIG. 3 counting trigger 9 runs on pulses with a log level. 0 of constant duration equal to tgi, then the probability of its failure due to non-operation from a short pulse is eliminated, and thereby the main disadvantage of the prototype circuit is eliminated, namely, the possibility of non-operation (failure) of the counting trigger 9 from short pulses arriving at its counting input is "C".

Claims (1)

A two-channel PWM containing a timing resistor and capacitor, an electronic key with three outputs: control, common and output, 2I-NOT input gate, feedback phototransistor, inverter, RS type trigger on two 2I-NOT gates, while the first resistor pin is connected to the positive terminal of the input power supply Uin, and its second output is connected to the first capacitor plate, to the output is the output of the electronic key, to the emitter of the phototransistor, the collector of which is connected to the plus terminal of the internal power supply of the power supply, and to the input of the inv The inverter whose output is connected to the input S of the RS type trigger, the input R of which is connected to the first input of the 2I-NOT input gate, the second input of which is connected to the output of the 2I-NOT trigger of the RS type trigger, the output of the 2I-NOT input valve is connected to the control input of the electronic key, and the second capacitor plate and the common electronic key output are combined and connected to the common input power supply bus, into which a counting trigger is inserted, made on the D trigger, triggering along the falling edge of the input signal, two channel valves 3I, p and this clock input from the counting trigger is connected to the first input of the input gate 2I-NOT and to the first inputs of the channel gates 3I, the second inputs of which are connected respectively to the direct and inverse outputs of the counting trigger, and the third inputs of the channel gates 3I are connected to the output of the 2I-NOT gate trigger type RS, with the first input of the input gate 2I-NOT is the input of a two-channel PWM.

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