Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is described in further detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The following detailed description of implementations of the invention refers to the accompanying drawings in which:
fig. 2 shows a module structure of a switching power supply circuit according to an embodiment of the present invention, and for convenience of description, only the parts related to this embodiment are shown, which are detailed as follows:
as shown in fig. 2, the switching power supply circuit 1 according to the embodiment of the present invention is used for charging an electric device (not shown in the figure), and includes a rectifier bridge 10, a transformer 20, a power switch M0, a signal generating module 30, a current bias module 40, and a driving module 50.
The rectifier bridge 10 is connected to a transformer 20, and the transformer 20 is connected to a power switching tube M0 and a power consumer. Specifically, the rectifier bridge 10 receives the alternating current, rectifies the alternating current into direct current, and outputs the direct current to the transformer 20, the transformer 20 stores energy according to the direct current when the power switch tube M0 is turned on, and charges the electric equipment according to the stored energy when the power switch tube M0 is turned off, that is, the transformer 20 charges the electric equipment under the action of the power switch tube M0.
In addition, the signal generating module 30 is connected to the power switch M0, and is configured to sample a current at an output terminal of the power switch M0 to obtain a sampled voltage VCS, and generate the PRE-off control signal PRE-off and the switch control signal PULSE according to the sampled voltage VCS and the received reference voltage VCS-off.
The current bias module 40 is connected to the power switch M0 and the signal generating module 30, and is configured to sample a current at an output terminal of the power switch M0, and output a driving current Idrv according to a sampling voltage VCS within an on-time range of the switch control signal PULSE.
The driving module 50 is connected to the power switch tube M0, the current bias module 40, and the signal generating module 30, and configured to drive the power switch tube M0 to turn on according to the received driving current Idrv and a preset driving current Idrv1 output by a preset current source when the switch control signal PULSE and the PRE-off control signal PRE-off are both in an on state, and continuously drive the power switch tube M0 to turn on according to the preset driving current Idrv1 when the switch control signal PULSE is in an on state and the PRE-off control signal PRE-off is in an off state; the preset driving current Idrv1 is smaller than the driving current Idrv; it should be noted that, in the embodiment of the present invention, when the switch control signal PULSE is in the off state, the driving module 50 stops driving the power switch M0 to be turned on, that is, the driving module 50 drives the power switch M0 to be turned off.
In specific implementation, the switch control signal PULSE and the PRE-off control signal PRE-off are both PULSE signals. Preferably, the switch control signal PULSE and the PRE-turn-off control signal PRE-off are both in the on state, which means that the switch control signal PULSE and the PRE-turn-off control signal PRE-off are both at a high level; the switch control signal PULSE in the off state means that the switch control signal PULSE is at a low level, and the PRE-off control signal PRE-off in the off state also means that the PRE-off control signal PRE-off is at a low level.
In addition, the switch control signal PULSE is a control signal that can control the on/off of the power switch transistor M0, that is, when the switch control signal PULSE is at a high level, the driving module 50 drives the power switch transistor M0 to be turned on, and when the switch control signal PULSE is at a low level, the driving module 50 drives the power switch transistor M0 to be turned off.
Further, the switching power supply circuit 1 provided in the embodiment of the present invention further includes other circuits such as a filter circuit, and structures, operating principles, and connection relationships between the other circuits such as the filter circuit and other devices in the switching power supply circuit 1 are the same as those in the prior art, and reference may be made to the prior art specifically, and details are not described here.
Further, as a preferred embodiment of the present invention, as shown in fig. 3, the signal generating module 30 includes a pre-shutdown unit 301 and a shielding unit 302.
Specifically, the pre-turn-off unit 301 is connected to the power switch tube M0, and is configured to sample a current at an output end of the power switch tube M0 to obtain a sampling voltage VCS, generate a pre-turn-off control voltage VCS1 according to the sampling voltage VCS, and compare the pre-turn-off control voltage VCS1 with a reference voltage VCS-off to output a comparison signal.
And a shielding unit 302 connected to the PRE-turn-off unit 301, for generating a PRE-turn-off control signal PRE-off and a switch control signal PULSE according to the comparison signal.
Further, referring to fig. 3 and 8, according to the fig. 8 and the fig. 3, in one period of the PRE-off control voltage VCS1, when the PRE-off control voltage VCS1 is greater than the reference voltage VCS-off for the first time, the PRE-off unit 301 outputs a high-level comparison signal to the shielding unit 302, the shielding unit 302 controls the PRE-off control signal PRE-off to switch from the on-state to the off-state, and delays the on-state time of the switch control signal PULSE according to the high-level comparison signal; when the pre-turn-off control voltage VCS1 is greater than the reference voltage VCS-off for the second time, the pre-turn-off unit 301 outputs a low-level comparison signal to the shielding unit 302, and the shielding unit 302 controls the switch control signal PULSE to be switched from the on state to the off state according to the low-level comparison signal.
In this embodiment, in one period, when the PRE-off control voltage VCS1 is greater than the reference voltage VCS-off for the first time, the shielding unit 302 controls the PRE-off control signal PRE-off to switch from the on state to the off state, and delays the on-state time of the switch control signal PULSE, so as to effectively prevent the power switch M0 from being turned off by mistake, and improve the reliability of the switching power supply circuit 1.
Further, referring to fig. 2 and 8, according to fig. 2 and 8, in the first time t1 when the switch control signal PULSE is switched to the on state, and when the PRE-off control signal PRE-off is in the on state, the current bias module 40 generates the first driving current I1 under the action of the sampling voltage VCS, the driving module 50 amplifies the first driving current I1 under the action of the switch control signal PULSE, and drives the power switch M0 to be turned on according to the amplified first driving current I1 and the preset driving current Idrv 1.
During a second time t2 after the first time t1, when both the switch control signal PULSE and the PRE-off control signal PRE-off are kept in the on state, the current bias module 40 generates a second driving current I2 under the action of the sampling voltage VCS, and the second driving current I2 increases with the increase of the sampling voltage VCS; the driving module 50 amplifies the gradually increased second driving current I2 under the action of the switch control signal PULSE, and continuously drives the power switch tube M0 to be turned on according to the amplified second driving current I2 and the preset driving current Idrv 1.
After the second time t2, when the switch control signal PULSE is kept in the on state and the PRE-off control signal PRE-off is switched from the on state to the off state, the driving module 50 amplifies the preset driving current Idrv1 under the action of the switch control signal PULSE, and continuously drives the power switch tube M0 to be turned on according to the amplified preset driving current Idrv 1.
It should be noted that, in the embodiment of the present invention, the driving current Idrv output by the current bias module 40 is composed of two stages, i.e., a first driving current I1 and a second driving current I2, that is, in an initial stage t1, the power switching tube M0 is driven to be turned on by using a larger first driving current I1 and a preset driving current Idrv1, and in a second time t2 range after the power switching tube M0 is turned on, the power switching tube M0 is driven to be turned on by using a gradually changed second driving current I2 and a preset driving current Idrv1, and after a second time t2, the power switching tube M0 is driven to be turned on by using only a preset driving current Idrv1, so that the purpose of driving the power switching tube M0 by using a variable current is achieved.
As a preferred embodiment of the present invention, in a specific implementation, when both the switch control signal PULSE and the PRE-off control signal PRE-off are in an on state, the preset driving current Idrv1 output by the preset current source is zero or smaller than the driving current Idrv output by the current bias module 40. That is, when the switch control signal PULSE and the PRE-off control signal PRE-off are both in the on state, the preset driving current Idrv1 outputted by the preset current source may be zero or a fixed current value, and the fixed current value is smaller than the driving current Idrv outputted by the current bias module 40.
When the preset driving current Idrv1 output by the preset current source is zero, the driving module 50 drives the power switch tube M0 only according to the driving current Idrv output by the current bias module 40; when the preset driving current Idrv1 output by the preset current source is a fixed current value, the driving module 50 drives the power switch M0 according to the sum of the driving current Idrv output by the current bias module 40 and the preset driving current Idrv1 output by the preset current source.
It should be noted that, in the embodiment of the present invention, although the preset driving current Idrv1 output by the preset current source is zero when both the switch control signal PULSE and the PRE-off control signal PRE-off are in the on state, the preset driving current Idrv1 output by the preset current source is not zero when the switch control signal PULSE is in the on state and the PRE-off control signal PRE-off is in the off state.
In addition, in other embodiments of the present invention, the preset driving current Idrv1 output by the preset current source may gradually increase and be much smaller than the driving current Idrv output by the current bias module 40; it should be noted that, in the embodiment of the present invention, the preset driving current Idrv1 outputted by the preset current source may be increased from zero, or may be gradually increased from a smaller current value, regardless of how the preset driving current Idrv1 is increased, which is much smaller than the driving current Idrv outputted by the current bias module 40.
In this embodiment, the switching power supply circuit 1 of the present invention provides a preset driving current Idrv1 and a larger first driving current I1 to the power switch M0 in a short time, so that the power switch M0 is turned on according to the preset driving current Idrv1 and the first driving current I1, thereby shortening the on-time of the power switch M0, further reducing the energy loss of the switching power supply circuit 1 during the on-time of the power switch M0, and in the second time t2 range when the power switch M0 is turned on, driving the power switch M0 with the preset driving current Idrv1 and the gradually changed second driving current I2, and driving the power switch M0 with only a small preset driving current Idrv1 after the second time t2, so as to drive the power switch M0 with a variable driving current, further improving the energy utilization ratio, and making the charge amount accumulated in the power switch M0 during the on process decrease, thereby reducing energy consumption.
Further, as a preferred embodiment of the present invention, as shown in fig. 3, the current bias module 40 includes: a first mirror current unit 401, a sampling unit 402, and a control unit 403.
The first mirror current unit 401 is connected to the control unit 403, the control unit 403 is connected to the sampling unit 402 and the shielding unit 302, the sampling unit 402 is connected to the power switch M0, and the control unit 403 and the sampling unit 402 are both connected to the driving module 50.
Specifically, referring to fig. 3 and fig. 6 together, according to fig. 3 and fig. 6, during the first time t1, the control unit 403 outputs the driving current to the driving module 50 according to the current output by the first mirror current unit 401 under the action of the switch control signal PULSE; the sampling unit 402 samples a current at an output end of the power switching tube M0 to obtain a sampling voltage VCS, and outputs a driving current to the driving module 50 under the action of the sampling voltage VCS, wherein a sum of the driving current output by the control unit 403 and the driving current output by the sampling unit 402 is a first driving current I1, and the driving current output by the sampling unit 402 is smaller than the driving current output by the control unit 403, preferably, the driving current output by the sampling unit 402 is close to zero, and the first driving current I1 is the driving current output by the control unit 403.
During a second time t2 after the first time t2, when the switch control signal PULSE maintains the on state, the control unit 403 stops outputting the driving current to the driving module 50, and the sampling unit 403 generates the second driving current I2 under the action of the sampling voltage VCS and outputs the second driving current I2 to the driving module 50.
Further, as shown in fig. 3, the first mirror current unit 401 is also connected to the sampling unit 402. The first mirror current unit 401 generates an initial driving current I0, and the control unit 403 outputs a driving current to the driving module 50 according to the initial driving current I0 under the control of the switch control signal PULSE; the sampling unit 402 receives the initial driving current I0 output by the first mirror current unit 401, and outputs a driving current to the driving module 50 according to the initial driving current I0 under the action of the sampling voltage VCS.
It should be noted that, in other embodiments of the present invention, the sampling unit 402 may also be externally connected with an independent current source, so that the current output by the externally connected independent current source is used to replace the initial driving current I0 output by the first mirror current unit 401.
In this embodiment, when the power switch M0 is turned on, since the driving current output by the sampling unit 402 is much smaller than the driving current output by the control unit 403 and is close to zero, the driving current output by the sampling unit 402 is negligible, that is, when the power switch M0 is turned on, the power switch M0 can be turned on only according to the driving current output by the control unit 403, that is, the first driving current I1, so that the on-time of the power switch M0 is effectively shortened, and the energy loss of the switching power supply circuit 1 during the on-duration of the power switch M0 is further reduced.
In addition, when the power switch M0 is turned on within the second time t2, the power switch M0 is stopped being driven by the larger first driving current I1, the power switch M0 is continuously driven by the gradually changed second driving current I2, and after the second time t2, the power switch M0 is continuously driven by the smaller preset driving current Idrv1, so that the amount of electric charges accumulated in the conduction process of the power switch M0 is reduced, the energy loss is reduced, and the energy utilization rate is further improved.
Further, as a preferred embodiment of the present invention, as shown in fig. 3, the sampling unit 402 includes: the sampling subunit 402a is connected to the mirror current subunit 402b, and the sampling subunit 402a is connected to the mirror current subunit 402 b.
The sampling subunit 402a samples the current at the output end of the power switching tube M0 to obtain a sampling voltage VCS; when the switch control signal PULSE is kept in the on state in a second time t2 after the first time t1, the sampling subunit 402a generates a driving current under the action of the sampling voltage VCS, and the mirror current subunit 402b amplifies the driving current generated by the sampling subunit 402a and outputs a second driving current I2; wherein the driving current generated by the sampling sub-unit 402a increases with the increase of the sampling voltage VCS.
In addition, during the first time t1, when the switch control signal PULSE is kept in the on state, the sampling sub-unit 402a generates a driving current under the action of the sampling voltage VCS, and the driving current is close to zero; the mirror current subunit 402b similarly amplifies the driving current generated by the sampling subunit 302a and outputs the amplified driving current.
It should be noted that, in the embodiment of the present invention, in the first time t1, the driving current generated by the sampling subunit 402a under the action of the sampling voltage VCS is close to zero, and therefore, the driving current obtained by amplifying the driving current by the mirror current subunit 402b is also close to zero.
Further, as a preferred embodiment of the present invention, as shown in fig. 4, the pre-shutdown unit 301 includes: the circuit comprises a fixed current source Ia, a variable current source Ib, a comparator COMP, a first switching element M1, a current mirror and a first resistor R1.
A first end of the first resistor R1 is connected to the power switch M0 (not shown in the figure), a second end of the first resistor R1 is connected to a first end of the first switch element M1 and a positive input end of the comparator COMP, a negative input end of the comparator COMP receives the reference voltage VCS-off, an output end of the comparator COMP outputs a comparison signal and is connected to an input end of the current mirror, an output end of the current mirror is connected to an input end of the variable current source Ib, and an output end of the variable current source Ib is connected to an output end of the fixed current source Ia and a second end of the first switch element M1 in common.
In a specific implementation, the first switch element M1 is implemented by a single-pole single-throw switch, and a first terminal and a second terminal of the single-pole single-throw switch are respectively a first terminal and a second terminal of the first switch element M1.
It should be noted that, in the embodiment of the present invention, the current mirror in the pre-shutdown unit 301 may be implemented by using an existing current mirror circuit that can adjust the current of the variable current source Ib, and details thereof are not repeated here.
Further, as a preferred embodiment of the present invention, as shown in fig. 5, the shielding unit 302 includes: the pulse width modulation circuit comprises a first NAND gate NAND1, a second NAND gate NAND2, a third NAND gate NAND3, a first inverter U1, a second inverter U2, a third inverter U3, a fourth inverter U4, a fifth inverter U5, a sixth inverter U6, a capacitor C, a reset-set trigger RS, a logic processing unit 302a and a first fixed pulse width modulation circuit 302 b.
Wherein, the input end of the first inverter U1 is commonly connected with the first input end of the first NAND gate 1 and the output end of the first fixed pulse width modulation circuit 302b, the second input end of the first NAND gate NAND1 receives the comparison signal, the output end of the first inverter U1 is connected with the first input end of the reset-set flip-flop RS, the output end of the first NAND gate NAND1 is connected with the input end of the second inverter U2, the output end of the second inverter U2 is connected with the second input end of the reset-set flip-flop RS and the second input end of the third NAND gate 3, the output end of the reset-set flip-flop RS is connected with the second input end of the second NAND gate NAND2, the first input end of the second NAND gate 2 is connected with the output end of the logic processing unit 302a and the input end of the first fixed pulse width modulation circuit 302b, the output end of the second NAND gate 2 is connected with the input end of the third inverter U3, the output end of the third inverter U3 outputs a PRE-off control signal PRE-off and is connected to the input end of the fourth inverter U4, the output end of the fourth inverter U4 is connected to the first end of the capacitor C and the input end of the fifth inverter U5, the second end of the capacitor C is grounded, the output end of the fifth inverter U5 is connected to the input end of the sixth inverter U6, the output end of the sixth inverter U6 is connected to the first input end of the third NAND gate NAND3, the output end of the third NAND gate 3 is connected to the input end of the logic processing unit 302a, and the logic processing unit 302a outputs a switch control signal PULSE.
It should be noted that, in the embodiment of the present invention, the reset set flip-flop RS is composed of a nor gate, and is active at a high level "1". Further, as a preferred embodiment of the present invention, as shown in fig. 6, the first mirror current unit 401 includes: a second switching element M2, a third switching element M3, a fourth switching element M4, and a fifth switching element M5.
An input end of the second switching element M2 is commonly connected to an input end of the third switching element M3 and receives the power supply voltage VCC, a control end of the second switching element M2 is commonly connected to an output end of the second switching element M2, an input end of the fourth switching element M4 and a control end of the third switching element M3, a control end of the fourth switching element M4 is commonly connected to an output end of the fourth switching element M4 and a control end of the fifth switching element M5, an output end of the third switching element M3 is connected to an input end of the fifth switching element M5, and an output end of the fifth switching element M5 is connected to the control unit 403.
In specific implementation, the second to fifth switching elements M2 to M5 are implemented by PMOS transistors, and the gates, sources and drains of the PMOS transistors are the control terminals, input terminals and output terminals of the second to fifth switching elements M2 to M5, respectively.
It should be noted that, in the embodiment of the present invention, the second switching element M2 to the fifth switching element M5 may also be implemented by using other devices having a switching function, such as an NMOS transistor, an N-type triode, a P-type triode, and the like, which may be specifically selected according to circuit requirements, and here, only a PMOS transistor is taken as an example for description, and no specific limitation is imposed.
Further, as a preferred embodiment of the present invention, as shown in fig. 6, the control unit 403 includes: a second fixed pulse width modulation circuit 403a and a sixth switching element M6.
The input end of the second fixed pwm circuit 403a receives the switch control signal PULSE, the output end of the second fixed pwm circuit 403a is connected to the control end of the sixth switching element M6, the input end of the sixth switching element M6 is connected to the first mirror current unit 401, and the output end of the sixth switching element M6 outputs the driving current.
In specific implementation, the switch control signal PULSE is passed through the second fixed pwm circuit 403a to obtain a PULSE signal with the same phase but a smaller high level width, so that the current bias module 40 provides a larger driving current to the power switch transistor M0 in a short time after the power switch transistor M0 is turned on according to the PULSE signal, so as to shorten the on-time of the power switch transistor M0.
In addition, the sixth switching element M6 is implemented by a PMOS transistor, and a gate, a source and a drain of the PMOS transistor are respectively a control terminal, an input terminal and an output terminal of the sixth switching element M6; it should be noted that, in the embodiment of the present invention, the sixth switching element M6 may also be implemented by using other devices having a switching function, for example, an NMOS transistor, an N-type triode, a P-type triode, and the like, which may be specifically selected according to circuit requirements, and here, only a PMOS transistor is taken as an example for description, and is not limited specifically.
Further, as a preferred embodiment of the present invention, as shown in fig. 6, the sampling subunit 402a includes: a seventh switching element M7, an eighth switching element M8, a ninth switching element M9, a tenth switching element M10, an eleventh switching element M11, a twelfth switching element M12, a thirteenth switching element M13, and a fourteenth switching element M14.
Wherein an input terminal of the seventh switching element M7 is commonly connected to an input terminal of the eighth switching element M8 and receives the initial driving current I0, a control terminal of the seventh switching element M7 is connected to an output terminal of the power switching tube M0, a control terminal of the eighth switching element M8 receives the reference voltage VCS-off, an output terminal of the seventh switching element M7 is connected to an input terminal of the ninth switching element M9 and a control terminal of the eleventh switching element M11, a control terminal of the ninth switching element M9 is connected to a control terminal of the tenth switching element M10 and a control terminal of the thirteenth switching element M13, an output terminal of the eighth switching element M8 is connected to an input terminal of the tenth switching element M10, a control terminal of the twelfth switching element M12 and a control terminal of the fourteenth switching element M14, an output terminal of the ninth switching element M9 is connected to an input terminal of the eleventh switching element M11, an output terminal of the tenth switching element M10 is connected to an input terminal of the twelfth switching element 12, an input terminal of the thirteenth switching element M13 is connected to an output terminal of the fourteenth switching element M14, an output terminal of the thirteenth switching element M13 outputs a driving current, and an output terminal of the eleventh switching element M11 is commonly connected to the ground with an output terminal of the twelfth switching element M12 and an output terminal of the fourteenth switching element M14.
In specific implementation, the seventh switching element M7 and the eighth switching element M8 are implemented by PMOS transistors, and a gate, a source and a drain of the PMOS transistor are respectively a control end, an input end and an output end of the seventh switching element M7 and the eighth switching element M8; the ninth switching element M9 to the fourteenth switching element M14 are implemented by NMOS transistors, and the gates, drains and sources of the NMOS transistors are the control terminals, the input terminals and the output terminals of the ninth switching element M9 to the fourteenth switching element M14, respectively.
It should be noted that, in the embodiment of the present invention, the seventh switching element M7 and the eighth switching element M8 may also be implemented by using other devices having a switching function, such as an NMOS transistor, an N-type triode, a P-type triode, and the like, which may be specifically selected according to circuit requirements, and here, only a PMOS transistor is taken as an example for description, and no specific limitation is made; similarly, the ninth switching element M9 to the fourteenth switching element M14 may be implemented by other devices having a switching function, such as a PMOS transistor, an N-type triode, a P-type triode, etc., which may be specifically selected according to circuit requirements, and are only illustrated by an NMOS transistor, which is not limited specifically.
Further, as a preferred embodiment of the present invention, as shown in fig. 6, the mirror current subunit 302b includes: a fifteenth switching element M15, a sixteenth switching element M16, a seventeenth switching element M17, and an eighteenth switching element M18.
An input terminal of the fifteenth switching element M15 is commonly connected to an input terminal of the sixteenth switching element M16 and receives the power supply voltage VCC, a control terminal of the fifteenth switching element M15 is connected to an output terminal of the fifteenth switching element M15, a control terminal of the sixteenth switching element M16 and an input terminal of the seventeenth switching element M17, an output terminal of the sixteenth switching element M16 is connected to an input terminal of the eighteenth switching element M18, an output terminal of the seventeenth switching element M17 is commonly connected to a control terminal of the seventeenth switching element M17 and a control terminal of the eighteenth switching element M18 and receives the driving current generated by the sampling subunit 402a, and an output terminal of the eighteenth switching element M18 outputs the driving current.
In specific implementation, the fifteenth switching element M15 to the eighteenth switching element M18 are implemented by PMOS transistors, and the gates, sources and drains of the PMOS transistors are respectively the control end, the input end and the output end of the fifteenth switching element M15 to the eighteenth switching element M18.
It should be noted that, in the embodiment of the present invention, the fifteenth switching element M15 to the eighteenth switching element M18 may also be implemented by using other devices having a switching function, such as an NMOS transistor, an N-type triode, a P-type triode, and the like, which may be specifically selected according to circuit requirements, and here, only a PMOS transistor is taken as an example for description, and no specific limitation is imposed.
Further, as a preferred embodiment of the present invention, as shown in fig. 7, the driving module 50 includes: a nineteenth switching element M19, a twentieth switching element M20, a twenty-first switching element M21, a twenty-second switching element M22, a twenty-third switching element M23, a twenty-fourth switching element M24, a twenty-fifth switching element M25, a twenty-sixth switching element M26, a twenty-seventh switching element M27, a second resistor R2, a preset current source Id, and a seventh inverter U7.
Wherein an input terminal of the nineteenth switching element M19 is commonly connected to an input terminal of the twentieth switching element M20 and a first terminal of the second resistor R2 and receives the supply voltage VDD, a control terminal of the nineteenth switching element M19 is commonly connected to an output terminal of the nineteenth switching element M19, a control terminal of the twentieth switching element M20, a second terminal of the second resistor R2, an input terminal of the twenty-first switching element M21 and a first terminal of the twenty-second switching element M22, a control terminal of the twenty-first switching element M21 is connected to an input terminal of the seventh inverter U7 and receives the switching control signal PULSE, an output terminal of the twenty-first switching element M21 is connected to an input terminal of the twenty-sixth switching element M26, a control terminal of the twenty-sixth switching element M26 is commonly connected to a control terminal of the twenty-fifth switching element M25, an input terminal of the twenty-fifth switching element M25 and an output terminal of the preset current source, a second terminal of the twenty-second switching element M22 is commonly connected to an input terminal of the twenty-fourth switching element M24, a control terminal of the twenty-fourth switching element M24 is connected to a control terminal of the twenty-fourth switching element M23 and an input terminal of the twenty-seventh switching element M23, an input terminal of the twenty-fourth switching element M23 receives the driving current Idrv output by the current bias module 40, a control terminal of the twenty-seventh switching element M27 is connected to an output terminal of the seventh inverter U7, an input terminal of the twenty-seventh switching element M27 is commonly connected to an output terminal of the twenty-fifth switching element M20 and to the power switching tube M0, and an output terminal of the twenty-third switching element M23 is commonly connected to the output terminal of the twenty-fourth switching element M24, the output terminal of the twenty-fifth switching element M25, the output terminal of the twenty-sixth switching element M26 and the output terminal of the twenty-seventh switching element M27.
In specific implementation, the nineteenth switching element M19 and the twentieth switching element M20 are implemented by PMOS transistors, and the gates, sources and drains of the PMOS transistors are respectively the control end, the input end and the output end of the nineteenth switching element M19 and the twentieth switching element M20; the twenty-first switching element M21 and the twenty-seventh switching elements M23 to M27 are implemented by NMOS transistors, and gates, drains, and sources of the NMOS transistors are control terminals, input terminals, and output terminals of the twenty-first switching element M21 and the twenty-seventh switching elements M23 to M27, respectively; further, the twenty-second switch element M22 is implemented by a single-pole single-throw switch, and the first terminal and the second terminal of the single-pole single-throw switch are the first terminal and the second terminal of the twenty-second switch element M22, respectively.
It should be noted that, in the embodiment of the present invention, the nineteenth switching element M19 and the twentieth switching element M20 may also be implemented by using other devices having a switching function, such as an NMOS transistor, an N-type triode, a P-type triode, and the like, which may be specifically selected according to circuit requirements, and here, only a PMOS transistor is taken as an example for description, and no specific limitation is made; similarly, the twenty-first switching element M21 and the twenty-seventh switching elements M23 to M27 may be implemented by other devices having a switching function, such as a PMOS transistor, an N-type triode, a P-type triode, and the like, which may be specifically selected according to circuit requirements, and here, only an NMOS transistor is taken as an example for illustration, and no specific limitation is made.
The operation principle of the switching power supply circuit 1 provided by the present invention is specifically described below by taking the circuits shown in fig. 2 to fig. 7 and the timing chart shown in fig. 8 as an example, and the following details are described below:
first, referring to fig. 4, fig. 5 and fig. 8, since the comparison Signal output by the comparator COMP in fig. 4 is logic 1 or 0 output after the pre-off control voltage VCS1 and the reference voltage VCS-off are compared by the comparator COMP, and the pre-off control voltage VCS1 is the sum of the sampling voltage VCS and Δ Vb, at the initial sampling stage, i.e., the first time t1 stage, when the pre-off control voltage VCS1 is smaller than the reference voltage VCS-off, the sampling voltage VCS is certainly smaller than the reference voltage VCS-off, and when the pre-off control voltage VCS1 is smaller than the reference voltage VCS-off, the comparison Signal output by the comparator COMP is 0; where Δ Vb is a voltage difference generated by the variable current source Ib flowing through the resistor R1.
When the comparison Signal output by the comparator COMP is 0, since the Signal LEB is 0 at this time, the PRE-off control Signal PRE-off and the switch control Signal PULSE output by the shielding unit 302b are both at high level at this time, and when the Signal LEB changes from 0 to 1, the PRE-off control Signal PRE-off and the switch control Signal PULSE output by the shielding unit 302b are also at high level at this time during the process that the comparator COMP outputs 0 because the PRE-off control voltage VCS1 is continuously less than the reference voltage VCS-off during the second time t2 period after the first time t 1.
Further, as shown in fig. 6, at the beginning, the mirror circuit formed by the second switching element M2 to the fifth switching element M5 generates the initial driving current I0, i.e., the current flowing through the second switching element M2 and the fourth switching element M4 is I0, and the current flowing through the third switching element M3 and the fifth switching element M5 is obtained by subjecting the initial driving current I0 to a ratio determined by the second switching element M2 and the third switching element M3 in the mirror circuit formed by the second switching element M2 to the fifth switching element M5.
Further, referring to fig. 6 and 8, in the first time t1, the control terminal voltage of the seventh switching element M7, i.e., the sampling voltage VCS, rises from zero and is relatively small, and at this time, the switching control signal PULSE is at a high level, and after the high level switching control signal PULSE is subjected to the fixed PULSE width modulation, the high level is maintained for a short time, so that the sixth switching element M6 is turned on, and a driving current is output, where the driving current is a current obtained by the proportion of the initial driving current I0.
Meanwhile, since the control terminal voltage VCS of the seventh switching element M7 rises from zero and is relatively small at this time, the seventh switching element M7 is fully turned on, which causes almost all of the initial driving current I0 flowing out of the fourth switching element M4 to flow into the seventh switching element M7, and further causes almost zero current to flow into the eighth switching element M8, so that the current flowing through the tenth switching element M10 and the twelfth switching element M12 is almost zero.
Further, since the tenth switching element M10, the twelfth switching element M12, the thirteenth switching element M13, and the fourteenth switching element M14 constitute a mirror circuit, the current flowing through the thirteenth switching element M13 and the fourteenth switching element M14 is proportional to the current flowing through the tenth switching element M10 and the twelfth switching element M12, and in the case where the current flowing through the tenth switching element M10 and the twelfth switching element M12 is almost zero, the current flowing through the thirteenth switching element M13 and the fourteenth switching element M14 is almost zero.
Further, since the fifteenth switching element M15, the seventeenth switching element M17, the thirteenth switching element M13 and the fourteenth switching element M14 form a current path, the current flowing through the fifteenth switching element M15 and the seventeenth switching element M17 is the current flowing through the thirteenth switching element M13 and the fourteenth switching element M14, and in the case that the current flowing through the thirteenth switching element M13 and the fourteenth switching element M14 is almost zero, the current flowing through the fifteenth switching element M15 and the seventeenth switching element M17 is also almost zero.
On the other hand, since the fifteenth switching element M15, the sixteenth switching element M16, the seventeenth switching element M7, and the eighteenth switching element M18 constitute a mirror circuit, the current flowing through the fifteenth switching element M15 and the seventeenth switching element M17 is proportional to the current I3 flowing through the sixteenth switching element M16 and the eighteenth switching element M18, and the current flowing through the sixteenth switching element M16 and the eighteenth switching element M18 is almost zero when the currents flowing through the fifteenth switching element M15 and the seventeenth switching element M17 are also almost zero.
Further, as can be seen from fig. 6 and fig. 7, the driving current Idrv finally obtained by the current bias module 40, i.e. the first driving current I1, is after the current output by the sixth switching element M6 and the current output by the eighteenth switching element M18, and in the case that the current output by the eighteenth switching element M18 is almost zero, then the driving current Idrv output by the current bias module 40 to the driving module 50 at this time is only the current output by the sixth switching element M6, i.e. the first driving current I1 is only the current obtained by the proportion of the initial driving current I0.
Referring to fig. 7 and 8, in the first time period t1, after the twenty-third and twenty-fourth switching elements M23 and M24 receive the first driving current I1, since the PRE-off control voltage VCS1 is less than the reference voltage VCS-off, the switch control signal PULSE and the PRE-off control signal PRE-off are both high, so that the twenty-first switching element M21 is turned on by the high-level switch control signal PULSE, and the twenty-second switching element M22 is turned on by the PRE-off control signal PRE-off, so that the current flowing through the nineteenth switching element M19 is the sum of the first driving current I1 and the PRE-set driving current rv1, and since the nineteenth switching element M19 and the twentieth switching element M20 form a mirror circuit, the current flowing through the twentieth switching element M20 is proportional to the current flowing through the nineteenth switching element M19, that is, the twentieth switching element M20 amplifies the sum of the first driving current I1 and the preset driving current Idrv1 to obtain the current DRV, and at this time, since the control signal of the twenty-seventh switching element M27 is obtained by inverting the switching control signal PULSE, the twenty-seventh switching element M27 is turned off, so the driving module 50 can control the power switching tube M0 to be turned on according to the amplified current DRV.
In this embodiment, the sixth switching element M6 is controlled to be turned on in a short time, and then the current obtained by the initial driving current I0 in proportion is output to the driving module 50 as the driving current Idrv through the turned-on sixth switching element M6, so that the driving module 50 controls the power switching tube M0 to be turned on according to the current DRV obtained by amplifying the sum of the driving current Idrv and the preset driving current Idrv1, thereby realizing that a larger control current is provided to the power switching tube M0 in a short time, further shortening the on time of the power switching tube M0, and further reducing the energy loss of the power switching tube M0 in the on duration.
Further, referring to fig. 4, fig. 5 and fig. 8, during a second time period t2 after the first time period t1, the sampling voltage VCS increases slowly, and as the sampling voltage VCS increases, the pre-off control voltage VCS1 also increases. When the PRE-off control voltage VCS1 is always less than the reference voltage VCS-off, the switch control signal PULSE and the PRE-off control signal PRE-off are maintained in a state within the first time t 1; when the pre-off control voltage VCS1 rises to the reference voltage VCS-off for the first time and continues to increase, since the pre-off control voltage VCS1 is equal to the sum of the sampled voltages VCS and Δ Vb, the sampled voltage VCS does not rise to the reference voltage VCS-off at this time, and the comparison Signal output by the comparator COMP at this time changes from 0 to 1. When the comparison Signal output by the comparator COMP changes from 0 to 1, since the Signal LEB is 1 at this time, the PRE-off control Signal PRE-off output by the masking unit 302b changes from high level to low level at this time, and the switch control Signal PULSE continues to be high level.
Further, since the level of the sampling voltage VCS determines the conduction level of the seventh switching element M7, when the sampling voltage VCS received by the control terminal of the seventh switching element M7 slowly increases and is smaller than the reference voltage VCS-off, the conduction level of the seventh switching element M7 decreases, so that the current flowing into the seventh switching element M7 decreases, and the current flowing through the eighth switching element M8 increases, that is, the current flowing through the tenth switching element M10 and the twelfth switching element M12 increases with the increase of the sampling voltage VCS, and the current flowing through the thirteenth switching element M13 and the fourteenth switching element M14 increases, so that the current flowing through the fifteenth switching element M15 and the seventeenth switching element M17 increases, and the current flowing through the sixteenth switching element M16 and the eighteenth switching element M18 increases with the increase of the sampling voltage VCS.
In addition, although the switch control signal PULSE is still at the high level, the signal controlling the sixth switching element M6 has already been converted to the low level, i.e. the PULSE signal obtained by the fixed PULSE width modulation of the switch control signal PULSE has now been converted to a low level, therefore, the sixth switching element M6 is turned off, the current flowing through the third switching element M3 and the fifth switching element M5 cannot be output to the driving module 50 through the sixth switching element M6, and the current output by the sixth switching element M6 becomes zero, that is to say, the driving current Idrv output by the current bias module 40 is only the current output by the eighteenth switching element M18, that is, the second driving current I2 is only the current outputted by the eighteenth switching element M18, and after the driving module 50 receives the second driving current I2, and controlling the power switch tube M0 to be continuously conducted according to the second driving current I2 and the preset driving current Idrv 1.
In this embodiment, since the second driving current I2 is increased according to the increase of the sampling voltage VCS obtained according to the sampling current flowing through the power switch tube M0, the variable second driving current I2 is used as the driving current of the power switch tube M0 in the conducting phase, so that it is not necessary to always use a constant large current to drive the power switch tube M0, and the charge storage of the power switch tube M0 in the conducting process is reduced, thereby reducing the energy loss, reducing the supply of extra energy, and improving the energy utilization rate.
Further, referring to fig. 4, 5 and 8 simultaneously, since the PRE-off control Signal PRE-off changes from high level to low level when the PRE-off control voltage VCS1 rises to the reference voltage VCS-off for the first time, the first switch element M1 is turned off, so that the fixed current source Ia and the variable current source Ib are turned off from the comparator COMP, so that the PRE-off control voltage VCS1 is equal to the sampling voltage VCS, and the PRE-off control voltage VCS1 is smaller than the reference voltage VCS-0ff, so that the comparison Signal output by the comparator COMP changes from 1 to 0. When the comparison Signal changes from 1 to 0, since the Signal LEB is still 1 at this time, the PRE-off control Signal PRE-off output by the masking unit 302b still maintains a low level, and the switch control Signal PULSE still maintains a high level state.
Further, referring to fig. 6, fig. 7 and fig. 8, when the PRE-off control signal PRE-off is at a low level, i.e. a time period after the second time t2, although the driving current Idrv still exists in the current bias module 40 and is output to the driving module 50, under the low level of the PRE-off control signal PRE-off, the driving current Idrv received by the driving module 50 is turned off, i.e. the input current of the driving module 50 is only the preset driving current Idrv 1. In addition, since the switch control signal PULSE is continuously at the high level at this time, the twenty-first switching element M21 is turned on, so that the current flowing through the nineteenth switching element M19 becomes the preset driving current Idrv1 generated by the preset current source Id. Since the nineteenth switching element M19 and the twentieth switching element M20 form a mirror circuit, the current flowing through the twentieth switching element M20 is proportional to the current flowing through the nineteenth switching element M19, that is, the current DRV for driving the power switch M0 is proportional to the preset driving current Idrv1, and the twenty-seventh switching element M27 is turned off, so that the driving module 50 can control the power switch M0 to be turned on according to the current DRV.
In this embodiment, when the pre-off control voltage VCS1 reaches the reference voltage VCS-off for the first time, the power switch tube M0 is pre-turned off, that is, the driving current Idrv is turned off, and only the smaller pre-set driving current Idrv1 is used to drive the power switch tube M0, so that the charge storage of the power switch tube M0 before the formal turn-off is greatly reduced, the time spent in the formal turn-off of the power switch tube M0 is reduced, and the energy loss is reduced; in addition, when the power switch M0 is turned off in advance, the high state of the switch control signal PULSE is maintained by the shielding unit 302b, thereby preventing the power switch M0 from being turned off by mistake.
Further, referring to fig. 4, 5 and 8, when the PRE-turn-off control voltage VCS1 rises to the reference voltage VCS-off again, the comparison Signal output by the comparator COMP changes from 0 to 1, and since the Signal LEB is 1, the switch control Signal PULSE output by the shielding unit 302b changes from high level to low level, and the PRE-turn-off control Signal PRE-off continues to be low level; it should be noted that, when the pre-off control voltage VCS is equal to the sampling voltage VCS, that is, when the pre-off control voltage VCS1 is equal to the reference voltage VCS-off, the sampling voltage VCS is also equal to the reference voltage VCS-off.
When the sampling voltage VCS rises to be equal to the reference voltage VCS-off, that is, the switch control signal PULSE is at a low level, the current bias module 40 still outputs the driving current Idrv to the driving module 50, however, since the switch control signal PULSE is at a low level at this time, the twenty-first switching element M21 is turned off, the twenty-seventh switching element M27 is turned on, and thus the current DRV output from the driving module 50 to the power switch M0 becomes zero, and the power switch M0 is turned off. In this embodiment, since the power switch M0 is driven by a variable current during the on-state, and is turned off before being turned off, that is, driven by a small current before being turned off, the power switch M0 stores less charges during the on-state, and thus when the power switch MO is turned off, the off-state speed is increased, the energy loss is reduced, and the temperature rise of the power switch M0 caused by the energy loss is reduced.
Further, the invention also provides a power supply, which comprises the switching power supply circuit 1. It should be noted that, since the switching power supply circuit in the power supply provided by the embodiment of the present invention is the same as the switching power supply circuit 1 in fig. 2 to 8, the detailed description of the switching power supply circuit of the power supply provided by the embodiment of the present invention with reference to the foregoing fig. 2 to 8 may be referred to, and details are not repeated herein.
In the invention, when the switching power supply circuit charges the electric equipment, the signal generating module samples the current at the output end of the power switch tube, and generates a pre-turn-off control signal and a switching control signal according to a sampling voltage and a received reference voltage, the current biasing module samples the current at the output end of the power switch tube, and outputs a driving current according to the sampling voltage within the on-time range of the switching control signal, and the driving module drives the power switch tube according to different driving currents under the action of the on-control signal and the turn-off control signal, so that the power switch tube is driven by the variable driving current, the energy loss is reduced, the energy utilization rate is improved, and the problems of high energy loss and low utilization rate of the conventional driving method for the power switch tube in the switching power supply circuit are solved.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.