RU1837298C - Device for addressing data arrays - Google Patents

Abstract

The invention relates to computing, in particular to external memory control devices, and can be used to expand the address space of a microcomputer while addressing a data memory of an arbitrary serial nature. The aim of the invention is to increase the speed of the device. The goal is achieved in that the device comprises two registers, a decoder, two counters, a comparison circuit and a single-shot. 2 ill.

Description

The invention relates to computer technology, in particular to external memory control devices, and can be used to expand the address space of a microcomputer for addressing memory | These are data of an arbitrary sequential nature.

The purpose of the invention is to increase the speed of the device.

Figure 1 presents a functional diagram of the device; figure 2 shows the timing diagrams of the operation of the device.

The device comprises a processor unit 1, a decoder 2. the first 3 and second 4 counters, a memory unit 5, the first 6 and second 7 registers, a comparator 8, a single vibrator 9, information input-output 10 of the device. The processor unit 1 through the information input-output is connected to the information inputs of the second counter

4 and the first register 6, input - output block

5 pam te and input-output 10 of the device. The decoder 2 from the information inputs, where the address output of block 1 goes, determines the first address at its first output connected to the counting input of the first counter 3, the gating input of the comparator 8 and the sample input of the memory block 5, the second address at its second output connected with the sync inputs of the registers 6, 7 and the first input of the installation of the first counter 3 and the third address on its third output connected to the installation input of the second counter 4. The read and write outputs of block 1 are connected to the corresponding inputs of block 5 and gate odes of the decoder 2. The output of the first register 6 is connected to the first information input of the comparator 8 and the information input of the second register 7, the output of which is connected to the information input of the counter 3, the output of which is connected to the first address input of the unit 5 and to the second information input of the comparator 8, the output of which through a one-shot 9 is connected to the second input of the counter 3 record and the counter clock input 4, the output of which is connected to the second address input of block 5.

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Figure 2 marked: a-c - respectively, the first or third outputs of the decoder 2; g, d - write and read signals of processor unit 1; e is a match interval of input operands of comparator 8; g - the output of the comparator 8; C - output single-vibrator 9.

The following sections are additionally indicated: 1 - initialization of counters 3.4 and registers 6, 7 before information exchange with memory; II - the beginning of writing / reading the first line of the fragment; III - write / read the last two elements of the fragment line; IV - write / read the next line.

The device operates as follows. .

The memory unit 5 stores an informational array with a dimension of 256x256 elements. It is addressed horizontally by an 8-bit counter 3. vertically by an 8-bit counter 4. The upper left element of the array is addressed by the null values of counters 3, 4. The transmission of elements of a rectangular fragment of the array is performed in the order from left to right, from top to bottom. Before transferring the elements of the fragment, the processor unit 1 initializes the counters 3, 4 and registers 6, 7. He sequentially selects their attributes from the stack of his system memory and stores them in the indicated counters and registers, first indicating the address A3, then three times A2. As a result, four bytes of the fragment attributes selected by the processor unit 1 from the stack are sequentially output to the information bus 10: first, the byte ULV, followed by address A3, then twice by Chlv, then Xn, followed by address A2. The output information is gated to the output of the recording (Fig. 2d, 1), which is processed by the third and then the second outputs of the decoder 2 (Fig. 2a, b, 1).

At the end of the initialization process: the coordinate Xn of the right column transmitted by the rectangular fragment is stored in register 6; in register 7, counter 3 - coordinate Hlv of the upper left element of the transmitted fragment; in counter 4, the Ulv coordinate of the upper left element of the transmitted fragment. The processor unit 1 proceeds to the sequential exchange of bytes of the indicated fragment with the memory unit 5; it sets the address A1 to which the first output of the decoder 2 corresponds.

The first output of decoder 2 activates the memory unit 5 at the EN input. by the activity of a write or read signal (WR, RD) by connecting the input or output of block 5 to bus 10 (Fig. 2c, d, d. II). Upon completion of reading-writing of the next element in the memory block 5, the counter 3 is incremented, to the address of the next element of the fragment along the line. The last element of the fragment line

it is determined on the comparator 8 (fig.2e, g, III), the pulse from the gated output of which with its trailing edge triggers a single-vibrator 9 (fig.2z, III), which records the coordinate Chlv on the second input of the record in the counter 3 from register 7 the left column of the fragment, and increments the counter 4 along the counting input. As a result, the counters 3, 4 address the leftmost element of the next row and the pumping process can be

continued (figure 2. IV). After miscalculation by the processor unit 1 of all the transmitted elements of the fragment, the pumping process ends.

Formulas of the invention

Array addressing device

data containing register decoder

and two counters, and the input of the operation mode of the device is connected. to the information input of the decoder, the first and second gate inputs of which are connected respectively to the read and write inputs of the device, the first output of the decoder is connected to the counting

the input of the first counter and the output of the gating access to the device memory, the second and third outputs of the decoder are connected respectively to the first recording input of the first counter and to the recording input

the second counter, the output of which is connected to the output of the address of the column of the array of devices, the output of the first counter is connected to the output of the address of the string of the device array, the input of the parameters of the addressed array of the device is connected to the information input of the second counter, characterized in that, in order to improve performance, a register, a comparison circuit and a one-shot are introduced into it, and the input

parameters of the addressed array of the device is connected to the information input of the first register, the output of which is connected to the information input of the second register and to the first information input

the comparison circuit, the output of which through a one-shot is connected to the second recording input of the first counter and to the counting input of the second counter, the output of the second register is connected to the information input of the first counter, the output of which is connected to the second information input of the comparison circuit, the gate input of which is connected to the first output of the decoder, whose second output is connected to the sync inputs of the first and second registers.