RU1837273C - Device for sorting data - Google Patents

Abstract

The invention relates to computer technology, and in particular to information input / output devices using EC computer interfaces. An object of the invention is to increase speed. The device contains switches 1-3, input registers 4, 5, a subscriber signal generating unit 6, an And 7 circuit, a reference memory unit 8, a decoder 9, a channel signal generating unit 10, a multiport memory unit 11, a comparator 12, a generating unit 13 memory signals, switches 14, 15. 10 ill.

Description

The invention relates to computing, and more particularly to information input / output devices using EC interfaces of computers

The aim of the invention is to eliminate

e the above disadvantages.

The essence of the invention lies in the fact that the device for sorting data, containing the first to fifth switches, a memory unit of standards, the first and second input registers, a comparator, a decoder and element And, the first information input of the device coming from the channel, It is connected to the first information inputs of the first and second switches, to the information input of the first register and to the first input of the element I. The first input of the device data attribute output from the channel is connected to the first information input of the third switch ora and to the second input of AND, whose output is connected to an input of the decoder. The output of the first switch is connected to the information input of the second input register. The outputs of the first and second input registers are connected respectively to the information input of the reference memory unit and to the first input of the comparator. The second information input of the device coming from the subscriber is connected to the first information input of the fourth switch and to the second information input of the first switch. The second input of the device data attribute output from the subscriber is connected to the first information input of the fifth switch. The outputs of the second, third, fourth and fifth switches are connected respectively to the first information output for the device subscriber, to the first data flag output for the device subscriber, to the second information output for the device channel and to the second data flag output for the device channel, the following are input: subscriber signals; channel signal generating unit.

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a multiport memory signal generating unit; and a multiport memory unit. The output of the reference memory unit is connected to the first information input of the multi-port memory signal generating unit, the first output of which is connected to the second input of the comparator, the output of which is connected to the first input of the multi-port memory signal generating unit mode, the second output of which is connected to the first inputs of the forming unit mode subscriber signals and a channel signal generating unit. The outputs of the first group of the multiport memory signal conditioning unit are connected respectively to the address input, read and write inputs of the reference memory unit. The outputs of the second group of the multiport memory signal generating unit are connected respectively to address inputs, to the writing and reading inputs of the multiport memory unit, the output of which is connected to the first information inputs of the aboneitis signal generating unit and the channel signal generating unit. The output of the second input register is connected to the information input of the multiport memory. The first information input of the device leaving the channel is connected to the second information inputs of the multiport memory signal generating unit, the channel signal generating unit and the subscriber signal generating unit. The first input of the data attribute from the device channel is connected to the first control inputs of the subscriber signal generating unit and the channel signal generating unit. The second information input of the device coming from the subscriber and the second input of the device data attribute coming from the subscriber are connected respectively to the third information and to the second control inputs of the channel signal generating unit. The first output of the channel signal conditioning unit is connected to the first control inputs of the second and third switches. The second output of the channel signal conditioning unit is connected to the first control inputs of the fourth and power switches. The first output of the subscriber signal conditioning unit is connected to the second control inputs of the second and third switches. The second output of the subscriber signal conditioning unit is connected to the second control inputs of the fourth and fifth switches. The third outputs of the subscriber signal conditioning unit and the channel signal conditioning unit are connected respectively to the first and second control inputs of the first

switchboard. The outputs from the fourth to eighth block of the channel signal generation are connected respectively to the second information inputs of the second and third

switches, to the second and third inputs of the multi-port memory signal generating unit mode and to the output of the device interrupt sign, the input of the initial blanking sign of which is connected to

the second inputs of the mode of the subscriber signal generating unit and the channel signal generating unit and to the fourth input of the multi-port memory signal generating unit mode. The first, second and third outputs of the decoder are connected respectively to the third information input of the subscriber signal generating unit, to the fourth and fifth information inputs of the block

generating channel signals. The outputs from the fourth to ninth subscriber signal conditioning units are connected respectively to the write-read input of the first input register, to the fifth mode input

a multiport memory signal conditioning unit, to the second information input of the fourth switch, to the second information input of the fifth switch, to the sixth and seventh mode inputs

a multiport memory signal conditioning unit. The ninth output of the channel signal conditioning unit and the tenth output of the subscriber signal conditioning unit are combined using a wired OR

and connected to the eighth input of the multi-port memory signal conditioning unit mode.

The following devices were introduced in the inventive device: a multi-port memory block and blocks for generating subscriber, channel and multi-port memory signals, which, together with other nodes, allow expanding the scope of the possible application of the device by working with faster subscribers, as well as increasing device performance compared to the prototype.

Significant differences are that the introduced nodes: multi-port memory block and blocks for generating subscriber, channel and multi-port memory blocks give new opportunities - they allow: - coordination of different types of EC computers (for example, between the subscriber and the proposed device streaming data is used, and between the computer and the proposed device with interconnected request and response signals);

- coordinate the speed data of the subscriber and the channel (for example, the transmission of information between the subscriber and the proposed device can be performed at a higher rate than between the device and the feces).

Thus, the use of the above blocks expands the class of resources working with this channel.

In addition, in a number of cases, it is possible to increase the distance between E1 M and the subscriber by dividing the total length between these devices into two parts: the channel — the proposed device and the proposed device — the subscriber.

In this case, the length of each part of Definition 1 is determined by the type of interface used and the maximum delays of the subscriber, the proposed device and channel.

The invention is illustrated in the figures: Figs. 1a, 16 is a block diagram of the device of Figs. 2a, 26 is an example of a specific embodiment of a subscriber signal generating unit (BSA6); Fig. Za, 36 is an example of a specific embodiment of a multiport memory CHI block generating unit (BSP 13); fi A - time diagram of the BSA 6 with the command MANAGEMENT; 5 is a timing diagram of a BSA b operation. transferring information from the channel to the proposed device; 6 is a timing diagram of the operation of the BSA 6 when transmitting information from the proposed device to the channel; Figures 7a, 76 are an example of a specific embodiment of a channel signal generating unit (BSK 10); Fig. 8 is a timing diagram of the operation of BSK 10 when transmitting information from a subscriber to the proposed device; Fig.9 is a timing diagram of the operation of the BSK 10 when transferring information ({formations from the proposed device to the user; Fig.10 is an example of a specific implementation of the multi-port memory unit

(fi

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A data sorting device, hereinafter referred to as a device, is presented) in FIG. 1a, 16 and contains the switches (Km) 1, 2, 3, the first input register (RgVh) 4, the second input register (RgVh) 5, the unit for generating subscriber signals (BSA) 6, circuit I 7, b ; memory of standards (OPET) 8, decoder (DS) 9, channel signal generating unit (BSK) 10, multiport memory (OHii / in) 11, comparator (COMP) 12, memory signal generating unit (BSP) 13, switches 14 and 15.

The first input of Km is connected to the first inputs of the device, circuitry I 7, Km 14, BSA 6, B Zh 10, BSP 14 and PrgVX 5. The second input of Km 1 is connected with the second inputs of the device, BSK 10 and the first input of Km 2 . Third and

the fourth inputs of Km 1 are connected respectively to the first outputs of BSA 6 and BSK 10. The output of Km 1 is connected to the input of PrGx 4, and the output of the latter is connected to the first inputs of 5 OMPP 11 and IKOMP 12.

The second input of the And 7 circuit is connected to the third inputs of the device, BSK 10, the first Km 15 and the second BSA 6 input. The output of the And 7 circuit is connected to the DS 9 inputs, and 10 of the outputs of the latter are connected to the third BSA b input and the fourth BSK 10 input,

The second input Km 14 is connected to the second output of the BSK 10, and the output DKDm 14 - with the first output of the device. 15 The second input of Km 15 is connected to the third output of BSK 10, and the output of Km 15 is connected to the second output of the device. The third inputs of Km 14, Km 15 are connected to the second output of BSA b (1UPR Km 14, 15), and the fourth inputs of Km 14, 0 Km 15 - with the fourth output of BSK 10 (2UPR Km 14, 15).

The inputs from the 2nd to (3 + 1) OPM 11 are connected to the first output of the BSP 13, and the output of the OPMP 11 is connected to the fourth input of the BSA 5 b and the fifth input of the BSK 10.

The second input of PrgVx 5 is connected to the third output of BSA 6, and the output of PrgVx 5 is connected to the first input of OPET 8. The second, third, and fourth inputs of OPET 8 are connected to the second output of BSP 13, and the output of OPET 8 is connected to the second output of BSP 13 .

The second input of the COMP 12 is connected to the third output of the BSP 13, and the output (1-) of the COMP 12 is connected to the third input of the BSP 13. 5 The second input of Km 2 is connected to the fourth output of the BSA 6, and the output of the first to the third output of the device.

The first input of Km 3 is connected to the fourth input of the device and the sixth input of BSK 10, the second input of Km 3 is with the fifth output of BSA 6, and the output of KM is the third fourth output of the device. The third inputs of Km 2, Km 3 are connected to the sixth output of BSA b (1UPR, Km 2, 3), the fourth inputs of Km 2, Km 3 - with the fifth output 5 of BSK 10 (2UPR, Km 2, 3).

The fifth input of the device (HIGH. From KH) is connected to the fifth input of BSA 6, the seventh input of BSK 10, and the fourth input of BSP 13.

The fifth output of the device (PREP) is connected to the sixth output of the BCS 10.

The seventh outputs of BSA 6 and BSK 10 are connected to the fifth input of BSP 13.

The eighth output of the BSA 6 is connected to the sixth input of the BSP 13.

5 The ninth output of BSA 6 is connected to the seventh input of BSP 13. The tenth output of BSA 6 is connected to the eighth input of BSP 13.

The eighth output of BSK 10 is connected to the ninth input of BSP 13. The ninth output of BSK 10 is connected to the tenth input of BSP 13. The fourth output of BSP 13 (KO) is connected to the eighth input of BSK 10 and the sixth input of BSA 6.

It is contemplated that the device is implemented on the elements of the 133 series.

When constructing circuits, various types of triggers are used.

Firstly, a trigger type 133TM2. This flip-flops have an information input T, a sample input C, and a setup input of zero

Secondly, trigger groups (which we also call triggers for simplicity of description).

These triggers are based on 133TM2; their setting to 1 and O is performed on the corresponding signal fronts. In this case, the left input of the trigger corresponds to the setting in G, the right - in O. Accordingly, the left output is single, the right one is zero.

The sign near the trigger indicates that the latter is triggered by the rising edge of the signal, the sign - by the falling edge of the signal.

When describing the operation of the proposed device, the abbreviations are used: SHI.N-Kk - channel bus exiting the channel; ISK-a - tracking pulses from the channel to the subscriber (identification lines used to determine the type of data located on SHIN-Kk, as well as the control line); SHIN-Ki ISK - corresponding to the above tires and lines on the input. to the subscriber; SHIN-Aa - subscriber buses leaving the subscriber; ISD-k - follow-up pulses from the subscriber to the channel (identification lines used to determine the type of data located on the SHIN-Aa, as well as the control line from the subscriber); ShMN-A and ISD - corresponding to the above described bus and line at the input of the channel.

The remaining abbreviations are deciphered in the description of the corresponding nodes. Pulses of tracking at the inputs of the proposed device are synchronized with pulses of internal frequency (SI). The SI generation unit, as well as the tracking pulse synchronization units, are not shown in the accompanying figures.

Sorting is performed using the comparator 12 (see Fig. 1a, b, 3a, 3b), which compares information from the channel million from the subscriber with the code on the gate and mask register (VOM). Depending on the information generated in the comparator, coming from a channel or subscriber is recorded at one or more addresses of the RF multi-port memory OPM 11, in which each gate has its own recording port.

The proposed device can be used to sort data organized as an array (scalar recording mode), or in the form of vectors (vector recording mode),

At the beginning, it is necessary to enter the initial information from k, and into the registers of the starting addresses of the record (1 START ADDR. 62 - START ADDRESS 63).

0 Consider entering the initial value in, for example, in Pr1 START ADR.62 (in all other registers, the information is entered in the same way).

See, figa, b, 23,0,33,6, 4. 5 The subscriber’s address code transmitted via ShII-K and followed by the ADR-K identifier contains eight bits.

For the proposed device, two left-hand bits determine the information transfer mode 0: 01 is the first mode in which an exchange is made between the channel and the proposed device; 10 and 11 are the second mode in which an exchange is made between the subscriber and the proposed device 5, where code 11 corresponds to transmission from the subscriber to the proposed device, and code 10 corresponds to reverse transmission; 00 - the third mode, information and control signals come from the channel to the subscriber and 0 (or) from the subscriber to the channel directly. So, let the code 01000000 be transmitted on the SHIN-KK, at this moment the DAR-K line is at a high level. This information is transmitted through I 7 to DS 9 and, in the form of a signal, 5 enters the subscriber signal block (BSA 6).

This signal sets the n 1 trigger of the first mode (Tg1P42). The Km14 and Km15 switches are closed from the latter through the first encoder (1Sh52) (at zero outputs of the indicated switches, equivalent zero), and through the second encoder (2Sh35), the Km2 and Km3 switches are opened at the first input, i.e. the outputs of the latter are received respectively by SHIN-Ad and from BSAO. 5 In addition, Tg1R42 through And 56 allows the reception of ISK-a signals from the channel to the internal BSAb nodes,

Then VBR-K comes from the channel, which sets in 1 TgRAB-A27 and through 0 KmZ and the channel is transmitted to RAB-A. From the front edge of RAB-A, ADR-K is dropped in the channel, from the rear edge of which is set to 1 Tg ADR-A29, which, through OR 38, generates code 01000000. 5 sent to SHIN-Aa. With some delay determined by the delay line L337, ADR-A is generated.

In response to ADR-A, UIR-K is generated in the channel, and the CONTROL command is set on SHIN-Ka.

On the leading edge of UPR-K, this command is received in the command register (egKOM31) and through DSh39 it generates a signal of UPR coming to I 44, I 45.

On the trailing edge of the UPR-K through And 23 it is installed in GTgUPR-Ap 32, the signal from which through the OR 40 and L341 the E channel enters in the form of UPR-A. On SHIN-Aa, at this moment the level is low, which corresponds to the status byte zero. In response to the UPR-UA, the channel generates INF-K, on the leading edge of which Tg UPR-Ap 32 is set to O.

On the trailing edge, INF-K via I 34 and L349 is set to 1 TgINF-Au 53. The latter is flashed by the front wall of INF-K via OR 51.

On the trailing edge, INF-K is set to {tc in G trigger transmission (Tg gear 43).

In the zero state of the end-of-exchange trigger (1Tg, end exchange 43), for each INF-K, a reception permission signal (EASR.PR) is generated through the reception permitting circuit (AND 44) E. The indicated signal with a part of the bits of PrgCOM.31 (NPEf). defining, in which exactly the register will be entered; information is received at the input of BSP13.

BSP13 signals and REG number are received at ДШ88, in which a reception signal is generated in the corresponding register. (In our case - in 1 START ADR.62). Information in the register comes from SHIN-Kn. .

The register enable signal (IP. In REG) also performs a shift in the register.

This continues until the necessary information is completely entered in the corresponding register and (knew determines the end of the exchange,

In this case, in response to INF-A, a UPR-K is generated in the channel, through the front side of which through OR 18, And 26 is set to 1 trigger for the end of the fraud (1Tg.KON.OBM. 34).

In this case, the reset of Tg INF-Au 53 is performed on the leading edge of the UPR-K via I 48, OR 51. On the trailing edge of the UPR-K through OR-NOT 17. L320, And 24 is set to 1, Tg UPR-Ao 33 and through OR 38, the CHANNEL END (QC) code is transmitted to IN-Aa, and the signal UPR-A is transmitted through OR 40, LZ 41. 1о UPR-A in the channel, a VBR-K discharge occurs and INF-K is generated, along the front side of which Tg RAB-A27 is reset through OR 17, 19 and Tg PR-AoZZ through OR 25, From the trailing edge of the signal from Tg AB -A27 through L321, L322 a pulse signal of the initial blanking is generated (Tg START.GASH 1 28), which through And 36 in the form

GAS1 signal arrives at the zero setting TMP42, Tg. TRANSMISSION 43, Rg.KOM.31, 1Tr.KOH.05M.34.

Thus, in register 1 START ADR.62 5 the necessary information from the channel is entered.

Information is also entered in other registers in a similar way.

Consider now passing an array

Yu data from the channel to the proposed device using sorting (scalar recording mode),

The entire interchange of interdependent signals is carried out similarly as described above. The timing diagram for this mode is shown in Fig. 5.

On DS39, instead of the CONTROL command, the RECORD command is decrypted.

0 in the case of each INF-K in the transmission mode through AND 58, a 13POP signal is generated, which is received through the switch (KM66), open at the first input (1UPR.km6b, 67 - high, 2UPr Kmbb, 67 - low)

5 on LH ZPOP84. Together with the 13POP signal from RG.KOM 31, the following are received: 1DU (additional instructions defining in this case the scalar recording mode), as well as the state of 1 Tg.con.obm. 34.

0 At the same time, information on the SHI-KK is received in the first input register (Pr ВХ4) through KM1, open at the first input (1 KmG SEC - high, 2 Km1 SEC - low). Information at the output of PrgX4 5 repeats the information at the output of Km1.

The information at the output of Prgx4 is repeated. It produces information at the output of Km1.

Information is recorded in a multi-port memory (OMP11) by

0 to the corresponding address (or several addresses). The information input of this memory is common to all ports and is connected to the output of PrVX 4.

This memory has j ports (1-J), in

5 it receives j addresses (1 ADR. - j ADR.); recording features (13P - j RFP) and the same number of reading features (1 CH - J CH).

The information from PrVX4 supplied to the first input of the comparator is compared to

0 last with the one that goes to its second input. In this case, this will be information from the first register of gates and masks (1BOM73), coming through Km76 (Signal. VECT.ZP. arrives at a low level).

5 As a result of the comparison, at the output of COMP.12 one (or several) of the signs 1 - J is generated, which are sent to the DVP ZPOP 84. In addition to these signals, the recording mode signals (scalar recording is also high, vector recording is low) )

A high level of recording permission occurs at the output of the DSA RCHP 84 on those wires 13P-j of the ZP that correspond to the allowed recording ports.

The recording addresses are formed on the recording adders (1 2) ЗП77 - jЈ ЗП48), on each of which three values are summed - the starting address (1START ADDR.62 - J START ADDRESS 63), the vector counter (1 СЧАВКТ68 - j Сн. VEKTBE) and recording counter (1 Sc.ZP74 - j Sc.ZP75).

Note here that the record counters are in the zero state and do not take part in the formation of the record address in this mode.

The outputs of the recording adders go to the first inputs of the address switches (1KM. ADDRESS86 - j Km.ADR87), controlled by the outputs KmZPbb and KmCht67.

In our case, the address switches open at the first input. Thus, the write addresses are received in OPMP11.

Signals 13P - j of the RF input are also sent to the vector counters (1 Count BEC. 68 - j Count BEC. 69) and the contents of the respective counters are increased by 1 on the trailing edge of the signal, thereby preparing recording addresses for the next call. The ending sequence is similar to that described above.

After the end of the scalar recording mode, the entire data array transmitted from the channel was said to be sorted to the corresponding addresses in OMP11, and the start addresses of each such subarray are contained in the start address register (1 START ADDR. 62-J START ADDRESS 63), and the number of recorded array elements is in the vector counters (1 Sc. VEK. 68-J Sc. VEK. 69).

Let the task now be - to transfer the sorted data array from OPMP11 to the channel. By the READ command, one subarray is transmitted to the channel.

A timing diagram of the operation for this case is shown in Fig. 6.

Initial sampling is performed as described above.

On DS39, the READ (THAT) command is decrypted. Through AND 47, on the trailing edge of INF-K, an INF-A reading trigger (TGINF-A cht55) is installed in H1, through which through I 57 1 PSTN is generated, which passes through Km ChT 67 to the LH ChTOP 85 (see Fig. 3.6 )

Together with signal 1 PT.OP with Pr.KOM31, No. 1 is transmitted - j is the port number from where information should be transmitted to the channel.

At the output of the DShCHTOP85, a high READING resolution level occurs on one of the wires 1HT - j TH, whose number is indicated in No. 1 - j.

Reading addresses of ports (subarrays) are formed on READERS (1 Th89 j 2 Th90), on each of which two values are added - the starting address (1 HIGH ADDR. 62 - j HIGH ADDR. 63) and the counter for reading (1 sec. ЧТ92 - j СЧ ЧТ.93).

The outputs of the read adders go to the second inputs of the address switches (1 Km.ADR.vb-j KM ADR.87), controlled by the outputs of Km ЗП66 and КМ ЧТ 67. In this example, the address switches open at the second input. In this way, read addresses are received in OMP11.

The 1HT - JTh signals also go to the read counters (1 C4. Count CHT.93) and increase the contents of the corresponding counters by 1 on the trailing edge of the signal, thereby preparing the read addresses for the next.

Information read from OPMP11

enters through AND 30, OR 38 on SHIN-Aa.

From the front front of Tg INF-A ChT 55

through LZ 59, OR 60, INFA is produced that enters the channel. Delay LZ 59

selected from the calculation, so that INF-A by vils would have later information on SHIN-Aa.

On the leading edge INF-K, the TG and NF.-A read 55 are dropped.

Such a sequence of signals continues until the entire specified subarray is transmitted to the channel.

. In the comparison schemes (1 CPA7 80 - j CPA.81), the write end address is compared with the current read address for each subarray. When equality occurs, the PABHO signal (1P-j P) occurs, which arrives at the LH GAS. 94. at the output of this decoder, the END OF EXCHANGE (QoS) signal arrives at OR 18. According to the Qo, the end sequence begins,

In addition, a blanking signal (1 GAB - J GAB) is set up on the GAS GAS 94, which sets the corresponding counters in O (Mid-Century 68 - J Mid Cent. 69; 1 mid-season ZP 74 - j Mid-Port 75) 1 Mid-Thu 92 - j Mid Thr 93).

On the leading edge of the CO through OR 18, AND 26 is set to 1 Tg KOH. OBM. 34.

In this case, on the falling edge of INF-K, through the OR-NOT 17, LZ 20, And 24, the UPR-A end trigger (Tg UPR-AoZZ) is installed in the unit, which, through OR 40, LZ 41, generates the UPR-a signal, and through OR 38 it transmits to SHIN-A, and the CHANNEL CODE ENDED (KK) code.

According to the signal UPR-K, developed in the channel in response to UPR-A, VBR-K is triggered, h (RES 16, AND 19 is set to zero Ti RAB-A27.. OR 25 through the front dash of the UPR -K is set in O T g USCHR-AoZb.

Consider the organization of the recording mode.

In this case, the code in the register of gates and masks comes from the memory of the standards (OP ET 8) | in which he had previously been placed on command of the RFP OP ET.

Then, at the same time that the vector element is received in PrVX4, the code from OP ET 8 is read into register 2BOM61. The Km76 switch is open at the second input (that is, the mode (torus recording) is specified and the indicated codes are sent to COMP12.

Due to the fact that in the general case the address of the vector number is only displayed at the end

from ve Wed |

for ne pr ve wa for di gd from to

broadcasts (according to the last component), and the following torus sorting algorithm — each vector element is written to all the recording addresses of ports 1-j, and then, after the end of the vector, the addresses of the ports are adjusted: there are accumulated signs from COMP12 do not meet the comparison condition, the addresses of the items are corrected. Note that at the beginning, the recording of information from the channel into the memory of standards 8.

You perform signal generation in BSAB similarly to the above-described high-speed recording mode; new IDU indicates the sign of recording in the OP ET.

This sign through KmZPbb arrives at Sch.ADR.ET 70, I79 and DShZPOP 84.

For each 13P OP through I79, OR82, a unit is added to the address estimator to modify the write address,

LH ZPOP 84 in this mode is blocked and 13P - j ZP are identically equal to zero. From I79, in OPET8, a signal of the ET ET is received, from SCH.ADR.ET 70 - the address of the OPET, with X5 - information from the channel. The information at the output of PrgWhB repeats the information at the input of this register at high

OP

Rge

QI5 Qing

uro

Op ok

Signal Р.2РгВх.

Thus, recording is done in

) T 8, and multiport memory OPMP 11

called blocked.

After transferring the entire array, at a high level with 1 Tg. CON.OBM. 34 Count / 1DR.ET70 is set to zero

ny (UO).

At this point, the recording mode in OPET8 ends.

(We now consider in more detail the vector recording for information

pulling out of the channel.

Signal generation in BSA6 is carried out similarly to the scalar recording mode described above, but the sign of vector recording is indicated in DN1. This symptom (VECT.ZP) 5 is supplied to I72, the accumulator of signs (NAKOP, PR83), Km76, DSh GASh 94, DSh U O 95, DSh PC 96, DSh ZP OP 84.

By the signal 13POP from BSab to DSH ZPOP84, all the signs of 13P - ZP are generated simultaneously 0 and information is recorded in OPI11 from PrgVX4 simultaneously to all addresses 1 of the ADR. - j ADRs. After that, units are added to all the vector counters (1 C4.BEK.68-j Sc. VEK.69) using signals 13P - 5 jP, thereby modifying the recording address,

Through AND 2, a unit (+1 CEC) is added for each recording signal to the vector length counter (Count LON. CEC 71). The same 0 signal is used as a read signal from OPET8 (CHT and OPET), and through OR 82 it is sent to the modification of SCH.ADR.ET70,

Information from OPET 8 is received in the register 2BOM61 and through Km76, the second operand to COMP12 arrives as 5.

This continues until the contents of Rx.L.D.E.C. 71 are compared with the contents of Pr.DL.VEK 65. In this case, the signal END OF VECTOR 0 (KB) is generated, which is transmitted to .OP.PRZZ, LH PC 96 and through LZ 91 on LH U O 95.

On the PC 96, the accumulated features for the transmitted vector are analyzed, and where these features are equal to one (i.e. 5, the vector satisfies the conditions of comparison), the contents of the vector counters (1 Count BEC 68 - J Count BEC 69) are added to the contents of the recording counters (1 Sc.ZP74 - J Sc.ZP 75). This addition is accomplished by resolving the 1-J RSDSD PC 96.

After such an addition, with some delay determined by LZ 91, all vector counters are reset to zero by signals 1 - V О with ДС У О 95.

5 Thus, upon completion of the recording of each vector in OPM11, the write addresses are corrected (1 ADR - j ADR) for the next vector.

Let us now consider the exchange of information of the proposed device with the subscriber.

At the beginning, the subscriber is configured to work with the device. So for disks, such a setting can consist of entering heads, searching for a zone by identifier, etc. In this case, the channel transmits a control command to the subscriber, and the interdependent signals are exchanged strictly in the REQUEST-RESPONSE mode (see Fig. 1a, b, 7a, b).

In this case, at the same time as the ADR-K signal on the SHYN-Kk channel, it sets a code containing 00 in the left bits.

A signal 0 is generated at the DS9, which enters the BSK10. Here he sets the trigger of the third mode (TgZR127) to 1, which through 1Ш134 opens Km14 and Km 15 at the first entrance, and after 2Sh120-Km2 and KmZ at the second entrance.

Thus, SHIN-Ka and SKK-a directly go to the subscriber (from the channel), and SHIN-Aa and ISD-to the channel (from the subscriber). In this case, the exchange is carried out strictly according to 3.

Consider now the transmission of information from the subscriber and the recording in OPMP11 of the proposed device (see Fig. 7a, b, 8).

The ADR-K signal is transmitted from the channel along one of the SCK-A lines, and via the SHIN-Kk signal, an air signal containing 11 bits in the left (senior) bits.

On DS9, signal 2 is generated, which enters BKS10, where it is set to 1 trigger of the second mode (Tg2P 126).

At the same time, the command code (11) is stored in the command register (PgCOM. 135), and the subscriber number is stored in the address register (Pg.ADR.104).

At the output 1Sh134, a signal 2UPR Km 14, 15 appears, switching Km14 and Km 15 to the second input.

At the output 2Sh 120, a signal 2UPR Km 2, 3 appears, switching Km2 and Km3 so that the outputs of the latter are set to a low level.

After this, the channel functions are performed by BSK 10; information on SHIN-KK and ISK-a is sent to the subscriber; on SHIN-A in ISD in the channel - zeros.

From Tg 2P126, TgADR-K 103 is triggered. Through I114, OR115, the subscriber's address (number) is sent to SHIN-KK, and the ADR-K identifier is sent through LZ 113 to ISK-A1.

From Tr 2P 126 with a certain delay determined by L397, Tg VBR-K 102 is triggered, the output of which in the form of a VBR-K signal is fed to ISK-d1

In response to VBR-K, the subscriber receives a signal RAB-A, from the leading edge of which TgADR-K 103 is triggered. In response to the falling edge of ADR-K, the subscriber answers ADR-A and the subscriber’s address (number) is set to SHIN-Aa, to which reference is made. Through I99 this address goes to the first input of the adder (Ј Ј 9), the second input of which is connected to PrGADR 104. and the third (allowing) to Tr2R 126.

If the address of the call to the subscriber matches the response address (from the subscriber), a high level occurs at the output - X 109. On the leading edge, ADR-A through LZ 108 is set to 1 Tg UPR-Kp 117. The delay value of LZ 108 is determined by the time necessary to calm the transients.

If the above addresses do not match at the output Ј 109 - a high level and this signal is sent to the interrupt.

0 G of the output of Tg UPR-Kp 117 through H1Q6, OR115 the RECORD command is transmitted to the SHIN-Kk. The second input I106 is connected to the DSh136, which turns the conditional form of the command into the form that the subscriber perceives 5.

The signal from the output of Tg UPR-Kp 117 through IL И123 in the form of UPR-K arrives at ISK-d. ADR-A is reset on the leading edge of UPR-K, the leading edge 0 of which Tg UPR-Kp117 is set to O, From the trailing edge of UPR-K, the subscriber is set to 1 UPR-A and the status byte is set to SHIN-Aa . On the status byte decoder (ДС BS 130), 5 UPR-Aa and a signal from the zero output 2Tg KOH.OBM.116 (if there is no end of the exchange, the last output is high) are received.

If the status byte received from the subscriber is zero, the output O is a high 0 level.

On the front front of the UPR-A through the LZ

129, the delay of which is selected from the condition

tranquilizing the transition in

DShBS130, through I137, OR142, signal

5 INF-K enters ISK-d.

From the leading edge, INF-K resets UPR-A from the subscriber, from the falling edge of INF-K preparation (INF-Kp) it is set to 1 transmission trigger (Tg BEFORE 128), 0 This completes the initial sampling and starts transmitting data.

The subscriber generates an INF-A signal on the IS-AK, and on the SHIN-Aa, information from the subscriber is displayed. The inputs I131 5 receive signals: RFP with DSh136, INF-A from the zero output TgKON.OBM. 116. From the I131 output, the 23POP signal is fed to the input of the BSP 13. In this case, the signal 2 of the control amplifier Kmbb is a high-level signal (mode two has been decoded) and the signal 23 of the OPP is recorded in OMP11. Together with the 23POP signal, additional indications (2DE) are transmitted to the BSP13, defining the vector or scalar recording mode, as well as the state 5 2 ТгКОН.ОБМ. 116.

With a certain delay determined by the setting of LZ 139, INF-K is generated through OR142, which arrives at ISK-a1. The amount of delay LZ 139 is determined by the end of the writing process to the memory.

On line 2 UPR Km1 - high level, n 1 UPR Km - low.

The high level 2 of the control loop Km1 is determined by the single state of the trigger of the second mode (Tg2P 126).

In this case, the information from SHIN-Ae through I m1 goes to the input register PrAx4, and then to KOMP12 and to OPM11 (to the information and ion input of the latter).

Then, actions similar to those described above are performed (when recording from a channel).

After some time, determined by the caller, INF-A reappears, and information from the subscriber appears on L JHH-Aa.

The process of writing to and in OMP11 continues until the transmission array is completed.

In this case, the subscriber generates PR-A on ISD-k at the last INF-K on its highest front, and information on the SHIN-A is set to CHANNEL FINISHED ((K) - at the normal end of the exchange.

On the leading edge of the UPR-A through LI98, I107, the mouth merges into 1 trigger of the exchange end (2 Tg.KON.OBM.116). Note that the other inputs on I107 - the second mode and Tg PER are high and They are charged with Tg2P12b and gpered128, respectively. Through I-NOT 94 at high levels of UPR-A and 2Tg KON.OBM.116, the TGVBR-K102 is reset.

At the end of the channel decoder (LH KK 33), a high level is established at the output of the QC, if the KA-AL code has finished via BUS-P, otherwise a high level is set at the output of the QC. The last enters the output of the device in the faucet.

Via I96, I101, LZ 112, OR 10, the UPR-K trigger (Tg UPR-K0 118) is installed in G along the middle front of the UPR-A (Tg UPR-K0 118), which through OR 123 is used as: Ignal UPR-K arrives at the ISK-d. (Indeed, the zero output of Tg KOH.KAN.100 -) is high, a single output of 2 Tg (ON.OBM.116 is high, KK is low).

UPR-A and RAB-A are reset from the front edge of the UPR-K in the zhonchi mode, and the last rear edge of the latter is via I119: Tg UPR-Ko 118 is thrown, which corresponds to -} corresponds to the INF-K reset (the END-KA-CHAL trigger- Tg CON.CAN.100 is located in O, at the control input of the switch Km111 - - (a high level, and at the output of the last - a high (E).).

Let us now consider the reading mode on EPMC 11 and writing to the subscriber (see Figs. 7a, 6.9).

The initial sampling (preparation) differs from that described above only in that. that on RE 136 signals are READ, Thu.

The transmission mode is that from the 5th subscriber an INF-A signal is received, which is an information request.

The I132 input receives high levels from the secondary school 136 (Th), from the inverse arm of 2 Tg KON.OBM.116 and the INF-A signal from the subscriber.

0 At the I132 output, a 24t OD signal is generated, which arrives at BS113. Simultaneously with this signal with Pr KOM. 135 receives the port number (2 No. 1 - J) from which the read is performed.

5 In this case (as in the previous one), 2 UPR Km 66, 67 is at a high level (mode two has been decoded), and at the 2 WHT signal 2, information from OPMP11 is read.

0 With a certain delay determined by LZ 140, INF-K is generated through OR 142, which arrives at ISK-d. The amount of delay is determined by the end of the process of reading from memory. Via AND 105, OR

5 115 information read from the memory is transmitted to the SHIN-Kk and then to the subscriber.

After some time determined by the subscriber, INF-A from the subscriber reappears. This continues until the transfer array is read.

In this case, in the BSP 13, an END OF EXCHANGE (CO) signal is generated. Through OR 98, AND 107 is set to 1 2 Tg.KOH, OBM.116. By the next signal

5 INF-A instead of INF-K, UPR-K will be developed. Indeed, the And 132 circuit is blocked by a low level from the zero arm of 2 Tg KOH. OBM. 116. Through I95 it is established in 1 Tg KON.KAN.100, which through OR

0 100 will install in GTGUPR-Ko112. Km 111 on control switches to the second input and on the trailing edge of INF-A Tg UPR-Ko 118 is set to 0. which is equivalent to resetting the UPR-K signal.

5 From the trailing edge of the UPR-K in the termination sequence, it is set to 1 UPR-A and the information CHANNEL FINISHED (CC) is displayed on SHIN-Ao.

Via LH KK 133. W 138, LZ 141. OR

0 142 is produced by INF-K. The quenching of Tg VBR-K is carried out similarly to the previous one.

In FIG. 10 presents an example of conc. multiple port assembly

5 memories (OPMP 11).

Here, OP1, OP2, .... OP are random access memory blocks.

The information inputs, as well as the outputs of all the RAM blocks, are interconnected respectively and are the information input and output of evil.

In each block of random access memory access address (1 R. AD, 2 ADR., .., j ADR), sign of access by record

13P,) and the sign of appeal for

tendency (1HT, 2HT, ..., J4T).

Strictly speaking, the node under consideration is a multi-port operational memory by record, because information from a common information input can be simultaneously recorded in each memory block.

Claims (1)

The technical effect is to increase the performance of the system (compared with the prototype) due to the fact that the sorting of vectors is performed in hardware in one pass. In addition, the proposed device allows working with faster subscribers, as well as matching the interfaces of the latter both in type and in data transfer rate with the channel used. SUMMARY OF THE INVENTION A data sorting device comprising first to fifth switches, a standard memory unit, first and second input registers, a comparator, a decoder, and AND element, the first information input of the device coming from the channel connected to the first information inputs of the first and of the second switch, to the information input of the first register and to the first input of the And element, the first input of the device data attribute output from the channel is connected to the first information input of the third switch and to the second input for the And element, the output of which is connected to the decoder input, the output of the first switch is connected to the information input of the second input register, the outputs of the first and second input registers are connected respectively to the information input of the reference memory block and the first input of the comparator, the second information input of the device coming from the subscriber is connected to the first information input of the fourth switch and to the second information input of the first switch, the second input of the device data attribute, coming from the subscriber connected to the first information input of the fifth switch, the outputs of the second, third, fourth and fifth switches are connected respectively to the first information output for the device subscriber, to the first data flag output for the device subscriber, to the second information output for the device channel and to the second output data sign for device channel, characterized in that, in order to increase speed, it comprises a subscriber signal generating unit, a channel signal generating unit, a multiport memory signal generating unit and a multi-program memory unit, the output of the reference memory unit being connected to the first information input of the generating unit signals 0 multiport memory, the first output of which is connected to the second input of the comparator, the output of which is connected to the first input of the mode of the unit for generating multiport memory signals, the second output 5 of which is connected to the first inputs of the mode of the subscriber signal generation unit and the signal generator block, the outputs of the first group of the multiport memory signal generation unit are connected to the address input, read and write inputs of the reference memory unit, the outputs of the second group of the multiport memory signal generation unit they are connected respectively to the address inputs, to 5 write and read inputs of the multiport memory block, the output of which is connected to the first information inputs of the subscriber signal generation block and the channel signal generation block, the second input register output is connected to the information input of the multiport memory block, the first information input of the device, the output from the channel is connected to the second information inputs of the unit 5 of generating a multiport memory signal, a channel signal generating unit and a subscriber signal generating unit, a first input of a data attribute from a device channel is connected to the first control inputs of a subscriber signal generating unit and a channel signal generating unit, a second information input of the device coming from the subscriber , and the second input of the device data attribute output from the subscriber is connected respectively to the third information and to the second control inputs of the channel signal generating unit, the first output of the channel signal generating unit tud0 keys to the first control inputs of the second and third switches, the second output of the channel signal generating unit is connected to the first control inputs of the fourth and fifth switches, the first 5, the output of the subscriber signal conditioning unit is connected to the second control inputs of the second and third switches, the second output of the subscriber signal conditioning unit is connected to the second control inputs of the fourth switches, the third outputs of the subscriber signal conditioning unit and the channel signal generating unit are connected respectively to the first and second control inputs of the first switch, the outputs from the fourth to eighth channel signal generating unit are connected | respectively to the second information inputs of the second and third Koh re mutators, to the second and third inputs the multi-memory signal generating unit and to the output of the device interrupt sign, the input of the initial blanking sign of which is connected to the second inputs of the mode of the forming unit; subscriber and block signals generated channel signals and to the fourth input of the multi-port memory signal generating unit mode, the first, second and third outputs of the decoder are connected respectively to the third information input of the subscriber signal generating unit, to the fourth and fifth information inputs of the channel signal generating unit, outputs the fourth to ninth subscriber signal generating units are connected respectively to the write-read input of the first input register, to the fifth input of the form block mode multiport memory signals, to the second information input of the fourth switch, to the second information input of the fifth switch, to the sixth and seventh mode inputs of the multiport memory signal generating unit, the ninth output of the channel signal generating unit and the tenth output of the subscriber signal generating unit using MOUNTING OR and connected to the eighth input of the mode of the multiport memory signal generating unit. / 3 & a & em / g fre. fa -S5 I with rCN Gso her vRs t I Ј § § J t I fc : V / s / ft%. Kjff / 7; / rf + jO / j 3i7 7 /% r; / rOfl3Ti Odr Offet lr-otchomlor, I §§ fltWt fT L coder-, m check, Mr. Azhrono.ham / g. b  v I WITH F 1G4Sh ± L e and -4 1 - § "H - / oa so -j y -4 CO R i i & t m / fe / I N I L / p g- cm gOD With W i : t; " fi.8 H /: .-, W. VI / W i i i i i i Gf f NT . editor N.Kol yes Compiled by A. Shafran Tehred M. Morgenthl (rma.Z f # s. / 0 Proofreader M. Andrushenko