RU1836723C - Interface for memory units check - Google Patents

Abstract

The invention relates to computer technology and can be used to control memory units. The device contains a status register, a control unit. A generator block, a shifter block, an arbiter, a control block, a counter, an address multiplexer, a register-former, a conversion unit, a data former, a decoder unit, a comparator, an error register are introduced into the device. 17 ill., Ztab.

Description

The invention relates to computer technology and can be used to control memory units using a specialized microcomputer.

The aim of the invention is to increase the reliability of control, expand the functionality and simplify the device.

In FIG. 1 shows a functional diagram of the proposed device; electrical circuits of individual blocks are presented in the following figures; figure 2 - block generators; in Fig.Z - block shifters; figure 4 - block selection mode; 5 is a control unit; figure 6 - block decoder; 7 is a fragment of the address multiplexer; in Fig.8 is a counter; Fig. 9 is a conversion unit; in FIG. 10 - fragment of the register-converter; in FIG. 11 - data generator; in FIG. 12 - a comparator; Fig. 13 is a status register; on Fig - register errors; in FIG. 15 - multipost system; in FIG. 16 is a fragment of a memory block; in FIG. 17 is a structure of a memory unit.

The proposed device (Fig. 1) contains a generator block 1, a shifter block 2, a mode 3 selection block, a control block 4, a decoder block 5, an address multiplexer 6, a counter 7, a conversion block 8, a register-shaper 9, a data shaper 10 , comparator 11, status register 12, error register 13, inputs – outputs first 14 and inputs – outputs second 15 data, inputs first 16 and inputs second 17 addresses, inputs first 18 and inputs second 19 control signals, inputs 20 errors, inputs 21 checks printed communications and accounting options, input 22 cancel regeneration, exit 23 for ishi, yield 24 reading outputs 25 errors, outputs 26 and control room space bonds, yield 27 response, block 28 outputs number, address outputs 29, -30 outputs control signals.

Block 1 of the generators (figure 2) contains an AND-NOT element with a Schmitt trigger 31, elements NOT 32-34, resistors 35, 36, capacitors 37-39, quartz resonator 40;

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ss

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with

Block 2 shifters (Fig.Z) contains a trigger 41, an AND-NOT element 42, registers 43-45.

The mode selection block 3 (Fig. 4) contains AND-NOT 46-51, NOT 52, 53 elements.

The control unit 4 (Fig. 5) comprises a multiplexer 54, 55, elements. OR NOT. 56-58, OR 59-61, AND NOT 62, NOT 63-72.

Block 5 decoders (6) contains decoders 73, 74, multiplexers 75, 76, drivers 77, 78, elements NOT 79, 80, OR 81-84.

The multiplexer 6 addresses (Fig.7) contains the same elements 85.

Counter 7 (Fig. 8) contains elements of the same name 86, 87 and trigger 88,

The transform unit 8 (Fig. 9) comprises bidirectional formers 89-92.

The register-shaper 9 (Fig. 10) contains the same elements 93.

Shaper 10 data (Fig, 11) contains the shapers 94, 95. The comparator 11 (Fig. 12) contains the element of the same name 96, the switching field 97, the element is NOT 98.

The state register 12 (Fig. 13) contains a register 99, an element NOT 100.

The error register 13 (Fig. 14) contains a register 101, the elements OR-NOT 102-105, AND-NOT 106.

The multi-post system for technologically running and monitoring memory units (Fig. 15) comprises a microcomputer 107, devices for monitoring memory units 108, verifiable memory units 109, a microcomputer interface 110 and a memory interface 111.

The memory block (Fig. 16, 17) contains groups of memory chips 112, buffer elements NOT 113 of RAS control signals, buffer elements NOT 114 of CAS control signals, buffer elements of HE 115 write signals, buffer address elements of HE 116, bidirectional shapers with honor control 117, multiplexer 118, resistor 119.

The interface 110 of the microcomputer contains the first inputs / outputs of the data 15, the inputs of the address 16, 17, the inputs 18.1, 18.2, 18.3, 19.1, 19.2, 19.3, 19.4 of the signals, respectively, byte number, word number, operation, recording, memory access, sign register , access to the register, error outputs 25, response 27, input 22 cancel regeneration.

The memory interface 111 contains inputs and outputs 14 of the data, inputs of 20 errors, inputs 21.1, 21.2 of the printed circuit check, inputs 21.3, 21.4 of the accounting options, output 23 write, output 24 read, output 26.1 control communications, output 26.2 numbers places, outputs 28 block numbers, outputs 29 addresses,

outputs 30.1-30.4 strobe of the address of the CAS column, outputs 30.5-30.8 strobe of the address of the RAS line.

The device can operate in the following modes: access to the device, memory access, regeneration, diagnostics, technological run,

In the memory access mode, operations can be performed - writing a byte, writing a word, reading. The choice of operation is determined by the signals at the inputs 18, 19, according to Table 1.

In a write operation, the byte or word number is determined by signals 18.1, 18.2,

5 according to table 2.

The write operation is performed as follows.

The memory access signal at input 19.2 through element 56 of block 4 is fed to

0 input of block 2, from the output of 2.6 of which to the input of arbiter 3.

If the device is not busy performing regeneration, the mode 3 selector is set to

5 memory and generates in block 2 signals 3.2, 3.3, 3.4, which enable the start of the shift 44. 45 block 2. In addition, the signal 3.3 enters the block decoder 5, which generates RAS signals to outputs 30. Clocking

0 shifters of block 2 are executed by a signal 1.2 from block 1 of the generators. A signal 2.10 of block 2 controls the operation of the address multiplexer 6, and a signal of 2.8 permits the output of CAS signals from block 5 to outputs 30.

5 Block 4 generates control signals 4.7, 4.8 to block 8 of the converter. The signals at outputs 4.1, 4.13 control the direction of operation of the bidirectional elements of blocks 8, 9, block 5 of decoders and

0 outputs 23, 24, which set the recording mode in the memory unit. .

The signal from output 4.6, the response goes to output 27.

The access address comes from input 16

5 to address multiplexer 6, from which it enters output 29. Multiplexer b converts the address from a parallel code into two packages with fewer bits.

The 16-bit data code through inputs 0 outputs 15, the register-shaper 9 and the conversion unit 8 is fed to the 32-bit data bus of the memory 14.

In block 8, only half of the elements 89-92 are always on, the second half 5 is in the third state. The selection of the included elements is performed by signals 4.7,4.8,

Thus, only 32 bits of data (1 word) are output to 32-bit I / O 14 per call.

Block 5 decoders at this address generates one of the RAS signals at outputs 5.6-5.9 and CAS signals at outputs 5.2-5.5.

When a byte is written, one of the CAS signals is generated for that byte (8 bits) which is written, and when a word is written, two CAS signals are generated for those bytes that are included in this word (16 bits); The choice of byte and word is determined by the signals at inputs 18.1, 18.2.

The choice of RAS signals is determined by the high order bits of the address (signals at inputs 17.1, 17.2).

Another write is made to record the remaining 16 bits.

Thus, 2 calls are required to record 32 bits,

In a read operation, blocks 1,2,3,6 work in the same way as in a write.

The decoder unit 5 generates CAS signals at outputs 5.2-5.5.

In the control unit 4, the signals at outputs 4.1, 4.13 go into a state corresponding to reading and cause a change in the direction of operation of the bi-directional elements in blocks 8, 9 and the setting of the reading mode in the memory unit.

Under the action of the signals at the outputs 4.7, 4.8, the conversion unit 8 receives 16 bits from 32-bit inputs-outputs 14 and transfers 1 bits of read data to the register-shaper 9, the recording of which is performed along the edge of the gate at the output 4.9, From the output of the register-shaper 9, the data are output to 16-bit inputs / outputs 15.

Thus, in one call, 16 bits of data are read (one word). Another read is made to read the second word. In this case, the conversion unit 8 transfers the second 16 bits from the 32-bit inputs-outputs 14 to the register-shaper 9 and then to the 16-bit inputs-outputs 15.

Simultaneously with the reception of data from inputs 20 to the error register 13 error signals are received. Moreover, error signals of those bytes that are entered in the register-shaper 9 are received. Error reception is controlled by signals 5.1, 18.2 on the elements 102-105. The entry in the error register 13 is performed on the edge of the signal 4.9, and the reset is performed on the signal 2.11. Element 106 generates a combined error signal. Error signals from outputs 13.1-13.5 are fed to outputs 25.

In regeneration mode, the device operates as follows.

Generator 31, 32 issues a regeneration request 1.1 to block 2 shifters, after which trigger 41, element 42, output 2.1 of block 2 is triggered.

If the device is not busy with accessing the memory, the mode 3 selection block is set in the regeneration state and gives a signal 3.1, which leads to the start of the shifter 43, from the output of which control signals are generated at the outputs 2.2-2.5 to the mode 3 selection block , block 5. address multiplexer 6, counter 7.

Block 5 of the decoder generates signals

5 RAS 5.6-5.9 to outputs 30. The address multiplexer 6 transmits the regeneration address from counter 7 to outputs 29.

At the end of the regeneration cycle, counter 7 is switched by signal 2.5 and prepares the next regeneration address. In the mode of canceling regeneration, low level arrives from input 22 to block 1 of the generators, which blocks the operation of generator 31, 32 and cancels the generation of requests for regeneration 1.1.

In the device access mode, the following operations can be performed: - write to the status register 12; - reading the status register.

0 Status register 12 has the following format:

(0) - a sign of device activity;

(1) is the installation location number of the memory unit;

5 (2) is the logical number of the memory block when reading;

(3) - a sign of incorrect parity when recording;

(4) - jumper control; 0 (5, 6) - jumper control;

(7, 8) - control of options for execution.

Writing to the state register 12 is performed as follows.

5 external signals are input to the control unit 4: a sign of access to the device 19.3, a call to the device 19.4 and a sign of recording 19.1.

Block 4 generates control signals 4.12, 4,13, which provide 0 data transmission from bus 15 through register-shaper 9 and entry of state into register 12. A response signal 4.6 is output 27.

Reading the status register is done as follows.

The input of block 4 receives signals 19.3, 19.4. The control unit 4 generates signals 4.1, 4.3, 4.5, 4.6. 4.9, which provide data from the state register and inputs 21 through the shaper

10 data and register-shaper 9 on. moves-outputs 15 and the output of the signal response and output 27.

In the diagnostic mode, the following operations can be performed:

-control of printed communications between con-, acts;

-control of the number of the memory unit;

-check control circuits;

-determining the variant of the checked memory location.

The control of printed communications between contacts is carried out as follows.

A predetermined code is recorded in the 4th row of the state register 12, which causes. transmitting the corresponding code from the output 12.5 to the output 26.1, which is connected to the inputs of the printed communications between the contacts of the memory unit being checked.

Then pernctpa is read and the control is 5. 6 bits of read code. In this case, the signals from the outputs of the checked printed communications are fed to the inputs 21.1. 21.2 and further through the data shaper 10 and the register-shaper 9 to the inputs / outputs of the data 15.

Printed communications are considered true when the values 4, 5 and bits of the read code match.

Monitoring the number of the memory block. The memory unit, when used as part of a computer, can have the numbers 0 or 1. The memory unit with the specified number is installed in the computer in place with the corresponding number.

The zero number of the memory block is determined by the low signal level at the output 4.10 of block 4, and the first number is determined by the low signal level at the output 4.11. The location number defines the output of the 12.6 status register.

The monitoring of the isomer of the memory unit is carried out as follows.

1. In the status register, 12 bits (1,2,3) are set to O, and bit (0) is set to 1.

2. Write to the memory of the specified code at this address.

3.Changing the code bit (1, 2) of the status register,

4. Read the specified address and control the code read.

If the code matches, bits (1) and (2) of register 12 from the memory block, the recorded code should be read, and if these bits do not match, the third state is set at the output of the memory block and the corresponding code is read.

Thus / it is verified that the memory unit remains operational only if the block number and the location number match:

Verification of control circuits is carried out as follows.

1. Write to the status register 12 1 in bits (0.3).

2, Writing a given data code to a given memory address with an incorrect parity.

3. Reading the set address and controlling the output of error signals. 0 Wrong parity is set by the outputs 4,10,4.11 of the control unit by means of element 117 in the memory unit.

The determination of the variant of the checked memory block is carried out by reading bits 5 (7.8) of the status register. In this case, the corresponding code specified by jumpers in the memory block is supplied through inputs 21.3, 21.4, data shaper 10, register-shaper 9 to output 15. Technologically, the microcomputer 107 tests the memory blocks taking into account their design.

A process run is performed as follows.

1. The memory units 109, devices 108, 5 of the microcomputer 107 are connected as part of the system (Fig. 15).

2. Write 1 to the bit (0) of the status register of device 108.1, which causes it to become active. In other devices

0 a similar bit is set to O.

3. Testing the memory block test 109.1.

4. Setting the status register of the next device 108.2 to 1 bit (0) and resetting the corresponding bit of the previous

5 devices.

5. Test control of a memory block 109.2, etc.

The decoding of the device number is ensured by setting a certain combination of jumpers in the switching field 97, according to Table 3.

Elements 31.32 can be performed on IC type 555 TL2, 33, 34 - 531 LN1, triggers 41, 88 - 531 TM2, registers 43, 44

5 - 531 IR23.99, 45 - 531 TM9, multiplexers 54-555 KP12.55- 155 KP2, 75, 76-555 KP12, 85, 118-531 KP2, decoders 73, 74-531 ID14, shapers 77, 78 113 - 116 - 555 APZ, counters 86. 87 - 555 IE19,

0 bidirectional formers 89-92 - 555 AP6, register-former 93 of type 1804 VA2, formers 94-95, -155 LP10, comparator 96-555 СП1. register 101-555 TM8, memory elements 112-565 RU7, bi-directional formers 117 with parity type 1804 VA4.

As a microcomputer 107, a SNUOP-21 stand is used (3).

The proposed device has the following advantages over the prototype.

1. Monitoring of passive memory units that do not have built-in control units in the modes of regeneration, circulation and cancellation of regeneration.

2. Control of different variants of memory units, differing, for example, by information capacity, combined in a multi-post system.

3. Monitoring of memory blocks, the bit of data of which is greater than the bit of the technological interface.

4. Monitoring printed communications between the contacts of the memory unit.

5. Reduction of equipment through the use of a combined internal bus for receiving and transmitting data, as well as by compressing the data bit of the memory block to the bit of the technological interface. .

6. Control of the logical number of the checked memory blocks.

7. Checking the memory block control circuits.

The expansion of the number of diagnostic operations and the introduction of additional modes causes an increase in the manufacturability of productions, reliability and maintainability of the units under test, as well as a decrease in the complexity of production.

Claims (1)

SUMMARY OF THE INVENTION An interface device for monitoring memory units, comprising a status register, a control unit, the first output of which is connected to a control input of a status register, which is intended to increase reliability control, simplification of the device and expanding the scope by expanding the number of diagnostic operations and introducing additional operating modes, the generator block, the shifter block, the mode selection block, the decoder block, the address multiplexer, the counter, the conversion block are introduced into it The register, shaper, data shaper, comparator, error register, the second output of the control unit is connected to the control inputs of the conversion unit and the register-shaper and is the read output of the device, the first output of the status register is the output of the device location number and connected to the input of the data shaper, the group inputs of which are the inputs for checking printed communications and taking into account device variants, the outputs of the data shaper are connected to the information inputs of the status register. the inputs and outputs of the conversion unit, the information inputs and outputs of the register-driver group, the inputs / outputs of which are the first inputs and outputs of the device, the inputs and outputs of the conversion unit are the second inputs and outputs of the device, the third output of the control unit is connected to the control inputs of the register-driver and with the first control input of the error register, the information input of which is the device error input, the error register output is the device error output, the third error register input OK connected to the first output of the shifter unit and the first control input of the control unit, the second control input of which is connected to the first output of the decoder unit and the information input of the register error, the second control input of which is connected to the third input of the control unit, the first input of the decoder unit and is the first control input of the device, the fourth input of the control unit is the second control input of the device, and the fifth is connected to the output of the comparator, the first input of which is connected to the fourth output of the control unit and the third input of the data generator, the fourth input of which is connected to the second output of the status register and the sixth input of the control unit, the fifth output of which is connected to the fifth input of the data generator, the second input of the decoder unit and is the write output of the device, the device regeneration cancel input is the input of the generator unit, the output which is connected to the first input of the shifter unit, the second input of which is connected to the sixth output of the control unit, the seventh output of which is the output of the Response device, the eighth output is the number of the device block, hell the address input of the address multiplexer is the first the address input of the device and is connected to the second input of the comparator, the third input of which is connected to the third input of the decoder unit and is the second address input of the device, the output of the control whose signals is the second output of the decoder unit, the fourth input of which is connected to the output of the mode selection unit and the third input of the shifter unit, the second output of which is connected to the input of the mode selection unit and the fifth input of the decoder unit, the third output of the shifter unit is connected to the counter input, the output which is connected to the information input of the address multiplexer, the control input of which is connected to the fourth output of the shifter unit, the output The address multiplexer is the output of the device address. Table table 2 Table 3 generator unit 1 FIG. 1 1836723 2/22 23 30 block 2 sdigateli W J with m cm cm School from 11 tin with g /; from 18.1 D 5.1 dtl: c; lff. with lu C / 2.2 control unit 4 of FIG. 5 .Na0,23 -On 11  Naz At 17 -New on 8 On the. 9.13 cm NW S 13 s 3.3 Bad 5 dashchf / for / ora 6 On the. No. 5 On Sh. M7 On 30.8 From 25 5  WITH -4R Counter 7 Fig. 8 cp8 cbn with L7 with 1W-Ш6 syz cb7 with 1W7 CHES with W c. .25 - 1431 CW3 with 8 block 8 1836723 ST P cg 87 7.5 t " 5 ST gz Na9.P Number 4 tkri with s jo r s and s 45 Fragment of the register-former 9 Fig. U with IG C 72.2 C 72-3 C 71.4 C / 2.5 C. C 4.3 C2P C2.2 C 2U s 27. SL.G S.Z Shaper 10 dvmy 11 Ј "" Haft Comparator 11 FigL with ml Multiple System FIG. 15 Status Register ft HatS Error register 73 Fig. Щ with P swag + SS A fragment of the memory block 109 Fig.1b toft at 20 With ash From 24 G 1 1 The structure of the lacquer block / and FIG. 7 SZO.G SZO.Z with ZO4 I