RU1835604C - Multiple-channel analog-to-digital converter - Google Patents

Abstract

The invention relates to the field of information and measurement technology and can be used in systems for collecting and reducing the redundancy of transmitted information from a large number of analog sensors. To increase the speed, a subtractive counter, a first and second AND elements, an OR element, an NOT element, and a pulse shaper are introduced in a device containing a group of comparators, a clock generator, a totalizing counter, a digital-analog converter, a group of triggers. 1 ill.

Description

The invention relates to the field of information-measuring technology and can be used in systems for collecting and reducing the redundancy of transmitted information from a large number of analog sensors,

The purpose of the invention is to increase speed,

The drawing shows a functional diagram of the device.

The device contains a group of comparators 1 by the number of input channels, a control unit made on a clock generator 2, an element 3 and a pulse shaper 4, a totalizing counter 5, a subtracting counter 6, an element NOT 7, a group of flip-flops 8, a digital-to-analog converter 9, an OR element 10, the second element And 11.

The device operates as follows.

The start signal arriving at the control input of generator 2 allows the appearance of clock pulses at its output, which, through the And element, arrive at the summing input of counter 5. The state of counter 5 displays the value of the high order group of converted input quantities. Information from the outputs of the summing counter 5 is supplied to the inputs of the higher bits of the digital-to-analog converter A / corresponding to the counter bits of the same name. which output is a reference signal.

The obtained reference voltage is supplied to the second inputs of the group of comparators 1, and the processed continuous signals are fed to the first. If the reference voltage does not exceed the values of the input signals, then the totalizing counter 5 continues to increase its state with the arrival of each subsequent clock cycle. Accordingly, at the second inputs of the group of comparators, new values of the reference value are formed. If the reference voltage exceeds one or more input

(L

WITH

00

with

01

0

about

yelling

quantities then trigger the corresponding ones. comparators. At the same time, the output of the OR element 10, through the inverter 7, receives a ban on the second input of the And 3 element and a permission on the second input of the And 11 element. In the counter 5, the code of the high-order bits of the converted values is generated, and clock pulses are input to the subtracting counter b. As a result, a decreasing code and, correspondingly, a decreasing reference voltage are generated at the output of the counter with a discreteness of lower bits.

When the shutdown thresholds previously triggered by the comparator are reached, the outputs of the corresponding triggers generate prohibition signals for comparison to the comparator group, and information can also be transmitted to the corresponding parallel processing channel or to the dispatch device in case of using a serial transmission channel.

When all previously activated comparators are turned off, an output is generated at the output of the OR 10 element, which transfers the circuit to its initial state, that is, permission to pass clock pulses to summing counter 5 and prohibition of subtracting counter b is applied, while subtracting counter b is set to the initial state / at the outputs of the counter - high level signals /. This procedure is repeated until a signal arriving at the shaper and indicating the end of the information conversion cycle for all h channels is detected at the overflow output of the totalizing counter 5. Next, the signal from the output of the driver sets the triggers to their initial state. Also, by this signal, a start signal can be removed, by which the generator 2 is blocked until a new polling cycle occurs.

Claims (1)

The claims A multi-channel analog-to-digital converter containing comparators according to the number of conversion channels, the first inputs of which are the corresponding input buses, the second inputs are connected to the outputs of the digital-analog the converter, and the outputs are connected to the first inputs of the corresponding triggers, the outputs of which are the output recording buses, respectively, the second inputs are connected to the first output of the block control, the second output of which is connected to the input of the first counter, the information outputs of which are connected to the first inputs of the digital-to-analog converter, respectively, the second counter, characterized in that, in order to improve performance, OR, NOT, the first AND element, the second counter are inserted into it is made subtracting, and the control unit is made on the second element And, a clock and a pulse shaper, the output of which is the first output of the block and the output bus of the end of the cycle, and the input is connected to the first a counter, the information outputs of which are the high-order bus, the first inputs of the first and second elements AND are combined and connected to the output of the clock generator, the output the first element And is connected to the first input of the second counter, the outputs of which are connected to the second inputs of the digital-to-analog converter, respectively. are the low-order output bus, and the second input of the second counter is connected to the second input of the second AND element and connected to the output of the element NOT, the input of which is combined with the second input of the first And element and connected to the output of the OR element, the inputs of which are connected to the outputs of the respective comparators, the third inputs of which are connected to the outputs of the corresponding triggers, the output of the second AND element is the second output of the control unit, the input of the clock generator is a start bus. 3awu 1