RU1818666C - Valve convertor reference code generator - Google Patents

Abstract

The invention relates to a conversion technique. The purpose of the invention is to improve accuracy. The valve converter reference code generator comprises an uncontrolled frequency divider, a clock source, a controlled frequency divider, a conjunctor, a computational unit, a network comparator, a counter, a delay unit, a register. 2 ill.

Description

The invention relates to the field of converter technology and is intended for use in microprocessor control devices for network driven gate converters.

The aim of the invention is to increase accuracy.

In FIG. 1 is a structural diagram. devices.

The clock source 1 is connected to a controlled frequency divider 2, the output of which through a connector 3 is connected to an uncontrolled frequency divider 4. The second input of the connector 3 is connected to the output of a clock source 1. The output of an uncontrolled frequency divider 4 is connected to the clock input of the counter 5, the output of which is removed a reference code. Register 6 is connected to the output of counter 5, and the output of register 6 through the computing unit 7 is connected to the control input of the controlled frequency divider 2. The network comparator 8 is connected to the clock input of register 6 and through the delay unit 9 to the installation input of counter 5. In FIG. 2 is a timing diagram illustrating the operating principle of the device, where 10 are the output pulses of the clock source 1; eleven -. output signals of a controlled frequency divider 2; 12 - signals at the output of conjunctor 3; 13 - signals at the output of an uncontrolled frequency divider 4; 14 - reference signal at the output of the counter 5 in the form of a weight equivalent; 15 - mismatch signal at the output of register 6 (weight equivalent); 16 - signal comparator network 8.

The principle of operation of the device is as follows. At the maximum network frequency, the controlled frequency divider 2 does not generate clock pulses and does not block the conjunctor, so that all pulses of the clock pulse source 1 pass to the input of the uncontrolled frequency divider 4, which divides the frequency of the source 1 f0 by K0 times. The output pulses of the uncontrolled frequency divider 4 switch the counter 5, at the output of which a reference code Kop is generated. During the network period, a reference signal is generated whose step length is K0 times the period of the clock source 1.

Ј

00

00 0

DS

about

When the network frequency changes at the moment of natural switching t fixed by the comparator of network 8 (diagram 16), the reference code is not equal to zero (diagram 14). The signal Kop at time t is equal to the Krasus mismatch signal, with negative values being fixed in the additional code and positive values in the direct code (Fig. 2). The mismatch signal from counter 5 is transferred to register 6, and after the interval specified by the delay node 9, all bits of the counter 5 are set to a single value. The Krasus signal is input to a computational unit that calculates the division coefficient Ku of the controlled frequency divider 2. The controlled frequency divider 2 selects one of the Ku pulses of the clock source 1 (diagrams 10 and 1.1), the extracted pulse from the output of the controlled divider of frequency 2 on the conjunctor 3 blocks the passage of one of the pulses of the clock source to the input of the uncontrolled frequency divider 4 (chart 12), then the Kop stage is extended and equal to (K0 + 1) periods of the clock source 1 (chart 13 and 14). As a result of these corrections, the mismatch is eliminated.

A controllable frequency divider should form on the K + 1 period

L (K + 1) L (K) + KoKpacc (K) K0 2 “race (K)

pulses, then the division coefficient calculated by the computing unit 7 is equal

k Ku - g -------,

Ј Beauty (k)

where A about snK0) is a constant, fc is the network frequency.

During each operation of the counter 5, the computing device enters the Crass mismatch signal and accumulates the sum of these signals taking into account the sign from the beginning of the operation of the device to the current moment. To reduce the computation time, function tabulation may be used.

The proposed device allows to increase the accuracy of operation of microprocessor phase control devices with changes in the network frequency, the impact on the duration of the steps of the reference code is minimal, the hardware cost of implementing the device is small.

Claims (1)

SUMMARY OF THE INVENTION A valve converter reference code generator comprising an uncontrolled frequency divider, a clock source connected via a controlled frequency divider to the first input of a conjunctor, a computing node whose output is connected to a control input of a controlled frequency divider, a network comparator and a counter characterized in that, in order to increase accuracy, a delay node and a register are introduced, the clock source being connected to the second input of the conjunctor, the output of which is through an uncontrolled the frequency divider is connected to the clock input of the counter, the installation input of which through the delay node is connected to the output of the network comparator and the clock input of the register, the input of which is connected to the output of the counter, and the output to the input of the computing node, and the computing node is made implementing the dependence Ku -Ј-- -----, where (tsnomK0) - konI Kras (k) stanza, fc is the network frequency, f0 is the frequency of the clock source, K is the division coefficient of the uncontrolled frequency divider, Krasé is the mismatch signal. At IS sixteen . ± - ua. Z