RU1817248C - Device for correcting errors in two fibonacci codes - Google Patents

Abstract

The invention relates to computer technology and can be used to correct errors. The purpose of the invention is to increase the speed of the device. The goal is achieved in that the device further comprises, from the first to the fourth, EXCLUSIVE OR elements and corresponding communications. The proposed device can be used to build highly reliable electronic devices for storing and processing information in systems with high reliability requirements, and can also be used in systems with a high level of interference. 1 ill.

Description

The invention relates to computer technology and can be used to correct errors of fibonacci 2-codes.

The purpose of the invention is to increase speed.;

The goal is achieved in that for the case and, the device containing the first to eighth elements AND, the first and second elements OR, and the outputs of the second and third elements AND are connected respectively to the first and second inputs of the first element OR, the outputs of the fifth and sixth elements And connected respectively to the first and second inputs of the second element OR additionally contains from the first to fourth elements EXCLUSIVE OR. wherein the first input of the device group is connected to the first inputs from the first to the third AND elements and is the first output of the device group, the second input of the group of which is connected to the second input of the first AND element, with the first inputs of the first EXCLUSIVE OR element and from the fourth to the sixth AND elements, the third input of the device group is connected to the second inputs from the second to fourth AND elements, with the first inputs of the second element EXCLUSIVE OR, the seventh and eighth elements of AND, the fourth input of the device group is connected to the third inputs the first and second AND elements, with the second inputs from the fifth to the seventh AND elements, with the first input of the third EXCLUSIVE OR element, the fifth input of the device group is connected to the third inputs from the third fifth of the AND elements, with the second input of the eighth AND element and with the first input of the fourth EXCLUSIVE OR element, the first to fourth outputs of the EXCLUSIVE OR elements are respectively from the second to fifth outputs of the device group, the sixth input of the group of which is connected to the third inputs from the sixth to eighth elements AND is the output of the sixth group, the outputs of the fourth and seventh AND gates connected to the (L

00 4

g

00

responsibly with the third inputs of the first and second elements OR, the outputs of the first element AND, the first and second elements OR, the eighth element AND are connected respectively to the second inputs from the first to fourth elements EXCLUSIVE OR.

Any natural number in the n-bit dnrm of the fibonacci p-code is represented as a polynomial

A-i aspo (S) (1)

where a5Ј {0,1}

pp (S} -p - Fibonacci number (p 0,1, ...)

{О for n О 1 for n 0 #V (S-1) + p | j (S-p-1) The error correction method in the Sth bit is described by the Boolean function:

(2)

ri (s) a (S-p + i) a (S) a (S + J)

where a (S) is the binary coefficient of the S-ro bit;

) a single error correction signal such as the transition O to G

i 0, ... p-1; J i + 1, ... p

The essence of the invention lies in the implementation of formula (2) for p 2 and p 8. It should be noted that since the p-lower order bits of the code are not processed by the device, the two least significant bits of the code are excluded from the device.

The drawing shows a diagram of the proposed device.

The proposed device contains three-input elements AND 1.1-1.8, elements OR 2.1, 2.2, elements EXCLUSIVE OR 3.1-3.4, information inputs AND and information outputs 5. Three-input elements AND 1.1-1.8 are designed to generate error correction signals, and elements IL AND 2.1, 2.2 are intended to combine these signals. The elements EXCLUSIVE OR 3.1-3.4 are intended to correct errors that have occurred at inputs 4 and to generate the correct code combination at the outputs 5 of the device. The introduced elements satisfy the criterion of significant differences.

The device operates as follows. Suppose that the input of the device is presented with the representation of the number 5 in 2 - the Fibonacci code-00100100. This combination, entering the corresponding inputs of the elements AND 1.1-1.8 in no case gives the output of the elements AND a unit potential, i.e. About through the elements OR 2.1, 2.2 and directly from the outputs of the elements AND 1.1, 1.8 is supplied to the first inputs of the elements EXCLUSIVE OR 6.1-6.4, to the second inputs of which the potentials of the controlled code are supplied, which in this case pass to the output of the device without changes. Suppose that in the fourth bit, a failure occurred such as the transition O to 1 and the code combination took the form 00110100. In this case, the And 1.1 element will work, because unit potentials of the third, sixth, and fourth bits, respectively, were applied to all its inputs. The unit potential from the output of AND 1.1 goes to the first input of the EXCLUSIVE OR 3.1 element, to the second input of which

5, 1 distorted fourth bit arrives. At the output of the EXCLUSIVE OR 3.1 element, there is a zero potential, which will pass to the output of the device, thus correcting the error that has occurred.

0 Similarly, a failure is corrected in the fifth digit. In this case, the AND element 1.2 and 1 is triggered through the OR element 2.1 and is fed to the first input of the EXCLUSIVE OR 3.2 element, where it corrects

5 The error that occurred is of the first order. If the controlled code combination had the form 00100010, a failure of the fifth category will cause the AND 1.3 element to trigger and then, similarly, through the OR 2.1 element, the operation of the EXCLUSIVE OR 3.2 element will be triggered. Similarly, a fault of the fifth category will be fixed in the case of the code combination 00010010, only this time the AND element 1.4 is triggered.

5 Thus, the proposed device fully retains the ability of the known device to correct part of one-time errors such as the transition O to 1. Improving performance is achieved in

0 by reducing the number of intermediate elements.

The proposed device can be used to build highly reliable electronic storage devices and

5 information processing in systems with high requirements for reliability, and can also be used in systems with a high level of interference.

Claims (1)

The claims 0 Device for correcting errors of 2-Fibonacci codes, containing the first to eighth elements AND, the first and second elements OR, and the outputs of the second and third elements AND are connected respectively to 5 by the first and second inputs of the first OR element, the outputs of the fifth and sixth AND elements, respectively, with the first and second inputs of the second OR element, characterized in that, in order to improve performance, it contains the first to fourth EXCLUSIVE OR elements, wherein the first input of the device group is connected to the first inputs from the first to third AND elements and is the first input of the device group, the second input of the group of which is connected to the second input of the first AND element, with the first inputs of the first EXCLUSIVE OR element and the fourth to the sixth AND element, the third input of the device group is connected to the second inputs from the second to fourth AND elements, with the first inputs of the second EXCLUSIVE OR element, the seventh and eighth AND elements, the fourth input of the device group with it is one with the third inputs of the first and second elements AND, with the second inputs from the fifth to the seventh elements AND, with the first input of the third element EXCLUSIVE OR, the fifth input of the device group is connected to third inputs from the third to fifth elements AND, with a second input of the eighth element AND and with the first input of the fourth element EXCLUSIVE OR. exits the first to fourth elements EXCLUSIVE OR are respectively the second to fifth outputs of the device group, the sixth input of which is connected to the third inputs with sixth through eighth elements AND and is the sixth output of the device group, the outputs of the fourth and seventh elements AND are connected respectively to the third inputs of the first and second elements AND, the outputs of the first AND element, the first and second OR elements, the eighth AND element are connected respectively to the second inputs of the first to fourth EXCLUSIVE OR elements.