SU1571798A1 - Multioutput majority device for correction of arithmetical errors - Google Patents

Abstract

This invention relates to automation and computing. The purpose of the invention is to simplify the device. The device contains correction nodes 1 and majority elements 2, the number of device steps equals the number of bits of words applied to the device, each level consists of three correction nodes and a majority element. The device corrects both type 2 + ^I errors and type -2 ^I errors. The introduction of majority elements allows refusing independent correction chains for errors like +2 ^I and -2 ^I. 2 Il.

Description

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The invention relates to computing and can be used to improve the reliability of arithmetic devices.

The aim of the invention is to simplify the device.

Figure 1 shows the structural diagram of the two stages of the device; 2 is a block diagram of the correction node.

The device contains correction nodes 1, majority elements 2, first 3, second 4, third 5 inequality elements, first 6 and second 7 AND elements, OR 8 element and has inputs for receiving the first word (9) a ;, a; and , the second word (10) ag, a, a, (2, the third word (11) a,, a, information outputs 12 a, a; 1 g, / a (- ъ correction nodes of the i-th stage, the second control inputs of 13 nodes, the correction, the inputs 14 of the reception of the correction signal Cor - + | / and the outputs 15 of the correction signal Cor,;.

The principle of operation of the device is based on the correction of errors of type +2 1 (or -2), caused by spurious transferences or the absence of transferences in words arriving at the inputs of the device.

The device works as follows.

The inputs of the correction nodes 1 receive words with arithmetic errors. The correction begins with the lower bits, the signals a0: without changing, are sent to the information outputs of the correction nodes 1, i.e. a0, - and 0. From the output of the majority element, the correct value of the signal a0 is removed if at least two signals are correct. When an error is detected in one of the words, the signal Cor is formed, which is fed to the correction unit 1 of the next bit of the given word. At the information output of the next bit correction node, we get the signal a -j a,, Kop (1j Signals aj, go to the majority element of its bit, at the output of which a signal a is generated. Nodes 1 analyze the signals at the control inputs, the input of the reception of the correction signal, the information input and form, when

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the correction signal to the node of the next bit of the word. This is how the arithmetic errors in all bits are corrected in succession.

Nodes 1 perform the following functions: correct errors caused by transfers from previous bits, before sending signals to the majority element 2, generate correction signals for an error in this bit, and transmit a correction signal that is received at the input of node 1, if conditions of this transmission.

The economic efficiency is that the introduction of major elements into the device eliminates the need for independent correction chains (for errors of + 2L type and errors of -21 type) and, therefore, significantly reduces the number of elements used.

Claims (1)

Invention Formula A multiple output majoritarian device for correcting arithmetic errors, containing n correction steps, each of which consists of three correction nodes, the information inputs of the first, second and third correction nodes of all steps are connected to the corresponding device inputs for receiving the first, second and third informational controlled words about tl and- t it is so that simplify the device, a group of majority elements is entered into it, the inputs of each of which are connected to the information outputs of the correction nodes of the corresponding level, and the outputs are the device outputs and connected to the first control inputs of the correction nodes of their level, the second control inputs of which are connected to the information inputs, and the inputs of the correction signal - with the outputs of the correction signal of the same correction nodes of the previous stage, the inputs of the correction signal of the correction nodes of the first stage dklyucheny bus logic zero, wherein each correcting unit comprises first to third elements nonequivalence, first and second AND gates and an OR gate, a first input of the first ele51 the inequality is connected to the information input of the correction node and the first input of the second inequality element, the second input is connected to the second control input of the correction node, and the output is connected to the first inverse input of the first element AND whose direct input is connected to the input of the correction node of the correction node, the second input the second element of inequality and the inverse input of the second element And, the second 717986 inverse input - with the direct input of the second element I, the output of the third element of unequality, the first input of which is connected to the output of the second element of unequality and information output of the correction node, and the second input - to the first control input of the correction node, the inputs of the OR element are connected to the outputs of the AND elements , and the output - with the output of the correction signal of the correction unit. five ten FIG. 2