SU1691893A2 - Device for shifting information with checking - Google Patents

Abstract

The invention relates to automation and computing and can be applied in high-performance digital information processing devices. The purpose of the invention — an increase in the reliability of the control — is achieved by analyzing the output information with zero input information. In the device for shifting information with the control containing block 1 shift, shaper 2 mask code, block 3 elements AND, blocks 4-6 addition modulo two, element AND, entered the element OR NOT 21, element OR 22, the second element AND 23 and corresponding functional relationships. 1 ill.

Description

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The invention relates to automation and computing, can be applied in high-performance digital information processing devices and relates to the improvement of the device according to the author. St. No. 1297116.

In the drawing there is a device diagram.

The device contains a block 1 of a shift driver 2 of the code code, a block of the elements I, the first, second and third blocks 4-6 addition modulo two &, the first element Vi 7, the input 8 of the device data, the input 9 of the number of device shifts, the input 10 of the shift direction of the device input 11 of the device shift type, input 12 control bits of the device, senior bit 13 of the device data, low bit 14 of the number of device shifts, first, second and third control inputs 15-17 of the device, respectively, output 18 of the device data, output 19 of the remote bit size roystva, the first output device 20 errors OR-NO element 21, an OR gate 22, the second element 23 and the 1/1 second output device 24 errors.

The first control input of the generator 2 of the mask code and the first control input from the engine are the input 9 of the number of device shifts, the second and third control inputs of the generator 2 of the mask code are the first and second control inputs 15 and 16 of the device, respectively, the output of the former The 2 mask codes are connected to the first input of the 3 I block, the second input of which is connected to the information input of the shift unit 1, the second and third control inputs of the shift unit 1 are inputs 10 and 11 of the direction and type of device shift, respectively Actually, the output group of the shift unit 1 is connected to the input group of the first addition unit 4 modulo two and is the output 18 of the device data, the output group of the first addition unit 4 modulo two is connected to the first input of the third addition unit 6 modulo two and with output 1E the control bits of the device, the input 12 of the control bits of the device is connected to the first input of the second addition unit 5 modulo two, the second input of which is connected to the output of the block 3 And elements, and the third input is connected to the output of the first element L 7, the first input 13 ne The first element AND 7 is the highest bit of the input data of the device, the second input 14 of the first element AND 7 is the youngest bit of the number of device shifts, the third input 17 of the first element And 7 is connected to the third control input 17 of the device, the output of the addition block 5 is module two is connected to a second input of modulo-two adder unit 6, the output of which is the first error output device 20,

an input group of the element OR 22 is connected to a group of outputs of the shift unit 1, the output of the element OR 22 is connected to the second input of the second element AND 23, the output of which is the second output 24 of the device error, the first input of the second element AND 23 is connected to the output of the element OR NOT whose output group is connected to the information input of the shift block.

The device works as follows.

The input 8 of the device data and the input of the shift unit receive information for performing a logical, arithmetic or cyclic type in the shift unit.

0 shifts. The inputs 9, 10, 11 of the device receive signals that set the shift unit to perform a certain number of shifts to the right or left and the type of shifts, respectively. Similar signals

5 are fed to the inputs of the mask code generator. The value of the number of shifts at the input 9 of the device and the value of the control signals at the inputs 15 and 1 b of the device at the output of the shaper 2 forms the corresponding code, which is then sequentially multiplied in block 3 with the binary code of the input information of the shift 1. As a result, the output of block 3 receives only those bits of the input information of the shift block 1, which should be pushed as a result of performing a shift operation in the device. When shifting to zero bits, as well as cyclic shift all bits of the input

The information of the device is saved, therefore, the output of the mask code generator 2, and, consequently, the output of the block 3 of the elements I, must also form a binary code consisting of all zeros. i

5 Shaper 2 mask codes can be implemented on the ROM according to the corresponding truth table. In this case, the inputs 9, 15, and 16 of the device form the address address of this ROM. Below is a table

0 explaining the functioning of the imaging unit 2 mask code for the case. In this case, it is assumed that when you shift to the left, the direct code of the number of shifts is fed to the input 9 of the device, and when you shift to the right, 5 is optional.

In block 5, the modular addition of two two groups of terms is carried out. The first group of terms is formed by bits (parity), related to certain groups of bits (for example, to bytes) of the input information of the device. This group of terms is fed to the first input of the unit 5 from the input 12 of the device. The second group of terms is formed by the outputs of the block of 3 elements AND (these outputs receive the values of those bits of the input information of the device that must be pushed in the process of performing a shift operation in it.) The third input of the block S from the exit of the first element I 7 is given a signal that takes into account the parity of the units being moved when the arithmetic shift to the right is performed in the device. This signal is equal to one only when you the arithmetic shift to the right is filled by an odd number of bits of a negative number (in this case, single signals are present at the inputs 13, 14 and 17 of the device), the output of block 5 forms the value of the predicted result parity.

With the help of the first modulo 2 addition unit 4, the formation of the actual parities for the groups of spars (for example, bytes) of the output information of the shift unit 1 is carried out. The values of these parities are fed to the output 19 of the device as control bits of the result. The same parities come in the third block 6, where they modulo two are added to each other and to the value of the predicted parity of the result and where their equality is checked. When the values of the actual and edited parities of the result do not match, an error signal is generated at the output 20 of the device.

Below is an example of a shift in the device byte A of information A132333435363738 with one check bit K, which supplements it to parity.

Suppose that in the device it is necessary to perform an arithmetic shift in the control of information A 31E2az34a5as3r by tp and discharge to the right, it is assumed that the most significant bit is 31-digit and. the control bit K, the input 9 of the number of shifts is the binary code 101, which is the complement of the code 011, the inputs 10, 11 of the device receive signals that set up block 1 to perform an arithmetic shift to the right in it, to the first and second control inputs s 15 and 16 of device 10 is supplied to the code, tuning generator 2 for a code mask for the shift to the right information, the third

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the control input 17 of the device is given a logical unit signal.

As a result, the value of

A1-Sha1E23ze4a5. which arrives at output 1 of the device as its result. The value of A1 is used in the first block 4 of the modulo two addition to form the actual parity of the Kf result in accordance with the expression E I © I 32 31 32 32Fzz®34® -5 (the Kf value is output to the device 19 as the control bit of the result). At the output of the imaging unit 2, a mask code is generated.

5 00000111, and at the output of block 3 of the elements I, the result is formed of LLC Oooaatev, which is equal to the value of the group of nominated bits in the initial information A. With the help of the second block 5 addition modulo

0 two, the value of the predicted parity of the Kp KFaE © atFa8 © 1 result is formed, where 1 represents the parity of the units moved in the right shift (one is formed at the output of the first element And 7). In third

5, modulo two addition block 6 compares the actual parity value Kf of the result with the predicted parity value Kp of the result, based on which the output 20 of the device is generated or not

0 generated error signal.

Similarly, the operation of the device can be considered for those cases where the information received at the input 8 of the device is accompanied by several 5 control bits (for example, each byte of the input information is accompanied by its own control bit).

If the input device data 8 is fed to shift the zero information, then

0 the output of the element IL1L-HE21, which performs the function of the zero-code decoder, appears a high level of voltage, which is supplied from the first input of the second element And 23. If the shifter is working

5 is correct, then on its output group (regardless of the signals at the inputs 9-11 of the device) there appears zero information that goes to the input group of the element OR 22, At the output of the element OR 22

0, a low voltage level appears that goes to the second input of the element 23, causing the appearance at its output and output 24 of a low voltage device, which indicates the absence of

5 error signals, if the shift block is working incorrectly and its group of outputs contains non-zero information in one or several bits, in this case, the output of the OR 22 element will result in a high voltage level that goes to the second input of the AND 23 element , causing the appearance at its output and output 24 of a high voltage device, which indicates the presence of an error in the operation of the shear unit.

The device allows to increase the reliability of the control unit shift by analyzing the output information with zero input information.

Claims (1)

The invention of the device for shifting information with control on the author. St. No. 1297116, distinguishing the function table of the mask code generator O 0 Under cyclic shift It is so that, in order to increase the reliability of the control, an OR-NOT element, a second AND element and an IL AND element are entered into it, the input group of which is connected respectively to the output group of the shift block, and the output to the second input of the second element And, the output of which is the second output error of the device, and the first is connected to the output of the element OR NOT, the group of inputs of which is connected to the information input of the shift block. 00000000