SU1363310A1 - Information shift device - Google Patents

Abstract

The invention relates to computing and may be when 13/4. FIG. 1 is changed in high-performance digital information processing systems, the control of the games is organized by parity. The purpose of the invention is to increase the reliability of the device (goal. The goal is achieved by the fact that the device contains an element 4, a block of elements 5 and 2 and two blocks of modulo-2 adders with corresponding connections, which perform the parity check of the original and processed information. the control is corrected information and its output to the outputs of the device 13, 14, 15. 3 Il./5 s 00 05 CO 00

Description

The invention relates to computing technology and can be applied in high-performance digital information processing systems, the control of which is organized by parity.

The aim of the invention is to increase the reliability of the device.

Fig, 1 shows a structural diagram of the proposed device for shifting information; Fig. 2 is a functional diagram of the block of I elements; FIG. 3 is a functional diagram of the second addition unit modulo two.

The device contains a cyclic shift unit 1, a shaper 2 of a mask, a result shaper 3, an element 4, a block of 5 elements I, the first 6 and a second 7 blocks of modulo-two adders, information inputs 8 of the device, inputs 9 of the number of device shifts, inputs 10 type of device shift, device shift direction input 11, device control input 12, device information outputs 13, device check output 14, device error output 15, first information input 16 FROM device information inputs 8, which are senior The discharge, the first input 17 of the inputs 9, the number of shifts of the device, is the youngest bit.

As a cyclic shift unit 1, nptiMSHeH can be any of the known single-ended combination shifters. Allowing to make a cyclical shift of information, for example, to the left. The right shift is provided by supplying from inputs 9 the number of device shifts to the control inputs of the cyclic shift unit 1 of the additional code from the number by: - which information needs to be shifted.

The shaper 2 of the mask code is designed to generate correction signals necessary for the arithmetic or logical shift of information in the device to be inserted. In addition, the mask code generator 2, in conjunction with the block 5 of the elements I, is intended to select those bits in the input information of the device that must be set up in the process of performing a shift operation in the device. According to the value of the number of shifts at the inputs of the device 9 and

five

0

five

0

five

0

five

0

five

the value of the control signals at the inputs 10 and 11 of the type and direction of the device shift, respectively, at the direct outputs of the mask code generator 2, a n-bit masking code is formed (the n-bit width of the shifted information), which later in block 5 is randomly multiplied with the binary the input information code of the device. As a result, the output of the block 5 elements AND receives only those bits of the input information of the device that must be inserted as a result of performing a shift operation in the device (when shifted by zero times the rows, as well as under cyclic shift, all bits of the input information of the device are saved, therefore, at the direct outputs of the generator 2 of the mask code, and consequently, at the output of the block 5 of the elements I, a binary code consisting of all zeros is formed. The former 2 of the mask code forms a masking code, inverse to the one obtained at its direct outputs.

Block 5 of the elements And contains two two-input And 18- (in this case), the first inputs B of these elements are the inputs of the second group of the block 5 elements And, the second inputs 19 are the inputs of the first group of the block 5 elements I.

The result shaper 3 is designed to finally form the result. It can be implemented on I-YPI elements.

With the help of the first modulo 2 addition unit 6, the actual parity of bit code information (or even parity of groups of bits, for example, bytes) of the result generator 3 is formed. The values of these parities are fed to the control output of the 14-device as control bits of the result. The same parities enter the second block of the 7-modulo two,

In the second block 7, modulo two four terms are added (the case is considered when one check bit is used). At the input 20 of the first group of block 7, the actual parity of the result bits from the output of the first block 6 is added modulo two. The inputs 21 of the second group

31

block 7 receives the values of the outputs of the 5-element block I (these outputs receive the values of those bits of the input information of the device that must be pushed in the process of performing a shift operation in it). The fourth input 22 of the unit 7 from the output of the element 4 is given a signal that takes into account the parity of the moving units when the arithmetic right shift in the device is performed to a negative number. This signal is equal to one only when an arithmetic shift to the right by an odd number of digits of a negative number is performed in the device (only in this case there are single signals at the first 10, second 11, third 16 and fourth 17 inputs of the element 4) , The third input 23 of block 7 receives the check bit (parity) of the input information from the control input 12 of the device. Thus, in the second block 7 of addition modulo two, the predicted parity of the result is compared with the actual one. In those cases When they do not match, at the output of block 7, which is the output 15 of the error of the device, an error signal is generated.

The control of the operation of the proposed device is based on comparing the values of the predicted and actual parities of the result. The value of the predicted parity is formed by adding modulo two in block 7 values of the control, bit of input information (or control bits of the input information, for example, the parities of its bytes) and the values of those bits that must be set in the shift process. This is done using the mask generator 2 and the block 5 of the elements I. The actual parity of the result is formed at the outputs of the first addendum block 6 modulo two in the form of the total parity of the result or in the form er, the parities of its bytes. A comparison of the actual and predicted parities of the result occurs in the second block 7 of the addition modulo two. The parity prediction is performed for all bits of the result together, and therefore the predicted parity of the result must be compared with the fact

g 15 0 5 Q

.

five

five

0

five

104

parity of all bits of the result.

In the proposed device there is a hardware control covering the performance of all types of shift (arithmetic, logical, cyclic). The volume of the control equipment in the proposed device is small and amounts to about 20% of the volume of the main equipment of the device.

Claims (1)

Invention Formula A device for shifting information containing a cyclic shift unit, a mask code generator, a result generator, the outputs of which are information outputs of the device, inputs of the direct and inverse mask codes of the result generator are connected to the direct and inverse outputs of the mask code generator, respectively, the shift control inputs of which are the inputs of the device’s shear control and are connected to the inputs of the shear control of the result generator, the input of the shear direction of which is the input of The device shifts and is connected to the shift direction input of the mask code generator, whose information inputs are the number of device shift inputs and connected to the number of shifts of the cyclic shift block, whose information inputs are device information inputs, and the first information input is connected to the input the sign maker of the result P1, whose information inputs are connected to the outputs of the cyclic shift unit, characterized in that, in order to increase the reliability of the device, it The element And, the block of elements And, two blocks, modulo two adders, the inputs of the first block of modulo two adders are connected to the outputs of the result generator, and the output is the output of the check bit and connected to the first input of the second block of modulo adders, output which is the output of the device error, and the second input of the second block of modulo-two adders is connected to the output of the block of elements And, the first group of inputs of which is connected to 513633 the direct outputs of the mask code scanner, and the second group of inputs are connected to the information inputs of the cyclic shift block, the third input of the second block of modulo-two adders is the control input of the device, and the fourth input is connected to the output of the AND element, the first input of which is RedOctor L. Veselkovska Compiled by S. Korolev Tehred L. Oliiyyk Order 6370/46 Circulation 588. Subscription VNIIPI State Committee of the USSR for inventions and discoveries 1130S5, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, Projecto st., 4 It is connected to the input of the SD code mask generator, the second input is connected to the shift control inputs of the mask code generator, the third input is connected to the first information input of the cyclic shift unit, and the fourth input is connected to the first information input of the mask code generator. Fig.Z Proofreader M.Maksimishinets