SU860335A1 - Device for correcting errors in discrete data - Google Patents

Description

(54) DEVICE FOR CORRECTING ERRORS IN DISCRETE INFORMATION The invention relates to telecommunications and can be used in many channel information transmission systems. A device for correcting errors in discrete information is known, which contains an error locator, the outputs of which are connected to the corresponding decoder inputs and the corresponding inputs of the OR element, as well as adders for the number of bits in the correction code block .l. However, the known device provides the correction of only one error and does not allow Loëvol to detect and correct errors in M adjacent binary bits. The purpose of the invention is to improve the correction ability by correcting errors in groups of adjacent bits of a correction code block. To achieve the goal of a device for correcting errors in discrete information, containing an localizer, the outputs of which are connected to corresponding inputs of a decryptor H with corresponding outputs of the element OR, as well as adders for the number of {bits in the correction code block | dag, additional adders about the number of check bits in the correction code block and key blocks for h the bits in the correction code block; the inputs of the adders are combined with the corresponding inputs of additional adders, the outputs of which are connected to the corresponding inputs of the localizer and the corresponding signal inputs of the key blocks, the control inputs and outputs of which are connected respectively to the corresponding outputs of the decoder and corresponding inputs of adders, and the error localer consists of OR elements by the number of check bits in the correction block for the code. The drawing shows a structural electrical circuit of the proposed device. , -, The device contains adders l -.- l, additional adders 2, 22, ..., 2 |, 3 errors localizer, consisting of the elements OR 4jj, 42 / ..., 4 decoder 5, element OR 6, blocks 7, tji .. 7 keys. The device works as follows. On entering the input input buses, a correction code in each additional adder 7, the corresponding test ratio is checked by adding and subtracting the corresponding P-ary bits. As a result, in each additional adder 2jj, 2l, ..., 2.1, the value of the OU is fixed if there is no single error in the specified bits, and the error value with its sign in the opposite case, At the output of each element OR 4 localizer 3 appears signal O, if the value O is received in the additional adder 2ij, and signal 1, if this value is different from zero. If at the output of at least one element OR 4 of the localizer 3 appears, the element OR forms a signal of the presence of an error. In addition, the set of signals at the output of the elements OR 4, .... 4 localizers 3 indicates the number of the failed digit. This number (J) is fed to the input of the decoder 5 and Tia its signal (unlocking unit 7j) of the keys appears at its corresponding {Jth) output. In this case, the value of j-ro (distorted) P-ary bit goes to the inputs of the corresponding adder li from the input buses, and the error value in this discharge to the others from the outputs of the additional adder 2 | through block 7; keys. In the adder Ij, the error value is subtracted from the value of the distorted bit (or added to it depending on the sign with which the error was obtained), with the result that the corrected value of this bit is formed at the outputs of this adder Ij. In other adders 1 corresponding to: non-expanded bits, the inputs receive only the values of these bits from the input buses, which are transmitted to the output without change, since the corresponding blocks of 7 keys (except 7j) are locked with signals from the outputs of the decoder 5.

For example, instead of the correct code combination 02211E1, the combination of 0221101 is received, i.e. there is a distortion of the sixth left of the P-bit digit (zero), instead of the binary combination 11 in this discharge of the received combination 00, which corresponds to a binary error (M-2 ). Checking the control ratios in additional adders 2c, 2 J, (modulo 4) gives, respectively, the values 1-1-0-1 -1-3.2-2-0-1 -1 3.0, instead of 1 - 1 - 3 - 1 0 2-2-3-1 0, 0-2-1-1 0 N & The presence of non-zero results at the outputs of cyNwaTOpoB 2, 2 causes the output of signals

OR 4jf, 42 of the localizer 3 and the inputs of the decoder 5 receives a binary code 110, indicating the number of the source & bit (6). A signal appears at the sixth output of the decoder 5.

1, which opens a key block, and in the Ig accumulator, the value of the distorted sixth bit (0) is added to the error value from the outputs of the additional adder 2 e (3). As a result, the corrected value of the sixth bit (3) appears at the outputs of adder 1. The remaining bits are passed on the output bus res changes.

If an error occurs in bits 1, 2, 4, corresponding to the test bits x, y, z, then in this case the value of the error in the corresponding additional adder (, 2) is obtained with a sign of the same sign. Therefore, in the adders 1., 1, 1 with

correction is performed by the subtraction operation, not the addition.

The technical and economic advantages of the proposed device consist in its higher correction ability, since it can detect and correct errors of multiplicity M in the corresponding P-ary bits of the code, while the device is faster than correcting devices that correct the errors of multiplicity M and built on the basis of successive shift registers with forward

connections, as it requires less clocks for correction. The arithmetic adders used in the proposed device are commercially produced as a single integrated circuit (e.g., a four-bit arithmetic logic unit), so that it is. has high adaptability.

Claims (1)

1. US patent I 3623155, CL 340146 .1, 1971 (prototype). f-- f f f f f