SU437219A1 - Cascade Decoder - Google Patents

Description

(54) DECODING DEVICE OF CASCADE CODE

one

The invention — a decoding device combining the functions of an error corrector and a decoder — can find application in telecontrol and communication systems.

The well-known cyclic code correctors on the RING controlled shift registers, which, in addition to decoding, can correct erasures and detect errors, cannot correct errors.

Also known are decoder-correctors of cyclic codes on ring-controlled control shift registers, which allow to correct errors. However, in such devices, with an increase in the number of correctable errors, the number of controlled shift registers increases linearly.

The purpose of the invention is construction of simple decoder-correctors with error correction.

The proposed decoder cascade code, in the first and second stages of which cyclic codes are used, as well as the well-known decoder-correctors, are not used for ring controlled shift registers, but only an insignificant additional equipment is needed for error correction, which practically does not depend on the number correctable errors.

This is due to the fact that the first stage code is used to detect errors (combinations of the first stage code

with errors found, are erased, and the second stage code is used to correct these erasures). The advantage of this decoding algorithm is that the decoders on the ring controlled shift registers used as decoders for the first and second stage codes allow the equipment to detect errors at no additional cost to the equipment.

(at the first stage of decoding) and correct erase (at the second stage of decoding).

In the proposed device, the outputs of an annular first stage decoder through two-input OR circuits, the second inputs of which are connected to the inverter output, are connected to inputs of the same name: the second stage annular decoder, the inverter input is connected to the output of a multiple input circuit OR,

the inputs of which are connected respectively to the outputs of the first stage ring decoder.

The drawing shows a decoder circuit diagram of a -stage (9, 4) code with a minimum code distance d-4 that corrects all single errors and detects all double errors.

The device consists of a ring decoder 1 binary (3, 2) code of the first stage, consisting of information; macioc inputs 2

and 3, two-input And 4-7 circuits and the binary cells 8-11 shift register; a logical decoding stage 12 of the decoding stages, consisting of a four-input circuit "OR 13, an inverter 14 and a two-input circuit" OR 15-18; ring decoder 19 Quaternary (3, 2) -Reed-Solomon code of the second stage, consisting of two-way circuits And 20-35 and binary cells 36-51 shift register.

Ring decoder 1 is made on ring-controlled 1 shift registers that implement the following system of code rings of the binary (3, 2) first-stage code: -O-, -011-.

The ring decoder 19 is made on ring controlled register: shift axes implementing the following system of code rings of the Quaternary (3, 2) Reed-Solomon code of the second stage: -O-, -011-, -022-, -123-, -033 - -132-.

The outputs of the memory of the decoder 19 are the outputs of the device.

The frequency of the shifting pulses of the decoder 1 is three times the frequency of the shifting pulses of the decoder 19 (the tires of the shifting pulses are not shown in the drawing).

The binary symbols of the cascade code are transmitted sequentially in time and arrive: "O to input 2, and" 1 to input 3 of the ring decoder 1, where each separate code combination of the first stage with base 2 is decoded. After every 3 clocks, the result of the decoder 1 is decoded The output signals of which are the symbols of the second stage with the base 4 and fed through the logic circuit 12 to the input of the ring decoder 19, decode the second stage code in 3 ticks. In the absence of errors in the code of the first stage, the output signals of the decoder 1 pass through logic circuit 12 to the inputs of the decoder 19 without changes. When errors are detected, the zero state of all outputs of the decoder 1 is converted by logic circuit 12 to the unit states of all inputs of the decoder 19, thereby correcting erase in the second stage code.

As an example, consider the decoding process of the combination 011 100 101, which is obtained from the code combination 011 of the PO 101 as a result of one error in the second sub-block. Consider first the work of the decoder 1. The process of receiving the first, second and third sub-block is shown in Table. 1. Recall that when receiving "O, the control signal is fed to input 2, and when receiving" 1 to input 3. Before receiving the next sub-block, all cells of the decoder 1 are set to state "1 (uiHiHa settings are not shown in the drawing ).

Table 1

State of memory cells

Decoding combination

So, after receiving the first ayblock in state "1, only cell 11 will appear, which corresponds to the symbol" L in the second stage code, after receiving the second subblock, all cells will appear in state "O, which corresponds to erasing symbol S in the second stage code, and finally, after the third, Table 2

State of memory cells