RU1803882C - Phase/code converter - Google Patents

Abstract

Usage: measuring technique, phase shift measurement in a wide range of frequencies. The inventive device includes 2 input drivers (1, 2), 1 control unit (3), 1 clock generator (4), 2 keys (5, 14), 1 subtraction circuit (6), 1 switch (7), 3 AND-OR combinational elements (8, 9, 12), 1 totalizing counter (10), 1 reversible counter (11), 1 controllable subtraction circuit

Description

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The invention relates to digital measurement technology and can be used to accurately measure phase shift over a wide frequency range.

The purpose of the invention is to increase speed.

The phase-to-phase converter circuit diagram is shown in FIG. 1. In FIG. 2 a) -d) is one of the possible implementations of the control unit, timing diagrams of the operation, and a ROM firmware card; in FIG. 3 is an example implementation of a controlled subtraction scheme; in FIG. 4 a) -b) - implementation and timing diagrams of the operation of the subtraction scheme; in FIG. 5 is an example implementation of a switch.

The phase-code converter (Fig. 1) contains input drivers 1 and 2, a control unit 3, a clock generator 4, a key 5, a subtraction circuit 6, a switch 7, combinational elements 8, 9, 12 AND-OR, summing the counter 10, reversible counter 11, controllable subtraction circuit 13, key 14.

The control unit 3 (Fig. 2a) comprises an OR element 35, a counting trigger 36, a D-trigger 37, a read only memory 38 (ROM).

The controlled subtractor circuit 13 (Fig. 3) comprises a subtraction circuit 39, AND elements 40, 41, 42, OR element 43.

Subtraction circuit 6 (Fig. 4a) contains a D-flip-flop 47 and an OR element 48. Subtractor circuit 39 has a similar structure.

The switch 7 (Fig. 5) contains elements 49.50 I.

As combinational elements 8, 9 and 12 can be used, for example, integrated circuits K155LRZ.

In the phase-code converter, the control inputs of the first combinational element 8 AND-OR are connected to the bits of the first counter 10, the signal inputs to the bits of the second counter 11, the control inputs of the second combinational element 12 are connected to the bits of the second counter 11 , signal - to the bits of the first counter 10, the output of which is connected to the first input of the control unit 3, the second and third inputs of which are connected respectively to the outputs of the first and second input drivers 1, 2, the inputs of which are the inputs of the device, the first the input of the key 5 is connected to the first output of the control unit 3, the second output of which is connected to the first input of the switch 7, the second input of which is connected to the output of the subtraction circuit b, the first input of which is connected to the output of the controlled subtraction circuit 13, the first input of which is connected to the output of the second key 14, first entry

which is connected to the output of the third combination element 9 AND-OR, the control inputs of which are connected to the coefficient setting bus, and the signal inputs to the bits of the first counter 10, the input of which is connected to the output of the clock generator 4, the third and fourth outputs of the control unit 3 are connected respectively, to the second and third inputs of the controlled subtraction circuit 13, the fourth input of which is connected to the output of the second combination element 12 AND-OR, the output of the first combination element 8 AND-OR is connected to the second input at key 5, output

5 of which is connected to the second input of the subtraction circuit 6, the first and second outputs of the switch 7 are connected respectively to the addition and subtraction input of the second counter 11, and the fifth output of the control unit 3

0 is connected to the second input of the key 14.

There are two options for the operation of the converter. In the first case, the converter operates as follows. In the initial state, keys 5, 14 are closed,

5, the counters 10 and 11 are reset, the switch 7 commutes the output 30 of the subtraction circuit 6 with the summing input of the reverse counter 11. At the control inputs of the controlled subtraction circuit 13 using block 3

0 control, a code is set in which the pulse sequence kdx from the output of the AND-OR combination element 9 is supplied through the controlled subtraction circuit 13 to the input 28 of the subtraction circuit 6.

5 The studied signals Ui (t) and L) 2 (t), the phase shift between which must be measured, are supplied to the input drivers 1, 2, respectively, and converted into short unipolar pulses. The control unit 3 generates from these pulses gating pulses of duration m with a repetition period T equal to the measured phase shift. Quantizing pulses of the generator 4 clock pulses during

5 gp of frequency periods of the studied signals are fed to the input of the summing counter 10. Quantization result of m periods

fifty

X2 THT

0)

where xm is the result of quantization of one period.

At the moment of the occurrence of the overflow pulse of the totalizing counter 10 (Fig. 26), the control unit 3 supplies the control code to the inputs of the controlled subtraction circuit 13 and an increment of the pulse sequence appears at its output

dp kdx - dq,

(2)

where is the XT-increment of the pulse sequence at the output of the combinational element 12 AND-OR. The key 5 is opened. The subtraction of the pulse sequence dr | c of the output of the AND-OR combination element 8 begins to arrive at the subtraction circuit 6. At the end of the gate signal at the direct output of the counting trigger 36 of the control unit 3, the output of the controlled subtraction circuit 13 is received increment of the pulse sequence dq. The switch 7 switches the output 30 of the readout circuit 6 with the subtracting input of the reverse counter 11. After a pause at the direct output of the counting trigger 36 of the control unit 3, the trigger 37 of the control unit 3 is reset to zero, the key 5 is closed, the converter goes back to the initial state | The measurement and the measurement cycle are repeated.

By the time of reaching the frequency in the counter J10 of the value XH 2P, the input of the counter 11 received (m-1) pulse sequences, each of which contains xx Pulses and part of the mth sequence A XT. In the reverse counter 11 the number is fixed

ZH k ((m-1) xr + A xg

(3)

where: k is the dividing factor of the frequency divider formed by the counter 10 and the combinational element 9 AND-OR.

 The counters 10, 11, the AND-OR combination element 12, and the controlled subtraction circuit 13 form a number-pulse multiplier. The increment of the pulse sequence at its output is described by the relation

dq dx 2n

(4)

where n is the bit depth of the counters.

At the output 27 of the controlled subtraction circuit 13, an increment of the pulse sequence appears

dp kdx - dq

(5)

Substituting the value (4) in the expression (5) we obtain

dp

2nkdx-zdx 2n

(6)

, At the output 30 of the subtraction circuit 6, the increments of the pulse sequence are described by the expression

dZ dp - dr (7) Counters 10, 11, the combination element 8 AND-OR and the subtraction circuit 6 form a pulse-number multiplier whose operation is described by the expression

dr dZ

2n

(8)

where x is the current value of the number in counter 10 after it is full.

Substituting into the expression (7) the value of dr from the expression (8) we obtain:

fifteen

2P -1's

(9)

Given the number of pulses xn 2P, required to overflow the counter 10, the total number of pulses received at its input is determined by the expression x 2P + x1. Substituting this value in (9) we obtain:

 x

dZ

(10)

thirty

Substituting in expression (10) the value of dp from expression (6) we obtain

2n k - 2 dZ d x

(eleven)

35 Section variables and integrating the left and right sides of the expression we get

-In (2nk-Z) lnx

(12)

40 Substituting the limits of integration, we obtain

21x1

-In (2nk-Z) l lnxl

Z4x4

, n2nk-Z ln- 2nk-ZiX4

(thirteen)

(14)

50 from here

2nk-Z4 xi 2nk-Zi X4

(fifteen)

where xi xm (m-1) + xt (16) is the quantization result (m-1) of whole periods and one phase shift.

Expressing the variable Zi from expression (15) under the condition

V.

X4 2n (m-1) xT + Ax (17) we obtain the solution of differential equation (11) taking into account the initial conditions

Zi

2n k m XT

XT (m - 1) + xr

At the moment of switching the counter 11 to the subtraction mode, the control unit 3 supplies a code to the inputs of the controlled subtraction circuit 13, and the supply of the component kdx to the input 23 of the controlled subtraction circuit 13 is stopped. In this case, the operation of the converter is described by the following relationships:

dZ - - dx x

Separating the variables and integrating both sides of the equation, taking into account the limits of integration, the solution of the differential equation will look like:

X2

or subject to (1), (16) and (18)

Z2 2nk -HL

XT

Choosing the division coefficient k

360 a

-10 and installing it on the bus usta2p

new coefficient, we get in the counter 11 the result of measuring the phase shift of the studied signals Ui (1) and LJ2 (t):

and xg Z2 360-10 -,

HT

where and T. is any integer.

A second embodiment of the converter associated with the occurrence of an overflow pulse of the totalizing counter 10 is illustrated in the timing diagrams of operation in FIG. 2c. Timing diagrams at the outputs of elements 35, 36 are similar to the first case.

By the time the number in counter 10 reaches the value X4, counter m receives all m sequences of XT, i.e. it will fix the number

ZH Ch. XT- k

In the case under consideration, xi X4, zi Z4.

Substituting these expressions into expression (20), taking into account (1) and (17), we obtain the expression for Z2 similar to expression (21), i.e. the conversion is carried out in the same way as 5 in the previous step in the previous case, and the number in the counter 11 at the end of the conversion is determined by expression (22).

The technical advantages of the proposed phase-to-code converter in comparison with the basic device, which is adopted as a prototype, is to increase the speed. The prototype works in two measures. The first also counts the number 15

Ni nTxfo (24)

where n is the number of periods of the reference signal;

fo is the frequency of the pulse generator of a sample frequency of 20.

Ti PTX

(25)

(twenty)

In the second cycle, the number of 25 pulses is counted

N2 rfo,

(26)

where r is the duration of the pulses corresponding to 30 the time shift between the signal fronts at the reference and measuring inputs of the device. The duration of the second measure is equal to the duration of the first measure:

35 T2 Ti PTX

(27)

The total conversion duration is

40

T Ti + T2 2 pTx

(28)

The inventive converter perform operations similar to the operations described by expressions (24) and (26), parallel to the time

T1 PTX

(29)

Then the ratios of the conversion time of the prototype and the claimed device

 2

(thirty)

Consequently, the speed of the phase-code converter used is 2 times greater than that of the prototype.

Increasing the speed of the claimed converter will significantly expand the scope of its application.

Claims (1)

The claims A phase-code converter containing two input drivers, a clock generator, a control unit, a subtraction circuit, two counters, two AND-OR combination elements, the control inputs of the first AND-OR combination element are connected to the bits of the first counter, signal - to the bits of the second counter, the control inputs of the second combination element AND-OR are connected to the bits of the second counter, signal - to the bits of the first counter, the output of which is connected to the first input of the control unit, the second and third inputs of the cat They are respectively connected with the outputs of the first and second input formers, the inputs of which are inputs of a device characterized in that, in order to improve performance, a third combinational element AND OR controlled subtraction circuit, a switch and two keys, the first input The key is connected to the first output of the control unit, the second output of which 25 0 5 twenty connected to the first input ° mmUta ™ Ram whose second input is connected to the output of the subtraction circuit, the first input of which is connected to the output of the controlled subtraction circuit whose first input is connected to the output of the second key, the first input of which is connected to the output of the third combination I-OR whose control inputs are connected to the coefficient setting bus, and the signal inputs to the bits of the first counter, the input of which is connected to the output of the clock generator, the third and fourth outputs of the control unit are connected respectively to the second and third inputs of the controlled subtraction circuit, the fourth input of which is connected to the output of the second AND-OR combination element, the output of the first AND-OR combination element is connected to the second input of the first key, the output of which is connected to the second input of the subtraction circuit, the first and second the outputs of the switch are respectively connected to the input of addition and subtraction of the second counter, and the fifth output of the control unit is connected to the second input of the second key. I I 288C081 OP f .r