RU1800454C - Adder-accumulator - Google Patents

Abstract

The invention relates to automation and computer technology and can be used to summarize multi-bit binary numbers in parallel. The purpose of the invention is to increase speed by obtaining a partially normalized amount. The goal is achieved by introducing into each category of the accumulating adder three elements AND, two delay elements, an OR element, a BAN element. The adder also contains a trigger with a counting input, three AND elements, two OR elements, an adder modulo two. The proposed adder can be used to build a computing system with high speed and noise immunity, 1 il.

Description

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The invention relates to automation and computer technology and can be used to summarize multi-bit binary numbers in parallel.

The purpose of this invention is to increase the speed of the adder by obtaining a partially normalized sum.

In the Fibonacci number system, any natural number A is represented as a polynomial:

A 2 ai ЧЧО, where ai E {0, 1}

I 1

Oh, at i 0

4 (i) I 1, at 1 0 (1) xP (i-1) + W (i-2),.

The permitted representation is the minimum form, which is characterized by the presence of at least one zero after each unit.

For example, the number 85 can be represented as follows:

Bit weights Ґ (0 55 34 21 1385321 1 Number representation form 851 0 1 0 100010

Based on the recurrence relation (1), the proposed addition method has the form:

HHO + HHF- 4 (i + 1) + 44i - 2) (2)

00

oh oh eat

4

H (i) + 4 (i-1) HH14-1) (3)

Therefore, the addition rule has the form:

00 01 00 10 00 10 10

+ + + + + + + + bits of terms. In this case, the code

00 00 01 00 10 01 K) the amount was received in normalized form 00 01 01 10 10 100 1001me, In a number of other cases it may be

5 was obtained in an abnormal form, thus, in the proposed example, when adding the numbers A

the method of addition, in contrast to the known 01001010010 and 6 01000001001

two, the terms of the term-10 are analyzed. V0 89 55 34 21 13 8 5 3 2 1 1

Suppose you need to add the numbers A p n G.1 01000010010 and B 01000001000, then A ° «1 ° | , 1 °, °, 1 °,

+ m i i

B O AND 000 0 | | 0 1i 0 0 11 V® 89 55 34 21 13 8 5 3 2 1 1 15I - --- U --- i - I

g ---, i- - -i S 10011100100 A 0 7 0 0 0 0 1 0 | 0 1 0 | . - --- -1--

4

In OM 0.0 О О О 1 | OiO 0 In both the first and second cases, −25

A feature of the proposed combiner of Fibonacci codes of the addition formobus is that it arrives with a partially normalized

carry signal in the (i + 1) th bit of the sum code.

if there is a unit in the ith bit 30, we consider the addition of the same first term and the (i - 1) th bit in the prototype of the proposed sum of the second term, resulting in the second:

Thus, to sum the numbers A and B by a known adder, seven totalization cycles and two normalization cycles are needed. In this adder, three summing cycles and two normalization cycles are needed. As a result, the average speed of the adder increases.

From the above, the addition algorithm follows:

1. The formation of the subtotal and transfer signals.

2. Summation of the subtotal and carry signal.

3. The repetition of paragraphs 1 and 2 until the intermediate amount becomes equivalent to the final one, as evidenced by the zero transfer signal,

The essence of the invention consists in the implementation of expressions (2) and (3). The functional diagram of the i-ro bit (i 1 -j-n) of the adder is shown in the drawing.

The i-ro adder (i 1 -jn) contains a trigger 1 with a counting input, elements And 2, 4, 17, 18 and 19, an element And 3 with two direct and inverse inputs, elements OR 5, 6, 23, delay elements 7, 21, 22 element BANS 20, adder 8 modulo two, input buses of the first 9 and second 10 terms of this category, input buses 24 and 25 of the first term of the (i + 1) -th bit and the second term of (i - 1) th bit 25 of the adder, input carry buses from the (i + 2) th bit 11 and from the (i - 1) th bit 12, the output of the sum of this i-ro bit of the adder 13, carry outputs in (1 + 1) -th 15 and in (-2) -th bits of the sum pa reset bus 16, the control resolution in the summing bus 26 Fibonacci notation.

The input bus 24 of the first term from the (i + 1) -th bit is connected to the first input of the AND element 17, the second input of which is connected to the control bus 26, and the output to the input of the delay element 21, the output of which is connected to the inverse input of the FORBID element 20, the other input of which is connected to the input bus of the second term of this category 10, and the output is to the first input of the OR element 5, the second input of which is connected to the input bus of the first term of this category 9, and the third to the output of the adder 8 modulo two whose inputs are connected to the input buses transfers from the (i + 2) 11th and (i - 1) 12th adder bits, which are also connected to the inputs of the And 2 element, the output of which is connected to the first input of the OR 6 element, the output of the OR 5 element is connected to the first input element And 3s two direct and inverse

inputs and to the counting input of trigger 1, the zero input of which is connected to the reset bus 16, and a single output is connected to the first input of the And 19 element and the second input of the And 3 element with two direct and inverse inputs, the inverse input of which is connected to the input of the And 19 element and the output of the element And 18, the first input of which is connected to the input bus 25 of the second term from the (1 - 1) -th bit, and the second input to the control bus 26, the output of the element And with two direct and inverse inputs 3 is connected to the second input of the element OR 6, the output of which is connected to the input of the element LCD 7, the output of which is connected to the first input of the OR element 23 and to the first input of the AND 4 element, the other input of which is connected to the control bus 26, and the output is the transfer output to (i

- 2) th bit of the adder 14, the output of the AND element 19 is connected to the fourth input of the OR element 5 and to the input of the delay element 22, the output of which is connected to the second input of the OR element 23, the output of which is

the transfer output to the (i + 1) -th bit of the adder 15, the single output of the trigger 1 with the counting input is the sum output of this i-ro bit 13. The purpose of the elements.

The trigger 1 with a counting input is intended for adding up the terms arriving at its input, issuing and storing the result of addition.

The OR element 5 serves to form a signal arriving at the counting input of the trigger from terms and transfer signals.

The OR element 6 generates a transfer signal taking into account the signal generated from

carry signals.

Elements AND 3, AND 19, OR 23 form a transfer signal arising in a given section of the adder.

The delay elements 7, 22 are designed to delay the transfer signals from a given bit by the amount of time required for the triggers to transition to a steady state.

The modulo adder two 8 forms

of the transfer signals, the signal involved in the addition.

Element And 2 forms from the transfer signals a transfer signal to adjacent bits.

The delay element 21 is intended to coordinate the time of arrival of the second term of the given category to the first term from the (i + 1) th digit.

The element PROHIBIT 20 allows the passage of the second term of this category in the absence of the first term in the (i + 1) th digit.

Elements And 4, And 17, And 18 allow the passage of terms from adjacent bits and the transfer signal to the (i - 2) th bit when summing numbers in a Fibonacci number system.

Introduced new elements and connections constitute significant differences of the proposed adder from the prototype and lead to increased performance.

The device operates as follows.

A signal is applied to the reset bus 16, which sets the triggers 1 of all bits to the zero state. The terms are supplied to the parallel inputs of the adder bits sequentially in time, the time interval between the arrival of two numbers being sufficient for generating the transfer signals and transmitting them through the delay elements 7, 22. The delay time of the elements 7, 22 should exceed the trigger switching time and the recording pulse duration. taken together. The delay time of the delay element 20 should be equal to the time interval between the first and second terms at the adder input.

When adding the numbers in the Fibonacci number system, a signal is applied to the control bus 26, allowing the passage of terms from adjacent bits and the transfer signal through the elements And 17, And 18, And 4.

The terms of this category go through the OR element 5 to the counting input of trigger 1, and the second term passes only if the first term is absent in the (I + 1) th bit of the adder. If it is present, the signal from the (i + 1) th digit passes through the delay element 21 and locks the BAN element 20 to pass the second term of this bit, since, according to relation (3), it will be used to form the transfer signal in ( i + 1) th bit of the adder.

If there is only one transfer to any bit, the output of the adder 8 modulo two generates a single signal, which through the OR element 5 is fed to the counting input of trigger 1. When two transfer signals are simultaneously received to any bit of the adder, the modulo two is generated at the output of the adder a zero signal that does not change the state of the trigger, but the element And 2

generates a transfer signal from a given bit of the adder.

In the presence of the second term in the (i - 1) th digit, it enters through the element And

18 to the inverse input of the And 3 element, which prohibits the passage of the transfer pulse into the (i - 2) th category and to the And 19 element, which forms a single pulse only when the trigger is in

0 single state. The generated pulse is a transfer pulse in the (i + 1) th digit and at the same time transfers the trigger of this bit to the zero state. If the trigger was at zero

5 state, i.e. the first term of the given digit was absent and the carry signal did not arrive at the given digit, then the second term from the (- 1) th digit is not taken into account in the i-th digit.

Claims (1)

0 When adding the numbers represented in the traditional binary system, the control bus 26 receives a signal that prohibits the passage of terms from neighboring 5 bits through the elements M, AND 18 and the passage of transfer pulses to the lower bits through the element And 4. Claims Accumulating adder; every i Whose 0 bit (i 1,2, .. ,, n, where n is the bit of the adder) contains a trigger with a counting input, the first, second and third elements AND, the first and second elements OR, the adder modulo two and the element 5 delays, and the input transfer buses from the (i + 2) -ro and (H) -th bits are connected respectively to the first and second inputs, respectively, of the first element And and the adder modulo two, the first term 0 i-ro bit is fed to the first input of the first OR element, the output of which is connected to the first direct input of the second AND element and to the counting input of the trigger with the counting input, the zero input of which is 5 keys to the reset bus of the adder, and the single output of the trigger with the counting input is the sum output of this bit of the adder and is connected to the second direct input of the second / second element AND, the output of which is connected 0 to the first input of the second OR element, the output of which through the delay element is connected to the first input of the third AND element, the second input of which is connected to the summation enable bus in the Fibonacci 5 number system of the adder, and the output of the third AND element is the transfer output to ) -th bit of the adder, the output of the adder modulo two is connected to the second input of the first OR element, the output of the first AND element is connected to the second input of the second OR element, characterized in that, in order to increase speed by obtaining of the normally normalized sum, the fourth, fifth, sixth AND elements, the second and third delay elements, the third OR element, the FORBID element are introduced into each bit of the accumulating adder, and the first term from the (I + 1) -th bit of the adder is supplied the first input of the fourth AND element, to the second input of which a summation enable signal is supplied in the Fibonacci number system, the output of the fourth And element through the second delay element is connected to the inverse input of the BAN element, the second input of which is connected to the input bus of the first term of this 1st category, and the output of the FORBID element is connected to the third input of the first OR element, the second term from the (i - 1 )th bit of the adder is fed to the first input of the fifth AND element, the second input of which is connected to the resolution bus summing in the Fibonacci number system, and the output of the fifth element And is connected to the inverse input of the second element And to the first input of the sixth element And, the second input of which is connected to a single output of the trigger with a counting input, and the output of the sixth element And is connected to the fourth input of the first OR gate and via a third delay element - to the first input of the third OR gate, a second input coupled to an output of the first delay element and the output of the third OR gate is a transfer output (i + 1) -th bit of the adder.