RU1798801C - Device for reconfiguration of multiprocessor system - Google Patents

Abstract

Usage: in redundant computing structures. Summary of the invention: according to the number of processors, the device comprises channels (1), a synchronization and coding unit (2), 2 resistors (R), a power supply (E), a reset input (26), and an information input - output (27). Each channel contains: AND element (7), 2 OR-NOT elements (5, 6), 3 HE elements (3, 4, 8), resistor (P), power supply (E), polling input (17), polling output (18), signal

Description

entrance (19). control input (20), control output (21), interrupt confirmation input (22), interrupt output (23), failure output (24), switching output (25), interrupt and control block (9), which contains: 3 elements And (11, 12, -13), the element is NOT (10), the OR element (14), 2 triggers (15, 16).

The synchronization and coding unit 2 comprises: a group of failure inputs, a group of synchronization inputs, a synchronization output. 17-3-5-6-5-4-2-15-11-14-13-21-20-14-16-23, 17-7-18-17, 19-5-8-R-E. 19-15-5, 4-15, 4-13, 22-30, 22-12-16-23, 26-12,26-15, 2 zp f-ly, 3 ill.

The invention relates to computer technology and can be used in highly reliable multi-machine and multiprocessor systems and networks for their reconfiguration in the event of computer and processor failures.

The aim of the invention is to expand the functionality of the device by providing, interrupting a serviceable processor and then changing its instruction to execute programs in accordance with the code, failure and the possibility of use in a redundant multiprocessor system.

Fig. 1 is a diagram of a device for reconfiguring a multiprocessor system; in FIG. 2 is a diagram of a synchronization and failure coding unit; in FIG. 3 - processor failure algorithm.

The device (Fig. 1) contains a READY bus, the ends of which are connected to the first terminals of the first and second resistors R, respectively, the second terminals of the latter are connected to the voltage output of the power supply E, N channels 1, synchronization and failure coding unit 2, in each channel 1 contains a resistor R, elements NOT 3 and 4, elements OR NOT 5 and 6, element AND 7, element NOT 8 with an open collector at the output, and an interrupt and control unit 9 containing element HE 10, elements 11, 12, 13 , OR element 14 and triggers 15 and 16. Each channel has a polling input 17, polling you stroke 18, failure inputs 19, control input 20, control output 21, interrupt confirmation input 22, interrupt output 23, failure output 24, switching output 25, and the device has a reset input 26, information input-output 27. group of inputs 28 of the block failure 2 synchronization and encoding, synchronization output 29 of the synchronization and encoding unit 2, a group of synchronization inputs 30 of the synchronization and encoding unit 2.

Failure synchronization and coding unit 2 (Fig. 2) contains an AND-31 element, delay element 32, encoder 33, register 34, trunk amplifier 35. decoder 36.

The device operates as follows.

. Preliminary, a low-level signal is applied to input 26, which in each channel sets the trigger 15 to a single state and, passing through the And element 12, sets the trigger 16 to zero. As a result, a high-level signal is established at the outputs 23 and 25. A low level signal is active at inputs 19 and 22. Each channel 1 is connected by interrupt failure inputs 19 and interrupt acknowledgment 22 and interrupt outputs 23 and 25 switching with the outputs and inputs of the corresponding processor of the same name. The processor reads from the Data file the names of the programs that it must execute, and proceeds to execute them. In the event of a processor failure, a low-level fault signal is fed to the fault input 19 of the corresponding channel 1. Then, a fault, passing through the OR-NOT 5 element appears at its output as a high-level signal, since all inputs of the OR-NOT 5 element are supported low level signals, except for the input to which a failure signal from input 19. A high level failure signal from the output of the OR-NOT 5 element is supplied to the input of the OR-NOT b element and maintains a low level signal at its output. After a time equal to the propagation delay time. Through the element NOT 8, the low-level signal from the output of the latter goes to the input of the OR-NOT 6 element and to the READY bus. From the READY bus, a low-level signal is supplied to the corresponding inputs of the elements OR NOT

6 other channels 1. At the outputs of the OR-NOT elements 6 of these channels 1, a high level signal will appear that will close the OR-NOT elements of 5 channels 1, and the failure signals arriving at the -19 inputs of the latter will be blocked.

In addition, the signal from the output of the OR-NOT 5 element will pass a low-level signal through the element NOT 4 and will close the AND element

7 of this channel 1. The low-level signal from the output of the And 7 element through the polling output 18 will go to the polling input 17 of the next channel 1 and will close the And 7 element in it. The low-level signal from the last output will go through the polling output 18 to the polling input 17 of the next channel 1 and will close the And 7 element in it, etc. In each subsequent channel 1, the low-level signal from the interrogation input 17 will also pass through the HE 3 element with a high-level signal and will block the OR-NOT 5 element in the following channels 1, to the 19 inputs of which also received failure signals simultaneously with the failure signal of the previous channel 1.

The failure signal from the output of the Element NOT 4 will also go through the output 24 of the channel 1 to the input 28 of the failure of the synchronization and failure coding unit 2 and to the information input of the trigger 15 and the input of the And 13 element, closing the latter. At the output of element And 13, a voltage drop occurs, from a high level to a low, forming a trailing edge of the signal. The voltage drop from a high level to a low one from the output of the And 13 element through the control output 21 of its channel 1 will go to the control input 20 of the next channel 1. In this channel 1, the trailing edge of the signal will pass through the HE 10 element and at its output will form a leading edge of the signal. by which information from the output of AND element 11 is recorded in trigger 16.

There will be a high level signal at the output of the And 11 element if there is no low level failure signal at the input 19 of this channel 1, i.e. the processor of this channel 1 is operational. In this case, 1 will be written to trigger 16, and at its zero output, a low level signal will be generated, which will output a signal at channel 23 output. Interrupt, element OR 14 will be closed by the signal from the output of element And 11, therefore, the signal front from the input 20 will not be distributed to other channels 1.

At the output of element And 11 there will be a low level signal, if at the input 19 of this channel 1 there is a low level failure signal, i.e. the processor of this channel 1 is faulty. In this case, the trigger 16 will confirm the zero state and the interrupt signal at the output 2 of this channel 1 will not appear.

The low-level signal from the output of the And 11 element will open the OR 14 element and the trailing edge of the signal will pass through the OR 14, And 13 elements and will exit at channel 21 output to the control input 20 of the next channel 1. In that channel 1, the operation will be occur in the manner described.

Having received the interrupt signal from the output 23 of channel 1, the processor switches to the interrupt failure processing program and provides a low level interrupt acknowledgment signal to the input 22 of its channel 1. This signal will pass through the And element 12 and set trigger 16 to the initial zero state. The interrupt signal from the output 23 of channel 1 will be removed.

In addition, according to the signal from input 22 of channel 1, which will be input to synchronization input 30 of synchronization unit 2 and failure coding, the code corresponding to the channel will be generated in the latter

I, which from output 24 of the failure set its input to the input 28 of block 2. After that, from the synchronization output 29 of block 2, the synchronization signal will be written to the trigger 15 O. The low-level signal from the single output of the trigger 15 will close the AND element

II. The same signal will go to switching output 25, which will disconnect the inputs and outputs of the failed processor from the system bus. The high-level signal from the zero output of the trigger 15 closes the OR-NOT 5 element, disconnecting the failure signal of the failed processor from the input 19 of channel 1 ..

According to the service program (see Fig. 3), a failure interruption, the processor reads from the output 27 of the device from block 2 the code No failure, which corresponds to the number of the failed processor. After that, the processor forms the failed processor PROCESOR No. searches for a segment in the data file named PROCESORNo. After this segment is found, the processor transfers the program names of the PROCESOR NO segment to its PROCESOR N segment and proceeds to the execution of the programs. Thus, after a processor failure, its program is executed by a working processor, and at the same time, its programs are executed.

After the failure of all processors, except one, the latter will execute all the programs executed by the system.

At this moment, when the trigger 15 of channel 1 of the failed processor is blocked by an OR-NOT 5 element, a high-level signal will be generated at the output of the element NOT 4, which will pass through the AND elements 7 of all channels 1. and in each channel 1 at the outputs of the elements NOT 3 will generate a low-level signal that will open the elements OR NOT 5 of all of the following channels. In addition, the element NOT 8 will form a high-level signal on the READY line, which will enable all channels -1 to work, after the output of the OR-NOT 6 element displays a low-level signal that opens the OR-NOT 5 elements of channel 1. After that, the device starts to work as described.

Failure synchronization and encoding unit 2 operates as follows.

When a low level signal is received at one of the inputs 28 of block 2, the code corresponding to the number of the failed processor appears at the output of the encoder 33. According to the low-level signal supplied to the corresponding input 30 of block 2, which appears as a high-level signal at the output of the NAND 31 element, the code from the output of the encoder 33 is written to the register 34. Then, the signal from the output of the NAND 31 element passes through the delay element 32, the delay signal at the time of writing the code to the register 34, and is sent to the output 29 of block 2. The processor supplies the input / output 27 with the address code, which is decoded by the decoder 36, The output signal of the latter allows the main amplifier 35 to work through which the code failed process the litter enters the input-output 27 and is read by the processor.

Claims (3)

1. A device for reconfiguring a multiprocessor system containing a bus. Ready, the first and second terminals of which are connected to the first terminals of the first and second resistors respectively, the second terminals of the latter are connected to the output of the power source, and the number of processors includes channels, each of which contains an element And, the first and second elements OR NOT, the first and second elements NOT, the third element NOT, made with an open collector at the output, and a resistor, and the polling output of each channel is connected to the polling input of the next channel, and the polling input of the first channel is the same input of the device, in each channel the polling input is connected to the input of the first element NOT, the first output of the channel resistor and the first input of the AND element, the output of which is the polling output of the channel, the second output of the channel resistor is connected to the output of the power source, the output of the first element is NOT connected to the first input of the first element OR NOT, the output of which is connected to the inputs of the second element NOT. the third element NOT and the first input of the second OR-NOT element, the output of which is connected to the second input of the first OR-NOT element, the output of the second element is NOT connected to the second input of the AND element, the output of the third element is NOT connected to the Ready bus and to the second input of the second OR element -NOT, the third input of which is connected to the signal input of the channel, characterized in that. what. in order to expand the functionality and scope of the device by providing interruptibility a healthy processor, followed by a change in its instruction for executing programs in accordance with the fault code and use in a redundant multiprocessor system, a synchronization and coding block is introduced into it, and an interrupt and control block is inserted into each channel, and the failure output of each channel is connected to the input of the same name a synchronization and failure coding unit, the synchronization output and each of the synchronization inputs of which are connected to the same input and output of the channel of the same name, the information input is the synchronization and failure coding block is the input-output of the device and is used to connect to the information inputs and outputs of each processor, the control output of the channel is connected to the same input of the next channel, and the control output of the last channel is connected to the same input of the first channel, channel reset inputs are connected to the device input of the same name, in each channel the output of the second element is NOT a channel failure output and is connected to the information input of the interrupt and control unit, the cat input failure It is connected to the signal input of the channel, which serves to connect the corresponding processor to the failure output, the synchronization input and reset input and the synchronization output of the interrupt and control unit are single, nominal inputs and output of the channel, the failure output of the interrupt and control unit is connected to the fourth input of the first of the OR-NOT element, the switching output of the interrupt and control unit is the channel output for connecting to the switching input information and control inputs and outputs of the corresponding processor, the input and the control output of the interrupt and control unit of the channel are the inputs of the same name, the output of this channel, the interrupt output of the interrupt and control unit is the channel output of the same name and serves to connect to the interrupt input of the corresponding processor, the interrupt confirmation input of the interrupt and control unit is the same input channel and is used to connect to the output confirmation of the interruption of the corresponding processor. 2. The device according to claim 1, characterized in: in that the interrupt and control unit of each channel contains an element NOT, an OR element, first to third elements AND, and first and second triggers, the direct output of the first trigger being a switching output block and connected to the first input of the first AND element, the output of which is connected to the information input of the second trigger and the first input of the OR element, connected by the output to the first input of the second element I. The output of the last is the control output of the unit, the information input of which is inen with the second input of the second AND element and with the information input of the first trigger, the synchronization input of which is connected to the block synchronization input, the inverse output is connected to the block failure output, and the single inverse installation input is connected to the first input of the third element. And the block reset input , the second input of the third element And is the input for confirming the interruption of the block and is connected to the synchronization output of the block, the output of the third element And is connected to the zero inverse installation input of the second trigger, the synchronization input of which is union of a yield of the NOR and inverted output is output interruption unit input FIG. and of the element H E is connected to the second input of the OR element and is the control input of the unit, and the second input of the first element AND is the input of the block failure. 3. The device according to claim 1, with the proviso that the synchronization and failure coding unit comprises an NAND element, a delay element, an encoder, a register, a main amplifier and a decoder, inputs The AND elements are synchronization inputs of the block, the output of the AND gate is connected to the register enable input and the input of the delay element, the output is the synchronization output of the block, inverse encoder inputs are block failure inputs, the encoder output group is connected to the information input group main amplifier, the decoder output is connected to the control input main amplifier, the group of outputs of which and the group of inputs of the decoder form the information input-output of the block. ( /FEW ). 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