JPH0319978B2 - - Google Patents

Description

[Detailed description of the invention] [Technical field to which the invention pertains] This invention relates to a backup system in the event of an abnormality or failure (so-called abnormality, etc.) If an abnormality, failure, etc. (including these are referred to as abnormality, etc. in this specification) occurs in the system and one of the memories is replaced, the replaced memory can be used as a spare memory and can be used as a regular memory. Even if an abnormality occurs, the replaced memory can be switched and used as the regular side in a so-called bumpless (continuous manner without fluctuation) without temporarily interrupting or stopping the processing or control of this system. This relates to a backup system for such abnormal situations.

[Prior art and its problems]

Conventionally, there are computer systems that employ systems with redundant memory in order to deal with abnormalities. An information processing system having the configuration as shown can be mentioned.

That is, as shown in FIG. 1, the arithmetic processing unit 1 is connected to a common bus 7, and the common bus 7 includes a first memory 4 (MEM4) and a common memory 4 (MEM4) that are provided in redundant systems. second memory 5
(MEM5) and input/output interface unit 6
(PIOU6) is connected. The arithmetic processing device 1 then accesses the first memory 4, the second memory 5, or the input/output interface 6, transfers data between them, and executes predetermined processing or control.

Here, the arithmetic processing device 1 includes an arithmetic execution processor unit 2 (EPU2) and a bus interface unit 3 (BIU3), and the arithmetic execution processor unit 2 executes control operations for this information processing system. , the bus interface unit 3 communicates with the calculation execution processor unit 2 and the common bus 7.
control data transfer to and from

In an information processing system with such a configuration, the same data is usually stored in two memories 4 and 5, one of which is used as a regular memory and the other is used as a spare memory. be done. When an abnormality or failure occurs in the normally used memory, the spare memory is switched to and used as the regularly used memory for processing or control in the system.

Here, it becomes necessary to replace the memory in which an abnormality has occurred due to the cause of the abnormality or failure.

In this type of system, when memory is replaced, if an abnormality occurs again in the regular memory and you try to switch to the new memory and use it, the replaced memory will not be used by the system. This means that the data is not included.
Therefore, it is necessary to temporarily interrupt or stop the processing or control of this information processing system, and to input the same data into the replaced new memory as in the normally used memory.

When such processing is performed, so-called bumps occur in the processing or control of the information processing system, which poses a problem.

Furthermore, especially in the case of a plant where the object to be controlled does not allow the occurrence of such bumps or where the occurrence of bumps is a problem, such memory replacement has a negative effect on the system, which is a problem.

[Purpose of the invention]

This invention has been made in view of the problems of the prior art.In addition to solving the problems of the prior art, it is possible to use the replaced memory as a spare memory, and it is possible to use this memory regularly without bumping. The purpose of the present invention is to provide a backup system in case of an abnormality, etc., which can be switched and used as a backup system.

[Key points of the invention]

In order to achieve such an object, the present invention provides a first
and a second memory, the first,
In an abnormality backup system in which one of the second memories is used as a regular memory and the other memory is used as a spare memory for backup in an abnormality, etc., the backup is performed and the spare memory is used. When a memory in which an abnormality has occurred is replaced with a new memory while the memory is being used as a regular memory, the replaced memory notifies the arithmetic processing unit that the memory has been replaced, and receives this notification. The arithmetic processing unit copies the data in the regularly used memory to the exchanged memory, and uses the exchanged memory as a spare memory, and the arithmetic processing unit copies the data in the normally used memory to the exchanged memory, and uses the exchanged memory as a spare memory. is characterized in that it has a connector to which power is supplied when memory is replaced, detects that power is no longer supplied to this connector, and notifies the arithmetic processing unit that the memory has been replaced. It is something.

With this configuration, the replaced memory stores the same data as the regular memory, and can be switched and used as the regular memory at any time.

As a result, even if system processing or control is switched to the replaced memory side, no bumps will occur in system processing or control due to this switching, so-called bumpless switching can be performed, and system processing or control can be performed. continuity will be maintained.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of the main parts of an information processing system to which the abnormality backup system of the present invention is applied. Components that are the same as those shown in FIG. 1 are designated by the same reference numerals.

10 is an arithmetic processing unit, which includes an arithmetic execution processor unit 11 (EPU11) and a bus interface unit 12 (BIU12).

Further, 8 and 9 are first and second memories common to the redundant systems, respectively, which are accessed from the arithmetic processing unit 10 via the bus 7, and only one of them is used regularly. One memory is used as one memory, and the other is used as a spare memory.

Here, the first memory 8 and the second memory 9 are
Each has a similar configuration, including a power supply connector 13 to be connected when replacing the memory, a memory replacement completion detection circuit 14, and an interrupt signal generation circuit 1.
5.

Now, like the processor unit 2, the processor unit 11 executes control computations for this information processing system, and the bus interface unit 12 connects the processor unit 11 and the common bus 7. control data transfer. Then, the calculation execution processor unit 11
is one of the first memory 8 or the second memory 9,
For example, when an interrupt signal indicating memory replacement is received from the first memory 8, a predetermined control program is started to read the data of the regularly used memory that has not been replaced, that is, the current In this case, the data in the second memory 9 is read out, transferred to the replaced first memory 8, and the data is copied to the first memory 8 side.

Here, either the first memory 8 or the second memory 9 is used for regular use, and the other is used as a reserve. broke down,
Assume that the regular side has been switched to the second memory 9 and that the first memory 8 is replaced.

First, the abnormal or failed first memory 8 is disconnected from the common bus 7. Next new first memory 8
Power is supplied to the terminal in advance through its connector 13, and then connected to the common bus 7. After completing the connection of the common bus 7, the connector supplying power is disconnected from the connector 13 to cut off the power supply. At this time, power is being supplied to the replaced first memory 8 from the common bus 7 side.

By doing so, memory can be replaced without affecting the system.

Now, in the above case, when the replacement of the first memory 8 is completed and, for example, the connector on the power supply side is disconnected, power is no longer supplied to the connector 13. Then, the memory exchange completion detection circuit 14 detects this state in which power is no longer supplied by disconnecting the connector, and sends the detection signal to the interrupt signal generation circuit 15.

Interrupt signal generation circuit 15 receiving this detection signal
sends an interrupt signal indicating memory replacement to the arithmetic execution processor unit 11 via a predetermined control line of the common bus 7, which has been connected.

When the arithmetic execution processor unit 11 receives this interrupt signal via the common bus 7 and the bus interface unit 12, it refers to the status and writes it to the second memory 9, which is currently the commonly used memory, as described above. The data is transferred to the first memory 8 and copied.

When this copying is completed, the replaced first memory 8 is replaced with a spare memory whose abnormality has been recovered by, for example, setting predetermined status information of the first memory 8 from an abnormal state to a spare state. Thereafter, it is recognized by the calculation execution processor unit 11 as a spare memory.

Therefore, if an abnormality occurs in the second memory 9 that is currently in regular use, the first memory 9 that has been replaced
This memory 8 can be used as a regular memory.

In this way, even if an abnormality occurs in the regularly used memory and the regular use is transferred to the replaced spare memory, or even if an abnormality occurs in this information processing system, the continuity of control will be maintained. This makes it possible to continue controlling a plant, etc., in a so-called bumpless manner.

〔Effect of the invention〕

As can be understood from the above explanation, when a memory in which an abnormality has occurred is replaced with a new memory, the replaced memory notifies the arithmetic processing unit that the memory has been replaced, and receives this notification. The arithmetic processing unit that was used for regular use copies the data in the memory that is used for regular use to the replaced memory, and the replaced memory is used as spare memory. Data will be stored and can be switched and used as a regular memory at any time.

As a result, the switching of processing to the replaced memory side can be performed in a so-called bumpless manner, with no bumps occurring in stem processing or control, and continuity in system control etc. can be maintained.

Moreover, when the power supply side connector is unplugged,
Since this immediately sets and recognizes the replaced memory as a spare memory, backup in the event of an abnormality can be easily and quickly performed.

[Brief explanation of the drawing]

Figure 1 is a block diagram of the main parts of an information processing system to which a conventional backup system for abnormal situations is applied, and Figure 2 is a block diagram of the main parts of an information processing system to which the backup system for abnormal situations of the present invention is applied. FIG. 1, 10... Arithmetic processing unit, 2, 11... Arithmetic execution processor unit, 3, 12... Bus interface unit, 4, 8... First memory, 5, 9...
Second memory, 6...I/O interface, 7...
Common bus, 13...Power supply connector, 14...Memory exchange completion detection circuit, 15...Interrupt signal generation circuit.

Claims (1)

[Claims] 1 The first unit connected to the arithmetic processing unit via the bus
and a second memory, the first,
In an abnormality backup system in which one of the second memories is used as a regular memory and the other memory is used as a spare memory for backup in an abnormality, etc., the backup is performed and the spare memory is used. When a memory in which an abnormality has occurred is replaced with a new memory while the memory is being used as a regular memory, the replaced memory notifies the arithmetic processing unit that the memory has been replaced, and receives this notification. The arithmetic processing unit copies the data in the regularly used memory to the exchanged memory, and uses the exchanged memory as a spare memory, and the arithmetic processing unit copies the data in the normally used memory to the exchanged memory, and uses the exchanged memory as a spare memory. is characterized in that it has a connector to which power is supplied when memory is replaced, detects that power is no longer supplied to this connector, and notifies the arithmetic processing unit that the memory has been replaced. Backup system for abnormal situations, etc.